JPH10161938A - Disk controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the operational reliability of disk controller having a write back cache. SOLUTION: At the time of writing write data to a cache 111, these write data are simultaneously written to a SRAM memory card 112 as well and a disk backup area 122 composed of continuous prescribed data storage areas is prepared on a disk device 12 as well. When an empty area is insufficient on the SRAM memory card 112, contents on the SRAM card memory 112 are simultaneously written into the disk backup area 122. At the time of recovery from power failure, erased data are recovered from the cache 111 while using the SRAM memory card 112 and the contents in the disk backup area 122.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a disk controller, and more particularly to a disk controller having a write-back cache and controlling a disk device in response to an access request from a host system.

[0002]

2. Description of the Related Art In recent years, in order to increase access speed,
Various disk control devices having a disk cache have been developed. The disk cache is a high-speed buffer storage for temporarily holding data input / output between the host computer and the magnetic disk device, and stores a part of a copy of data on the magnetic disk. Usually, a high-speed semiconductor memory such as an SRAM or a DRAM is used as the buffer storage.

In a disk control device provided with a disk cache, when a host computer requests a disk device for read access, first the buffer storage is referred to, and if the requested data is in the buffer storage (cache hit). The data is immediately transferred from the buffer storage to the host computer without actually accessing the magnetic disk device.

If the requested data is not in the buffer storage (cache miss), block data of an appropriate size including the requested data is read from the magnetic disk device and transferred to the host computer. , Stored in the buffer storage. At this time, if there is no unused empty entry in the buffer storage, block replacement is performed according to an algorithm such as LRU. In this case, the oldest block or the least frequently used block in the buffer storage is ejected to the magnetic disk device, and the resulting empty entry stores new block data.

On the other hand, when the request from the host computer is a write to the magnetic disk device, the data is written to the buffer storage. In this case, it is necessary to reflect the contents of the buffer storage to the disk device,
There are a write-through system in which buffer storage and data rewriting of the disk device are performed simultaneously, and a write-back system in which only the contents of the buffer storage are rewritten first and data rewriting of the disk device is performed later.

Generally, since the latter method has higher performance, a write-back method is often used for a disk cache. As described above, when the disk cache is used, the number of mechanical drive operations required to access the magnetic disk device is reduced, and the access speed of the magnetic disk device is apparently significantly increased. Can be.

[0007]

However, as described above, the disk cache is composed of a volatile semiconductor memory such as an SRAM or a DRAM. Therefore, if a power failure such as a power failure occurs, the contents of the cache are lost. Are all lost. In particular, in the case of a write-back type disk cache, a serious situation such as losing the latest user data before being reflected in the disk device is caused.

The data loss of the write-back cache due to such a power failure can be solved by providing a dedicated battery for holding the data of the write-back cache in the disk control device. However, this increases the cost of the disk controller because the battery is expensive. In addition, when a battery is mounted, a large amount of mounting area is occupied by the battery, which causes a problem that the disk control device cannot be realized by one circuit board.

SUMMARY OF THE INVENTION The present invention has been made in view of the foregoing, and has been made in view of the above circumstances. Therefore, it is possible to back up write-back cache data with a simple configuration without providing a dedicated battery for holding write-back cache data. It is an object of the present invention to provide an inexpensive and sufficiently reliable disk controller.

[0010]

SUMMARY OF THE INVENTION The present invention relates to a disk control device having a write-back cache and controlling a disk device in response to an access request from a host system, which has a smaller data storage capacity than the write-back cache. A backup memory configured from a non-volatile memory, in which cache directory information of the write-back cache and write data written from the host system to the write-back cache are written; and to secure an empty area in the backup memory, Means for batch-transferring each of the write data written in the non-volatile memory to a backup area comprising a predetermined continuous data storage area on the disk device; and Using spare contents of the backup area on the disk device, characterized by comprising a means for restoring the unreflected write data to the lost and the disk device from the write-back cache.

In this disk control device, as a means for backing up data in the write-back cache, a nonvolatile memory backed up by a battery such as an SRAM having a smaller data storage size than the write-back cache is used. .

When writing write data to the write-back cache, the write data is simultaneously written to the nonvolatile memory. Also, a backup area composed of a continuous predetermined data storage area is prepared on the disk device, and if there is insufficient free space in the nonvolatile memory, the contents of the nonvolatile memory are stored in the backup area on the disk device. Written collectively. Since this writing is performed on a continuous data area, it can be performed at a higher speed than normal data writing on a disk device.

At the time of recovery from a power failure, the contents of the nonvolatile memory and the backup area are used based on cache directory information of the nonvolatile memory and the like.
Processing for restoring write data that has disappeared from the write-back cache and has not been reflected on the disk device is performed. This makes it possible to back up cache data larger than the capacity of the non-volatile memory, thereby realizing an inexpensive and sufficiently reliable disk control device.

In consideration of the failure of the disk controller, the non-volatile memory may be detached by itself, so that only backup data can be read from another device. For example, JEIDA / PCMCIA
It is preferable to use a removable memory card such as a standard SRAM card with a battery.

When such a memory card is used as a backup memory, the system is restarted while the memory card storing the write data is removed during the power-off, or the memory card used during the power-off is used. If a memory card other than the memory card is replaced,
Normal data recovery cannot be performed and there is a danger that erroneous data is written to the disk device.

Therefore, flag information indicating whether a write operation using the write-back cache is permitted and identification information unique to the disk are stored in both the disk device and the memory card. It is preferable that the apparatus further comprises means for comparing the flag information and the identification information between the memory card and the disk device at the time of recovery from a power failure to determine whether or not a correct memory card is mounted. Thus, if the memory card is accidentally replaced while the power is turned off, or if the used memory card remains removed, it is detected that the correct memory card is not installed. Therefore, it is possible to take measures such as reporting it to the host system.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a configuration of a disk controller 11 according to an embodiment of the present invention. The disk controller 11 is a magnetic disk device 1 used as a secondary storage device of a computer system.
And controls the magnetic disk device 12 in response to an access request from the CPU of the computer system, that is, the host system. The disk controller 11 is realized by, for example, one circuit board, on which a cache memory 111 and an SRAM card 112 with a battery are mounted.

The cache memory 111 constitutes a disk cache for temporarily storing read data and write data from the disk device 12, and can operate as a write-back cache. The cache memory 111 holds a data memory for holding read / write data, and cache directory information for managing which address position on the disk device 12 corresponds to data on the data memory. And a tag memory. The data memory has a storage capacity of several tens of megabytes, for example.
The power of the cache memory 111 is not backed up, and its stored contents are lost during a power failure.

The SRAM card 112 with a battery
It is composed of a PC card of the EIDA / PCMCIA standard, and can be detachably mounted on a PC card socket provided on a circuit board of the disk controller 11. This SRAM card with battery 112 is
When the cache memory 111 is used as a write-back cache, it is used as a non-volatile memory for backing up the write-back cache data, and the write-back cache data from the host system is written to the cache memory 111. At the same time, the data is also written to the SRAM card 112. The SRAM card 112 also writes various control information 113 and cache directory information 114 that is the same as the cache memory 111. SR
The data storage size of the AM card 112 is, for example, about 1 Mbyte, which is smaller than the data storage size of the cache memory 111.

The data storage area of the magnetic disk device 12 is logically divided into an area 121 (disk normal data area) for normal use and an area 122 (disk backup area) for storing a backup of write-back cache data. You. The disk backup area 122 is composed of physically continuous storage areas on the disk device 12, and when the SRAM card 112 runs out of free space, all the write-back cache data backed up on the SRAM card 112 Is the disk backup area 122
Is written all at once.

The data on the SRAM card 112 and the disk backup area 122 is used for restoring write-back cache data that has been lost from the cache memory 111 due to a power failure and has not been reflected in the disk normal data area 121 of the disk device 12. Can be

Here, the operation of the disk controller 11 during normal operation will be described with reference to the flowchart of FIG. When a host system issues a write-back cache command that is a write command that uses the cache memory 111 as a write-back cache (step S101), the disk controller 11 sets the SR
It is checked whether the AM memory card 112 has a necessary free space (step S102).

If free space is secured in the SRAM memory card 112, the write data (write-back cache data) of the write-back cache command transferred from the host is transferred to the cache memory 111 and the SRA.
After writing to the M card 112 (step S103), and updating the cache directory information of the cache memory 111 and the cache directory information 114 of the SRAM card 112, a command end report is made (step S104).

FIG. 1 shows a state in which data En is written in cache memory 111 and SRAM card 112. On the other hand, when there is no free space, the write data (write-back cache data) of the write-back cache command transferred from the host is not written to either the cache memory 111 or the SRAM memory card 112, and the disk device 12 Is written to the disk normal data area 121 (step S112).

The data written to the cache memory 111 is thereafter written to the disk normal data area 121 asynchronously with the write-back cache command. When the data is written to the disk normal data area 121, the corresponding data in the SRAM card 112 is invalidated by updating the cache directory 114. FIG. 1 shows a state in which the data of A0 to An has already been data destaged in the disk normal data area 121.

When a write-back cache command is continuously issued from the host and it is detected that there is no more space for writing the next write data in the SRAM card 112 (step S105), the disk device 12
It is checked whether or not there is a free space in the disk backup area 122 (step S106).
The data written to the RAM card 112 is collectively written to the disk backup area 122 asynchronously with the write-back cache command (step S1).
07).

As a result, it is possible to newly write the write-back cache data into the SRAM card 112. In this batch writing, the SRAM card 112
Is written to the disk backup area 122 by serial access, so that the time required to write individual write-back cache data to the disk normal area 121 as usual is much less than the total time. It is possible to execute. This is limited to the case where the data length is relatively short. However, when the data length is long, the write-back cache function itself does not exert any effect. Therefore, it is better to write the data directly to the disk from the beginning.

In FIG. 1, A0 to An, B0 to Bn, C0 to
The state where the data of Cn and D0 to Dn are backed up to the disk backup area 122 is shown. Among them, the data of A0 to An is already destaged in the disk normal area 121, so that its contents are invalid.

To invalidate the data in the SRAM card 112 and the disk backup area 122, as described above, the processing of writing the data written in the cache memory 111 to the disk normal data area 121 (steps S108 and S109). In this case, the data on the SRAM card 112 or the disk backup area 122 corresponding to the written data is invalidated by the cache directory information 114 (step S110).

When a disk write command instructing data writing to the disk device 12 is issued from the host (step S111), the write data transferred from the host is written to the disk normal data area 121, and then an end report is issued. (Step S112), and invalidates the data on the corresponding SRAM card 112 or disk backup area 122 (step S113).

When the host issues a write-back cache command for rewriting data existing in the SRAM card 112, no free space is required, and the data in the cache memory 111 and the data in the SRAM card 112 are rewritten. And reports the end of the command. When a write-back cache command that rewrites data in an area corresponding to data saved in the disk backup area 122 is issued, an end report is returned after writing data to the disk normal data area 121, and the corresponding disk is returned. The data in the backup area 121 is stored in the cache directory 11
4 is rewritten and invalidated.

Next, referring to FIG.
An operation of restoring data that has been lost from the cache memory 111 due to a power failure and has not been reflected in the disk normal data area 121 using the data in the disk backup area 122 and the disk 12 will be described.

If a power failure occurs during operation, as shown in FIG.
If the write-back cache data not written in No. 1 remains in the SRAM card 112 and the disk backup area 122, the process of copying the data to the disk address in the disk normal area 121 to which the data should be written at the next power-on is performed. Will be Which data is copied is determined by the cache directory information 114 and the control information 1 in the SRAM card 112.
13 is used.

The control information includes an SRAM card 1
12 and a data storage area of the disk backup area 122, there is provided a bank management table for managing which cache block of the cache memory 111 corresponds to the data written therein. From the cache block number of the table, the cache directory information 11
By searching "4", the disk address on the disk normal area 121 to which data should be written can be checked.

In FIG. 3, the disk backup area 1
Among the data remaining in the storage area 22, since the data A0 to An have already been written in the disk normal area 121, it is determined from the cache directory information 114 that they are invalid.
No writing is performed when the power is turned on. Data B0 to Bn
, C0 to Cn, and D0 to Dn, the disk address to which the data is to be written is checked using the bank management table and the cache directory information 114. Will be copied. The disk addresses of the data E0 to En remaining in the SRAM card 112 are checked in the same manner, and the data is directly copied from the SRAM card 112 to the disk address to which the data should be written. After copying all data to the correct disk address, the control information 113 and the cache directory information 114 are initialized.

FIG. 4 shows the structure of the control information 113 and the cache directory information 114 used for the above processing. Cache directory information 114
Is composed of entries corresponding to a plurality of cache blocks written to the data memory of the cache memory 111, and each cache directory entry is configured as shown in FIG. That is, each cache directory entry includes ordinary cache directory data (device number of a disk device to which data is to be written, LRU data including frequency information used for an LRU algorithm, a cache tag indicating a disk address, 16 Kbytes). , A management flag indicating validity / invalidity of each cache block, a start and data length for designating a valid data portion in a cache block, and a bank number indicating a data storage area where cache block data is backed up. ing.

The bank management table 113a stores the data of the SRAM card 112 and the disk backup area 12
The data of the maximum data size (for example, 64 Kbytes) that can be backed up in the SRAM card 112 is defined as one bank, and the cache block of each cache block data stored in each bank is composed of entries for managing the data of the SRAM card 112. It is composed of a plurality of bank entries each indicating a number (cache directory number). The structure of each bank entry is as shown in FIG. The number of bank entries is the sum of the number of banks prepared in the disk backup area 122 and the number of banks 1 of the SRAM card 112.

The current bank pointer 113b indicates the bank entry number of the bank management table 113a which manages the data present in the SRAM card 112, and the value of the current bank pointer 113b is the data of the SRAM card 112. When the data is backed up to an empty bank in the disk backup area 122, the value is updated to a new bank value.

In the example of FIG. 4, the cache directory 1
The bank number m is assigned to the entry of the 14 cache blocks x.
Is stored, and the bank number n is stored in the entry of the cache block y. This is an area where the actual data x of the cache block x corresponds to the bank m (in this case, since the current bank is m, the SRAM card 112
Area where the actual data y of the cache block y corresponds to the bank n (banks other than the current bank m are the disk backup area 122).
At the same time).

The cache block number x is stored in the bank m entry of the bank management table 113a.
The cache block number y is stored in the entry, and the cache block number included in each bank can be known from the bank management table 113a.

Next, when a data backup occurs, the data of the SRAM card 113 is written to an empty bank of the disk backup area 122 (or a bank in which all cache block data is invalidated), and the bank is stored in the bank. m. Further, the value of the current bank pointer 113b is updated to the number of the next unused bank entry (or the bank entry in which all cache block data is invalidated) in the bank management table 113a.

Data is read from the SRAM card 112 and the disk backup area 122 only at the time of data recovery operation, and a normal read command from the host system is not read from the cache memory 11.
1 or only data read from the disk normal data area 121 is performed.

As described above, in this embodiment,
As a means for backing up write-back cache data, an SRAM memory card 1 with a battery having a smaller data storage size than the cache memory 111
12, when writing write data to the cache 111, the write data
It is also written to the M memory card 112. Also, a disk backup area 122 composed of a continuous predetermined data storage area is prepared on the disk device 12, and if there is not enough free space in the SRAM memory card 112, the contents of the SRAM memory card 112 are stored in the disk backup area. The data is collectively written to the area 122. Then, at the time of recovery from the power failure, the SRAM memory card 1 based on the cache directory information 114 and the like.
A process for restoring write data that has disappeared from the cache 111 and has not been reflected in the disk device 12 is performed using the contents of the disk backup area 122 and the disk 12. As a result, it is possible to back up the cache data larger than the capacity of the SRAM memory card 112, and it is possible to realize the inexpensive and sufficiently reliable disk controller 11.

Further, since the SRAM memory card 112 is detachable, if the disk controller 11 fails, the SRAM memory card 112 is removed from the disk controller 11 and its backup data and cache directory information are read out by another device. Thus, the disk device 12 can be repaired.

As described above, the removable SRAM card 1
Although the use of the HDD 12 is effective as a measure against the failure of the disk controller 11, the SRAM card 112 can be easily replaced.
The system may be restarted with the RAM card 112 removed, or the SRAM card 1 in use while the power is turned off.
When the memory card is replaced with another memory card other than 12
Normal data recovery using the backup data of the RAM card 112 cannot be performed, and there is a danger that erroneous data is written to the disk device 12. In order to prevent such a problem from occurring, in this embodiment, the reliability of the backup data is maintained by the following method.

That is, a flag (WBC permission flag) indicating that the write-back cache function is used is set in the control area 123 of the disk device 12, and the SR is set only when the flag is set.
AM card 112 and disk backup area 1
It is determined that the data of No. 22 is valid. The WBC permission flag is set when a write-back cache permission command is issued from the host, and when the host issues a write-back cache prohibition command and when the system has been stopped normally, the write-back cache permission flag is set. Reset when the cache function is automatically disabled. If this flag is not set, either the system has been stopped normally or the write-back cache function is not used, and even if another SRAM card is inserted, the disk Normality can be guaranteed.

When the system is operating without an SRAM card, the WBC permission flag of the disk device 12 is always reset. Therefore, even if a new SRAM card 122 is mounted on the disk controller 11, the controller 11 Can recognize that the data in the disk device 12 is normal. Therefore, during system operation, S
Plug-and-play is possible in which the RAM card 122 is mounted and the write-back cache function is effectively activated from that point.

If the WBC permission flag is set, the SRAM card 112 at that time is set as follows.
To ensure the integrity of your data. First, in the control area of the disk 12, as shown in FIG. 7, not only the WBC permission flag but also information specific to the disk such as a serial number is stored. When the write-back cache function is used, that is, when the W
When setting the BC permission flag, the SRAM card 11
2, the same information as the disk device 12, that is, the WBC permission flag and the serial number of the disk device 12 are stored as a part of the control information 113.

When the power is turned on, such as when returning from a power failure, the controller 11 compares the WBC permission flag between the disk control area 123 and the SRAM card 112 with the serial number of the disk device 12. If they match, it can be guaranteed that the SRAM card 112 has not been replaced while the power is off.

The cache directory information 114
If a power failure occurs at the moment when critical data such as is rewritten, data may not be correctly restored at the next power-on. Therefore, in order to guarantee the normality of data, it is necessary to guarantee not only the validity of the SRAM card 112 described above but also the validity of critical data by the following method.

That is, immediately before rewriting critical data, a flag (CRITIC flag) indicating that the data is being rewritten is set in the control information storage area of the SRAM card 112.

After rewriting a series of critical data, the CRITIC flag is reset. When the power is turned on, the controller checks the CRITIC flag, and if not set, can determine that the critical data is correct. If this flag is set,
Since the data using the write-back cache cannot be guaranteed, the host is notified by a method such as prohibiting normal access to the disk data. In order to prevent the power from being shut down during the rewriting of critical data, a mechanism for notifying the controller 11 when a power failure is detected and a power supply for guaranteeing the operation until the controller 11 completes the rewriting process are provided. Auxiliary power supply to perform is required.

Since the SRAM card itself does not have a check code generation function such as a parity addition function, the reliability of data can be increased by adding a parity bit when writing the cache directory information 114.

Further, by adding a check code such as LRC to the write cache data itself, data reliability can be improved. When the power is turned on, the controller 11 can determine whether the data is correct based on the check code. However, if a power failure occurs during data transfer, there is no need to guarantee the data, and it is not necessary to recognize that the check code is abnormal even if it has an error. By the following method, it is possible to know whether or not data having an error in the check code was being transferred at the time of the power failure.

First, the DM from the main memory of the host system is
SRAM card 1 immediately before data transfer by A
The number of the cache block being transferred is written to the control information storage area of No. 12. Immediately after the data transfer is completed, the number is rewritten to an invalid value such as -1. With this method, when the power is turned on, the controller 1
Even if the block 1 detects an error in the write cache data by checking the check code, if the block in which the error is detected remains in the control information storage area of the SRAM card 112, the data is invalidated, and the controller 11 operates normally. Can be continued. If the contents of the write-back cache data are determined to be abnormal, the host is notified by a method such as prohibiting normal access to the block.

In consideration of the above points, when the power is turned on, the controller 11 executes the data reliability determination processing according to the procedure shown in the flowchart of FIG. That is, when the power is turned on, the controller 11 first sets the disk device 1
2 is read out (step S).
201), it is checked whether the WBC permission flag is set (step S202). If the WBC permission flag is set, it means that the write-back cache function was used before the power failure occurred, and the controller 11 stores the contents of the control information storage area of the SRAM card 112 as shown in FIG. Read (step S203), SRAM card 112 and disk device 1
2 is checked for a match between the WBC permission flag and the disk serial number (step S20).
4). If they match, the controller 11
It recognizes that the SRAM card 112 has not been replaced while the power is off, and that the correct SRAM card is installed,
Check whether the CRITIC flag is set,
It is determined whether or not the critical data recorded on the SRAM card 112 was being rewritten (step S205).

If the rewriting is not in progress, the controller 11 checks the parity data to determine whether the cache directory information 114 is correct (step S206). A validity check is performed using a check code for each of the other cache blocks (step S207).

If no abnormality is found in the above check, it can be determined that the write-back cache data is normal, so that all data on the SRAM card 112 and the disk backup area 122 are written to the original disk address (step S208). Then, the WBC permission flags of the disk device 12 and the SRAM card 112 are reset, and the cache directory information is initialized (step S209).

Thereafter, when the host issues a write-back cache permission command, the SRAM card 1
It is checked whether or not No. 12 is mounted (step S2).
10 to S212), if implemented, first SR
The writing of the disk serial number and the setting of the WBC permission flag are performed on the control information storage area of the AM card 112, and then the writing of the disk serial number and the setting of the WBC permission flag are also performed on the control area of the disk (step). S213, S21
4).

When the host issues a write-back cache prohibition command, all write-back cache data is written to the disk, and then the SRAM card 112 and the W of the disk control area 123 are written.
The BC permission flag is reset (steps S215 to S215).
218).

FIG. 10 shows a processing flow when rewriting critical data such as write-back cache data, a write-back cache directory, and control data.

Execution of a write-back cache command,
Alternatively, it is necessary to rewrite the cache directory information 114 of the cache block including the write-back cache data by executing a disk write command or destaging the write-back cache data, or rewrite critical data related to the write-back cache. When it is detected that the data is necessary (step S301), the parity data of the cache directory is created as follows, and the SRAM
CRIT stored in the control area of the card
The IC flag and the DMA transfer flag are rewritten.

The parity bit is added by taking the exclusive OR of the least significant bit while shifting the data of the cache directory one bit to the right, and reserves the result of the exclusive OR of all the bits and the parity check. This is performed by taking and storing the exclusive OR with the bit (steps S302 to S307), whereby the result of the exclusive OR of all the bits in the cache directory can be set to 0. The controller 11 checks the parity of the cache directory when the controller 11 is turned on. If the parity data is not 0, the controller 11 notifies the host of the added parity data by, for example, prohibiting normal access to the disk data. By reading immediately after writing, it is used to confirm that data corruption has not occurred at the time of writing.

Next, the cache directory and the SRA
Set the CRITIC flag before rewriting critical data in the control information storage area of the M card, rewrite those data, read the data when rewriting is completed, check the validity, and then reset the CRITIC flag (Step S
308-S311).

When starting the DMA transfer, the number of the cache block in which data is to be transferred is set to the SRAM card 1
12 and the cache block number is invalidated when the DMA transfer is completed (steps S312 to S315).

Next, a second example of the data normality detection processing will be described with reference to the flowchart of FIG. Here, the normality check is performed using the write cache data and the check code added to the write cache directory when no command from the host is executed even during the normal operation.
As a function of No. 12, a battery exhaustion is also reported, which is also a target of failure detection.

The normality check shown in FIG. 11 is executed by the controller 11 at regular intervals. If the battery of the SRAM card 112 runs out or a check code error is detected during operation, the subsequent command write-back is performed. The cache function is prohibited, the data in the cache memory 111 is written to the disk device 12, and the WBC permission flag is reset (steps S401 to S405). In this way, by writing the write-back cache data of the cache memory 111 that is not backed up to the power to the disk 12,
No need to lose write-back cache data. Further, since an ECC code is usually added to the cache memory 111 that is not backed up by a power supply, an error can be detected only by reading. If an error is detected, write cache data is written from the SRAM card 112 and the disk backup area 123 to the disk 12 (step S406).
To S409).

As described above, by combining the duplication of the write-back cache data and the normality check of the write-back cache data during operation, even if a memory failure or data loss occurs in the memory, normal data can be transferred to the disk. It becomes possible to write.

As a result, even if a failure occurs in the cache memory 111 or the SRAM card 112 during the operation of the system, all the write-back cache data can be written to the disk 12 without loss.

[0070]

As described above, according to the present invention, the data in the write-back cache can be backed up with a simple configuration without providing a dedicated battery for holding the data in the write-back cache. Since the function of determining data normality is added, a low-cost and sufficiently reliable disk controller can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a disk control device according to an embodiment of the present invention.

FIG. 2 is an exemplary flowchart illustrating a backup operation of write-back cache data in the embodiment.

FIG. 3 is an exemplary view for explaining a data restoration operation at the time of restoration from a power failure in the embodiment.

FIG. 4 is an exemplary view showing an example of the structure of a management table used in the embodiment.

FIG. 5 is an exemplary view showing an example of a data structure of a cache directory entry used in the embodiment.

FIG. 6 is an exemplary view showing an example of a data structure of a bank management table used in the embodiment.

FIG. 7 is an exemplary view showing an example of information of a disc control area used in the embodiment.

FIG. 8 is an exemplary view showing an example of control information recorded on an SRAM card used in the embodiment.

FIG. 9 is an exemplary flowchart showing the procedure of data normality determination processing executed by the disk control device of the embodiment.

FIG. 10 is an exemplary flowchart illustrating the procedure of rewriting processing of write-back cache data and the like executed by the disk control device of the embodiment.

FIG. 11 is an exemplary flowchart showing another procedure of the data normality determination process executed by the disk control device of the embodiment.

[Explanation of symbols]

11 disk controller, 12 disk device, 1
11: cache memory, 112: SRAM card, 1
13 ... control information, 114 ... cache directory information.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code FI G06F 12/08 320 G06F 1/00 341N

Claims (7)

[Claims] 1. A disk control device having a write-back cache and controlling a disk device in response to an access request from a host system, comprising: a nonvolatile memory having a smaller data storage capacity than the write-back cache; A backup memory in which cache directory information of a write-back cache and write data written from the host system to the write-back cache are written; and in order to secure an empty area in the backup memory, the backup memory is written in the nonvolatile memory. Means for batch-transferring write data to each other to a backup area composed of a predetermined continuous data storage area on the disk device; and, upon recovery from a power failure, the backup memory and the disk device. Means for restoring write data that has disappeared from the write-back cache and has not been reflected in the disk device using the contents of the backup area. 2. The disk control device according to claim 1, wherein said backup memory comprises a memory card which can be removably mounted on said disk control device. 3. A means for storing flag information indicating whether or not a write operation using the write-back cache is permitted and identification information unique to the disk in both the disk device and the memory card. Means for comparing the flag information and the identification information between the memory card and the disk device at the time of recovery from the power failure to determine whether or not a correct memory card is mounted. 3. The disk control device according to claim 2, wherein: 4. A means for writing a flag indicating the start of rewriting to the memory card prior to rewriting various control information of the memory card, and resetting the flag at the end of rewriting; Means for judging whether write data that has disappeared from the write-back cache and has not been reflected in the disk device can be correctly restored using the memory card, based on the state of The disk control device according to claim 2. 5. A means for adding an error detection code to the cache directory information written in the memory card, and performing error detection of the cache directory information by the error detection code upon recovery from the power failure,
3. The disk according to claim 2, further comprising: means for determining whether write data lost from the write-back cache and not reflected on the disk device can be correctly restored using the memory card. Control device. 6. A means for writing a cache block number to be transferred to the memory card prior to write data transfer from the host system to the disk control device, and invalidating the cache block number at the end of transfer. 3. The apparatus according to claim 2, further comprising: means for performing error detection using the error detection code for data other than the data being transferred by the data specified by the cache block number at the time of recovery from the power failure. The disk control device according to the above. 7. A disk control device having a write-back cache and controlling a disk device in response to an access request from a host system, comprising: a memory card backed up by a battery; A backup memory for backing up a part of the memory, in which write data to be written from the host system to the write-back cache is written; Adding means for checking error detection codes of the write-back cache and the memory card during operation to monitor operation states of the write-back cache and the memory card. Error check means, and a battery check means for detecting battery exhaustion of the memory card, and when the error check means and the battery check means detect an abnormality in one of the write-back cache and the memory card. A disk control device for writing write data stored in the other disk device to the disk device.