JP2010152747A - Storage system, cache control method and cache control program for storage - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a storage system, capable of reducing, in cache control for improving the apparent performance of the storage system from a host computer in response to increase in capacity of a storage medium such as a magnetic disk, the capacity of a battery for battery backup which is set for failures such as power supply interruption without deteriorating the apparent performance from the host computer. <P>SOLUTION: Write data from the host computer is stored in a backed up nonvolatile memory 102, and read data read from the storage medium 104 is stored in a volatile memory 103. Data corresponding to an address of write data is searched on the volatile memory 103, and when the address is present, the write data is stored in the nonvolatile memory 102 after invalidation of read data (or disposal of the cache of the address on the volatile memory) is performed. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a storage system, a storage cache control method, and a cache control program. In particular, the present invention relates to a storage system, such as a magnetic disk, which has a low speed when reading from or writing to a storage medium having a low speed and a large capacity compared to the processing speed of a host computer. A storage system for guaranteeing the data written in the cache memory from the host computer when the power is turned off in the control means of a high-speed storage medium (DRAM, flash memory, etc.) called a so-called cache memory for guaranteeing the performance of the storage medium The present invention relates to a storage cache control method and a cache control program.

  In a conventional storage system, write data from a host computer is temporarily stored in a cache memory (hereinafter sometimes abbreviated as “cache”), and when the write data is stored in the cache memory, the write data is stored in the storage to the host computer. Data seen from the host computer by writing to a medium (such as a magnetic disk) that responds to the effect of writing and then writes the write data written in the cache memory to a medium (such as a magnetic disk) that is slower but larger in capacity than the cache. Has been used to improve the write performance (referred to as the write-back cache algorithm).

  In this case, a volatile semiconductor memory (DRAM or the like, hereinafter simply referred to as “volatile memory”) is generally used as the cache, and these volatile memories have good performance, but per bit. The unit price is high, and the written data may be lost when the power is turned off unexpectedly, such as at the time of a power failure. For this reason, the data written to the cache by the write-back cache algorithm may be lost when the power is turned off. Therefore, a backup method using a battery or the like is employed.

  For example, in the disk cache device described in Patent Document 1, in order to cope with the problem that the period during which the data contents are not identical is long, and the possibility of being lost due to a failure such as a power failure is high, The time at which data was written is stored for each entry, and if there is an entry that has not been written to the disk device even after a predetermined time has elapsed from the write time, It discloses that data of an entry is written to a disk device.

Further, in the disk cache device described in Patent Document 2, a disk cache device having a volatile memory not backed up by a battery and a non-volatile memory backed up by a battery has been proposed. Read data to the host device is stored in an empty entry in the volatile memory, and for write data from the host device to the disk cache device, is there an entry for the data at that address in the volatile memory? It is disclosed that after determining whether or not the entry exists, the entry is invalidated, and if it does not exist, the write data is stored as it is in an empty entry of the nonvolatile memory.
JP-A-2-19941 JP-A-8-137753: (FIGS. 1, 3-5, paragraphs 12-13, 22-32)

  By the way, with the recent increase in the amount of information processing, the amount of data stored per storage unit continues to increase, the capacity of the built-in magnetic disk increases significantly, and the number of connected host computers also increases. ing. For this reason, the storage capacity required for the cache is also increasing. For this reason, in the conventional storage system described in the background art above, the capacity of the battery for backing up the non-volatile memory used for the cache also increases. However, the use of a battery with a large capacity has a problem in that the cost increases, and the occupied volume and weight of the battery in the storage also increase.

Therefore, in the storage system of the present invention, it is necessary as a data protection means at the time of power interruption of the above-mentioned cache (particularly a cache using a volatile semiconductor memory such as DRAM) provided corresponding to an increase in storage capacity. In addition, it has been a problem to reduce the capacity of the battery for backing up the nonvolatile memory.
For this reason, in the battery backup means performed over the entire cache in the conventional method, it has been a specific problem to reduce the battery capacity without degrading the apparent performance from the host computer.

Note that the proposal of the above-mentioned Patent Document 1 is a technique related to a disk cache device, and even if a power failure occurs, only data written within a predetermined time from the occurrence time is lost. It is possible to reduce the influence of such as. However, since the battery-backed non-volatile memory is not used as the cache memory, the loss of data cannot be prevented completely, and the effect of performing the write-back can be reduced.
The proposal of the above-mentioned Patent Document 2 is also a technology related to a disk cache device, and its purpose is similar to that of the storage system of the present invention, but only the well-known LRU algorithm is described, and protection in the event of power interruption The operation of the recovery means necessary for (backup) is not explained explicitly, and is not described at all as claims or effects.

The present invention has been made in view of the above-described conventional problems, and in a storage system, cache control for improving apparent performance from a host computer in response to an increase in storage media such as magnetic disks. In view of this, an object of the present invention is to provide a storage system that can reduce the capacity of a battery backup battery installed in preparation for a failure such as power interruption without degrading the apparent performance from a host computer.
Another object of the present invention is to provide a storage system that does not impair stored data even when a power failure occurs.

  In order to solve the above problems, a storage system according to the present invention includes a large storage device whose data input / output speed is slower than the requested data input / output speed of the host device, and data between the host device and the large storage device. In a storage system comprising a non-volatile semiconductor memory having a battery for storing memory during a power failure and a volatile semiconductor memory as a cache memory for a cache means for reducing the difference in input / output speed, a data write request is issued from the host device. When the write request data is sent, the write request data is temporarily stored in the nonvolatile semiconductor memory, and the write request data is written to the host device when the write request data is stored in the nonvolatile semiconductor memory. Means for responding a notification of completion, and reading data from the host device When a request is sent, data matching the read request is read from the large storage device and stored in the volatile semiconductor memory, and thereafter, when a data read request is sent from the host device , Means for reading out the data stored in the volatile semiconductor memory and sending it to the host device, and when the page of the data stored in the volatile semiconductor memory exists at the time of recovery from a power interruption, And a means for invalidating the page. A storage system is provided.

  In addition, the storage cache control method according to the present invention includes a nonvolatile semiconductor memory having a battery for storing memory during a power failure and a volatile semiconductor memory, and a difference in data input / output speed between the host device and the large storage device. In the storage cache control method for mitigating, when a data write request is sent from the host device, the write request data is temporarily stored in the nonvolatile semiconductor memory, and the write request data is stored in the nonvolatile semiconductor memory. At the time of storing, the step of responding to the host device with a notification that the writing of the write request data has been completed, and the data read request from the host device when the data read request is sent from the host device. Reads data that meets the requirements and stores it in the volatile semiconductor memory Thereafter, when a data read request is sent from the host device, the step of reading the data stored in the volatile semiconductor memory and sending it to the host device; And a step of invalidating the page when there is a page of the data stored in the volatile semiconductor memory. A storage cache control method is provided.

  Furthermore, the cache control of the storage according to the present invention comprises a nonvolatile semiconductor memory having a battery for storing memory during a power failure, and a volatile semiconductor memory, and provides a difference in data input / output speed between the host device and the large storage device. In a storage cache control program for causing a computer to control the cache to be relaxed, when a data write request is sent from the host device, the write request data is temporarily stored in the nonvolatile semiconductor memory, and the nonvolatile memory When the write request data is stored in the semiconductor memory, the host device responds to the notification that the writing of the write request data is completed, and when the data read request is sent from the host device, Read data that matches the read request from the large storage device. And reading the data stored in the volatile semiconductor memory and sending it to the host device when a data read request is sent from the host device. And a step of invalidating the page when there is a page of the data stored in the volatile semiconductor memory at the time of recovery from a power failure. Is to provide.

  As described above, according to the storage system of the present invention, data read from a storage medium (a large storage device such as a magnetic disk device) is stored in a volatile memory, and write data sent from a host computer is stored in a battery. By arranging it in a non-volatile memory protected by means such as backup, the storage capacity of the memory necessary for the storage system is ensured, so that the large-scale cache capacity necessary for the entire system is secured, while the battery By reducing the amount of non-volatile memory required for backup, it is possible to reduce the capacity of the battery required for backup and to prevent data loss even when a failure such as a power failure occurs.

Hereinafter, the principle of the storage system according to the present invention will be described.
The problem with the conventional storage system is that battery backup is performed for both the cache for the write data from the host and the cache for the read data from the storage medium of the storage system. Normally, the cache of read data from a storage medium (such as a magnetic disk) has data on this storage medium. Therefore, even if the cache data becomes unusable when the power is turned off, the data on the storage medium is erased. If there is an access from the host computer again, it can be expanded on the cache memory.
On the other hand, when write data from the host computer responds to the completion of writing when it is stored in the cache (that is, write-back cache), generally this data does not remain in the host computer and is stored in the cache on the storage system side. Therefore, it is a target to be protected by powering off the storage system.

  A storage system of the present invention includes a nonvolatile memory in which a semiconductor memory is battery-backed for temporarily storing write data from a host computer, and a volatile memory for temporarily storing data read from a storage medium. Write data from the non-volatile memory and data read from the storage medium (magnetic disk or the like) are arranged in the volatile memory. As a result, write data from the host computer necessary for battery backup is protected from the power failure of the system, and a read cache that does not require battery backup is arranged in a volatile memory that does not require battery backup. By configuring in this way, the battery backup of only the write-back cache that is originally necessary is performed, so that the battery capacity can be greatly reduced.

  More specifically, when a write request is sent from the host computer, there is a cache management means for determining whether the write data at the address indicated by the write request exists in the nonvolatile memory or the volatile memory. The cache management means links and manages the address of the data cached in the nonvolatile memory and the volatile memory as viewed from the host, and refers to cache management information such as a table in this management. The cache management information is arranged in a nonvolatile area that does not disappear even when the power is turned off. However, a part of the nonvolatile memory described above may be used, or a separate nonvolatile memory may be secured and used.

  Further, the cache management means secures an area for storing the write data on the nonvolatile memory if there is no data at the same address in both the nonvolatile memory and the volatile memory for the write data from the host computer, Data is stored in this area. If the data indicated by the address of the write data from the host computer exists in the nonvolatile memory, the data on the nonvolatile memory is replaced with the write data sent from the host computer. Further, if the data indicated by the address of the write data sent from the host computer is not in the nonvolatile memory and exists in the volatile memory, the data on the volatile memory is invalidated, and a new area is created on the nonvolatile memory. The write data from the host computer is stored in this area.

  In addition, when a read request is sent from the host computer to the storage system, the cache management means determines whether the data requested by the read request exists in either the nonvolatile memory or the volatile memory. If it exists in either of them, the data in that area is sent to the host computer. Otherwise, the data requested by the read request must exist in either the nonvolatile memory or the volatile memory. For example, an area is secured on the volatile memory, the data at the address indicated by the read request is read from the storage medium and secured in the area, and the data is sent to the host computer as a result of the read request.

  Note that when the power is cut off, such as a power failure, the volatile memory data is restored to the valid state on the cache management information, and the volatile memory has no actual data. The data is invalidated (that is, discarded as cache data) with reference to the contents of the cache management information, and the normal processing is restored after the power is restored.

Hereinafter, the best embodiment of the storage system of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a configuration diagram showing the overall configuration of the storage system according to the embodiment of the present invention.
The storage system according to the present embodiment shown in the figure includes a cache management unit 101 that receives write data from a host computer (not shown) and determines whether the data exists in a nonvolatile memory or a volatile memory; The non-volatile memory 102 in which the cache management information is not erased even when the power is turned off, the volatile memory 103 in which the cache management information is erased when the power is turned off, and a storage medium 104 such as a magnetic disk are configured.

Hereinafter, the operation of the storage system according to the present embodiment will be described.
The cache management unit 101 manages the cached data in the nonvolatile memory 102 and the volatile memory 103 by linking the address and data specified by the read request or the write request from the host computer. Refer to the information. The cache management information is arranged in the nonvolatile memory 102 that does not disappear even when the power is turned off. The write data from the host computer also sends the address mapped on the storage medium 104 at the same time as the write data, is temporarily stored in the non-volatile memory 102 for the purpose of improving responsiveness, and finally written to the storage medium 104. . Further, the host computer designates the address of the storage medium 104 and issues a read request. The cache management unit 101 returns the latest data indicated by the address in the storage medium 104, the nonvolatile memory 102, or the volatile memory 103 to the host computer.

  The configuration of the cache management information is shown in FIG. 2 and FIGS. 2 shows the overall configuration of the cache management information of the storage system according to the present embodiment, FIG. 6 shows the free page management information, and FIG. 7 shows the LRU of the clean cache page allocated to the volatile memory. FIG. 8 shows an LRU configuration of dirty cache pages allocated to the nonvolatile memory, and FIG. 9 shows an LRU configuration of clean cache pages allocated to the nonvolatile memory.

Hereinafter, the above-described operation will be described in more detail with reference to FIGS. 2 and 6 to 9.
The cache management information shown in FIGS. 2 and 6 to 9 exists in the non-volatile memory 102, and the stored contents are maintained even in the event of a power failure or the like. Further, the cache management means 101 described above has information on the cache entry 201 and the cache tag 202 as cache management information. The cache entry 201 is calculated from an address designated by the host computer by a technique such as hashing. If the address is the same, the same cache entry 201 is selected. Here, calculation is performed using a hash, but other equivalent methods may be used.
A pointer to the cache tag 202 is stored in each entry of the cache entry 201, and it is possible to adopt a bidirectional link structure as shown in FIG.

  FIG. 3 is a configuration diagram showing the configuration of the cache tag 202. The cache tag 202 shown in the figure includes cache information 301, a page pointer 302, an LRU pointer 303, and a tag pointer 304. The cache information 301 includes a memory type 305 of a flag indicating whether or not a page managed by a cache tag (details will be described later, but an area where data itself is stored) exists in either a volatile memory or a nonvolatile memory. Dirty information 306 and medium storage address 307. Dirty information is information indicating whether or not the data of the page is Dirty (that is, the write data sent from the host computer by write back etc. exists in the cache and has not yet been written on the medium). It is. Here, 1 is written if it is Dirty, and 0 is written if it is Clean (that is, the same data as the data on the medium exists in the cache).

The medium storage address 307 is information indicating which address on the storage medium 104 the data on the cache memory corresponds to when the write data from the host computer or the data read from the medium is temporarily arranged on the cache memory. It is.
The page pointer 302 indicates a pointer of a page which is an area where data is actually stored. This pointer is a page on the non-volatile memory 401 showing the page configuration in FIG. 4 or a volatile memory showing the page configuration in FIG. The start address of the memory of one of the pages on the page 501 is indicated.

The LRU pointer 303 is used to determine the priority order when reusing pages in a clean state when a write-back cache is flushed or a page that is a cache storage area cannot be newly acquired.
Hereinafter, a description will be given with reference to FIGS. 7, 8, and 9. FIG. 7 shows a configuration of a volatile entry when the algorithm for managing the Clean page of the volatile memory is LRU (first-in last-out algorithm or last-in first-out algorithm). The volatile entry having a configuration based on the LRU is information for managing data read from the storage medium 104 and temporarily stored in the volatile memory. The cache tag 202 has a link structure with the volatile Clean LRU entry 701 at the head.

  The LRU pointer 303a of the cache tag 202 indicates the head of the next cache tag 702, and the LRU pointer 303b has a link structure for storing the head address of the cache tag closer to the entry. The LRU pointer 303a of the last cache tag 703 of the link writes NULL (zero) which is information indicating the end of the link to indicate that it is the last tag. In addition, the LRU pointer 303b of the cache tag immediately after the entry writes the address of the entry. By taking such a bidirectional link structure, it is easy to remove a cache tag in the middle of the link. The above-described configuration is similarly adopted in the LRU that manages dirty data on the nonvolatile memory shown in FIG. 8 and the LRU that manages clean data on the nonvolatile memory in FIG. 9.

The tag pointer 304 constituting the link structure of the cache entry 201 also has a bidirectional link structure, and the same operation as the LRU pointer is possible. The tag pointer 304a is a tag on the back side of the link, and the tag pointer 304b is an entry. Stores the top address of the tag on the near side.
Similarly, there are a link for managing the dirty page of the non-volatile memory in FIG. 8 and a link for managing the clean page of the non-volatile memory in FIG. 9, each of which exists on the non-volatile memory as cache management information.

  In addition to the currently used page, there is also a link for managing a page that is not managed by a cache entry, that is, not yet allocated, and is managed by the free page management link of FIG. When pages in the initial state such as when power is turned on are not allocated at all, all pages are connected to this empty page management link. This link is managed separately for the nonvolatile memory and the volatile memory, and is connected to either the nonvolatile memory empty entry 601 or the volatile memory empty entry 604, and is managed by the link structure of the tag pointer 304 of the cache tag, similarly to the cache entry. The last tag writes information indicating NULL at the end of the link to the tag pointer, and the page pointer 302 points to an individual page pointer allocated on the non-volatile memory or volatile memory at the time of initial power-on.

10, 11 and 12 are flowcharts showing the overall operation of the storage system according to this embodiment. FIG. 10 shows the operation during a read request, and FIG. 11 shows the operation during a write request. FIG. 12 shows the operation when the power supply is restarted. Hereinafter, the overall operation of the present embodiment will be described in detail with reference to the flowcharts shown in FIGS. 10, 11, and 12.
First, in step S1, when a write request is received from the host computer, the cache management unit 101 selects a tag whose address of the received write request matches the core address 307 in the cache tag existing in the link of the cache entry 201. Search for.
In step S2, this search is verified. If there is no corresponding tag, the process proceeds to step S3, and if there is a corresponding tag, the process proceeds to step S6.

In step S3, an arbitrary cache tag is extracted from the link of the non-volatile memory free entry 601.
In step S4, the cache pointer extracted by operating the tag pointer 304 is inserted into the link of the cache entry searched in step S1, and the link of the volatile Clean LRU entry 701 is operated by operating the LRU pointer 303 of the cache tag. Insert into. Then, the dirty information 306 of the cache information of the tag is set to 1 dirty, and the memory type 305 is set to 1 nonvolatile. However, if there is no cache tag in the link of the non-volatile memory free entry 601 in step S3, the cache tag of the link of the non-volatile Clean LRU entry is used, and if there is no cache tag in the link of the non-volatile Clean LRU entry. The cache tag is extracted from the link of the non-volatile dirty LRU entry, the page data indicated by the page pointer of the cache tag is written to the medium, and then the cache tag is used.

In step S5, data from the host computer is stored at the address of the page pointer 302 of the tag, information indicating that the data has been written is transmitted to the host computer, and the write request from the host computer is terminated.
In step S6, as a process when there is a cache tag of the storage address 307 that matches the corresponding address in step S2, it is determined whether or not the dirty information 306 of the cache information 301 of the corresponding cache tag is 1 dirty. If it is determined that it is Dirty, the process proceeds to step S5.
In step S7, as a process when the dirty information 306 of the cache information 301 is not dirty (that is, clean), the memory type 305 of the cache information 301 is determined. If the memory type 305 is not nonvolatile, the process proceeds to step S9.

In step S8, after the dirty information 306 is rewritten from clean to dirty, write data from the host computer is written to the page of the address indicated by the page pointer 302 of the cache tag, and the process proceeds to step S5.
In step S9, as a process in the case where the memory type 305 of the cache information 301 is not non-volatile (that is, clean of 0) in step S7, the tag page invalidation process is performed.

  In this invalidation processing, the page tag is removed from the link of the cache entry 201 and the link of the LRU (in this case, the link of the volatile Clean LRU entry), and inserted into the link of the volatile memory free entry 604, so that it is stored on the volatile memory. Discard the cache. After that, a new tag is newly extracted from the link of the non-volatile memory free entry 601, the dirty information 306 of the cache information 301 of the tag is changed to 1 Dirty, and the memory type is similarly changed to 1 non-volatile. The link of the cache entry searched with the address of the write request is connected, and then the link of the nonvolatile dirty LRU entry 801 is connected. Thereafter, the process proceeds to step S5.

FIG. 11 is a flowchart showing the operation when there is a read request from the host computer.
First, in step S21, when the cache management unit 101 receives a read request from the host computer, the cache entry is determined by using the hash of the read address indicated by the request and connected to the link of the cache entry. The address corresponding to the storage address 307 of the cache tag 201 is searched.
Next, in step S21, the search result is verified. If there is no address indicated by the storage address 307, the process proceeds to step S23. Otherwise, if there is an address indicated by the storage address 307, the process proceeds to step S24.

  In step S23, if the address specified in the read request in step S22 is not found from the storage address 307 of the cache tag 201, the cache tag is newly taken out from the link of the volatile memory free entry 604, or there is nothing. A tag is extracted from the link of the volatile Clean LRU entry to obtain a page for storing data, and then the address of the tag is inserted into the link of the cache entry and the link of the volatile Clean LRU entry that are searched first. At this time, the dirty information of the cache information 301 is set to Clean, and the memory type is set to volatile. Thereafter, the address of the read request is written to the storage address 307, the data of the storage medium 104 designated by the address is read, and the data is written to the page indicated by the address of the page pointer 302, and the process proceeds to step S24.

In step S24, the page data indicated by the address of the page address 302 of the tag is sent to the host computer, the fact that the read request has been completed is also returned, and the read request is terminated.
FIG. 12 is a flowchart showing a recovery process at the time of restart after power-off.
Immediately after recovery from the power interruption, the page data on the volatile memory 103 is erased due to the power interruption, resulting in a state inconsistent with the cache management information protected by the power interruption. For this reason, since the page information erased in the volatile memory 103 must be removed from the cache management information, the processing shown in the flowchart of FIG. 12 is performed.

First, in step S31, if a write or read request is received from the host computer in a state where the cache management information is inconsistent during the recovery process, it may cause a malfunction. Pause the request. First, the pointer of the volatile Clean LRU entry 604 is referred to.
In step S32, it is checked whether or not the pointer of the volatile Clean LRU entry 604 is last (= NULL). If the pointer of the volatile Clean LRU entry 604 is not NULL, there is a cache tag to be processed, and the process proceeds to the next step S33. . Otherwise, if the pointer of the volatile Clean LRU entry 604 is NULL, there is no cache tag to process, and the process moves to step S35.

In step S33, it is removed from the link of the cache entry indicated by the tag pointer 304 of the cache tag indicated by the pointer and also from the link of the volatile Clean LRU entry 701. Thereafter, in step S34, the cache tag is connected to the end of the volatile memory free entry 601, and the process returns to step S31 to continue the processing of the remaining cache tags.
In step S35, since the process of invalidating the page on the volatile storage medium has been completed, it is set in a state where a read or write request from the host computer can be accepted, and then returns to the normal state.

FIG. 13 is an explanatory diagram showing an example of the initial value of the cache control information in the storage system according to the present embodiment.
Next, referring to the initial values of the cache control information shown in FIG. 13, using the flowcharts of FIGS. 10, 11, and 12, the operation of the storage system according to this embodiment will be described in a specific example. .
In this embodiment, the storage medium 104 shown in FIG. 1 may be constituted by a readable / writable recording medium such as a magnetic disk device (HDD), a silicon disk, or an optical disk.
The storage medium 104 has one or more of the above storage media, and can determine a unique data storage location for a specified address by a read or write request from a host address.

  In addition, when data is actually written to a storage medium, the same data is written to a plurality of media, RAID control used in a disk array system, etc. in preparation for the case where reading or writing cannot be performed due to a medium defect or medium failure. Thus, data redundancy using parity may be performed. When the cache management unit 101 performs a read operation or a write operation on these storage media, the redundancy processing is concealed and is performed according to the address specified by the read request or write request from the host computer. , Virtually determine one storage location. In the following description, it is assumed that these redundancy processes are concealed in the read operation or write operation on the storage medium 104. The addresses designated by these host computers and the storage addresses indicate the same address space, but the pointers shown in the cache management information are managed in a different address space.

FIG. 14 is an explanatory diagram showing a state diagram as one example of cache control information in the storage system according to the present embodiment.
Hereinafter, with reference to FIG. 1, FIG. 3, FIG. 10, FIG. 13, and FIG. 14, one embodiment when there is a write request from the host computer to this storage system will be described. When the write request is received from the host computer, the cache management unit 101 searches the cache tag existing in the link of the cache entry 201 for the address of the received write request. At this time, the address indicated by the write request received from the host computer is, for example, “4700”, and the cache tag link for managing the cached data in FIG. 13 is connected only to the cache entry 1301. To do.

  Also, the calculation of the hash value of the address “4700” indicates the entry of the cache entry 1301. Then, the cache management unit 101 searches the link of the cache entry 1301 from the designated address to determine whether a tag with the corresponding address exists. The pointer stored in the cache entry 1301 is “7806” at this time, and the cache management unit 101 next specifies the contents of the storage address of the cache tag 1302 specified by the address “7806” and the host computer. When the comparison is made with the address “4700”, the storage address of the cache tag 1302 is “12A000”, which does not match.

  Therefore, the cache management unit 101 refers to the tag pointer of the cache tag 1302 and determines whether or not the next cache tag exists. Therefore, the cache management unit 101 refers to the cache tag indicated by the value of the tag pointer F304a that refers to the back of the cache tag. At this time, since the value of the tag pointer F304a of the cache tag 1302 is “6450”, the cache tag 1303 designated by this “6450” is referred to. When the storage address of the cache tag 1303 is referred to in the same manner as the previous time, it is “36C00”, which is different from the address “4700” designated by the host computer. Similarly, the value of the tag pointer F304a of the cache tag 1303 is “3200”.

  The cache tag indicated by “3200” is the cache tag 1304, and the storage address of the cache tag 1304 is “47600”. Again, since the address is different from the address “4700” designated by the host computer, whether or not the next cache tag exists is continuously searched. The tag pointer F (304a) of the cache tag 1304 (the cache tag shown in FIG. (See reference numeral) indicates “NULL”, so that the cache tag 1304 can be determined to be the last tag of the cache entry 1301. Therefore, there is no data indicated by the address designated by the host computer, and it is determined that there is no corresponding cache tag as a result of the search (step S1).

  Next, when it is determined that there is no tag at the address (step S2: NO), the tag is extracted from the head of the link of the nonvolatile memory empty entry 1341. For this, the nonvolatile empty entry 1341 shown in FIG. 14 is referred to, and the cache tag 1342 indicated by the nonvolatile empty entry 1341 is taken out. Since the tag pointer of the nonvolatile free entry 1341 indicates “7200”, the cache tag “7200” is referred to. To remove the cache tag 1342 from the link of the nonvolatile free entry, the contents of the tag pointer F (304a) of the cache tag entry 1342 are copied to the tag pointer F (304a) of the cache tag indicated by the pointer of the tag pointer B (304b). To do.

  Here, the pointer of the nonvolatile empty entry 1341 is considered to be equivalent to the tag pointer F (304a) of another cache tag. This is realized by writing the contents of the tag pointer B (304b) of the cache tag 1342 to the tag pointer B (304b) of the cache tag 1343 indicated by the pointer of the tag pointer F (304a). Then, the content of the nonvolatile empty entry 1341 becomes the address “8250” of the cache tag 1343, and the content of the tag pointer B (304b) of the cache tag 1343 is replaced with “7200” indicating the nonvolatile empty entry 1341. The removal of 1342 is completed.

  The cache tags are extracted in the same manner for other entries. At this time, if there is no empty page in the nonvolatile empty entry 1341, the cache tag is extracted from the nonvolatile Clean LRU entry and used, or the cache tag of the nonvolatile dirty LRU is extracted and used. When the nonvolatile dirty LRU is taken out, it is used after the page data indicated by the page pointer is written in the storage medium area that can be uniquely determined by the storage address (step S3).

  After the cache tag is taken out, the cache tag 1342 is connected to the end of the cache entry 1301 and also connected to the end of the nonvolatile dirty entry 1321. For this purpose, the cache tag of the pointer of the cache entry 1301 is sequentially traced backward until the tag pointer F (304a) becomes NULL while referring to the tag pointer F (304a). Since the cache tag 1304 is the last cache tag, the content of the tag pointer F (304a) of the cache tag 1304 is replaced with the value of the start address of the cache tag 1342, and the value of the tag pointer F (304a) of the cache tag 1342 is changed. In NULL, the contents of the tag pointer B (304b) of the cache tag 1342 and the head address of the cache tag 1304 are stored.

  Here, the value of the tag pointer 304a of the cache tag 1304 is “8310”, the value of the tag pointer F (304a) of the cache tag 1342 is “NULL”, and the value of the tag pointer B (304b) of the cache tag 1342 is “ 3200 ", and the link starting from the cache entry 1301 is completed. At the same time, a nonvolatile dirty LRU entry is added to the end of the link in the same manner. Then, the content of the LRU pointer F (303a) of the cache tag 1312 is replaced with “8310” which is the start address of the cache tag 1342, the LRU pointer F303a of the cache tag 1342 is “NULL”, and the content of the LRU pointer 303b is also the cache tag. The link starting from the nonvolatile dirty LRU entry 1321 is completed by replacing “6300” which is the start address of 1322.

  Thereafter, the Dirty information 306 of the cache information of the cache tag 1342 is set to 1 Dirty, the memory type 305 is set to 1 non-volatile, and the storage address is specified by the read request or write request from the host computer “4700”. "Is stored (step S4). Thereafter, the page indicated by the page pointer 302 of the cache tag 1342 (in this case, data from the host computer at the address of “nonvolatile memory page 8”) is stored, and information indicating that the data has been written is transmitted to the host computer. Then, the write request from the host computer is terminated (step S5).

Hereinafter, one embodiment in the case where there is a tag of the corresponding address in step S2 will be described.
This case corresponds to the case where the address indicated by the write request from the host computer is “36C00” in the state shown in FIG. As in the case described above, if the calculation of the hash value of the address “36C00” indicates the cache entry 1301, the link search for the cache entry 1301 is performed as in the case described above (step S1). Then, since it matches the storage address of the cache tag 1303, it is determined that the cache has been hit (step S2). Next, it is determined whether or not the dirty information 306 of the cache information 301 of the cache tag 1303 is 1 dirty (step S6).

Since the Dirty information of the cache tag 1303 is Dirty, the data from the host computer is written to the cache tag 1303 page pointer, here the memory address indicated by “nonvolatile memory page 1”, and the write request from the host computer is completed. Step S5).
A case where the dirty information 306 of the cache information 301 is not dirty (that is, clean) will be described. In this case, in step S2, as in the case where the write request from the host computer is “47600”, the link search of the cache entry 1301 is performed, and as a result, the storage information of the cache tag 1304 is the same.

  In step S6, it is determined that the dirty information of the cache tag 1303 is Clean (step S6: NO). Next, the memory type 305 of the cache information 301 of the same tag is determined (step S7), and since it is one non-volatile memory, after rewriting the dirty information 306 of the cache tag 1304 from Clean to Dirty, Write data from the host computer is written to the page at the address indicated by the page pointer 302, and the write request is completed (step S5).

In the following, one embodiment will be described in the case where the memory type 305 of the cache information 301 is not 1 in step S7 (that is, 0 is a volatile memory).
Here, it is assumed that the address of the write request designated by the host computer is “12A000”. The calculation result of the hash value of the address “12A000” indicates the cache entry 1301. At this time, if the link of the cache entry 1301 is traced, it can be determined that the data matches the storage address of the cache tag 1302 and the data specified by the address exists in the cache (steps S1, S2: YES). Therefore, it can be determined in step S6 that the cache information of the cache tag 1302 is Clean, and in step S7, it can be determined that the cache information is volatile memory. This indicates that the data of the write request exists in the volatile memory.

  The data of the write request from the host computer is arranged in the nonvolatile memory in preparation for power failure. For this reason, the data in the volatile memory is invalidated (that is, the cache data is discarded), and there is data with the same address but different To prevent it. This is realized by removing the cache tag 1302 from the cache entry 1301 and simultaneously removing it from the link of the volatile Clean LRU entry 1311 and connecting it to the volatile empty entry 1351.

  To remove the cache tag 1302 from the link of the cache entry, the contents of the tag pointer F (304a) of the cache tag entry 1302 are copied to the tag pointer F (304a) of the cache tag indicated by the pointer of the tag pointer B (304b). . Here, the contents of the cache entry 1301 are rewritten. This is realized by writing the contents of the tag pointer B (304b) of the cache tag 1302 into the tag pointer B (304b) of the cache tag 1303 indicated by the pointer of the tag pointer F (304a). Thus, the address “6450” of the cache tag 1303 is entered in the contents of the cache entry 1301, and the contents of the tag pointer B (304b) of the cache tag 1303 are replaced with “3708” indicating the cache tag entry 1301. Complete the removal.

  Similarly, the operation of removing from the link of the volatile Clean LRU entry 1311 is also performed, and the process for removing the cache tag 1302 is completed. At this time, the content of the volatile Clean LRU entry 1311 is replaced with “6200” which is the address of the cache tag 1312, and the content of the LRU pointer B (304b) of the cache tag 1312 is replaced with “1010” of the entry address. Complete removal from the entry. Thereafter, connection is made to the end of the link of the volatile free entry 1351. To this end, the LRU pointer F (303a) of the cache tag at the address indicated by the contents of the volatile free entry 1351 is sequentially traced until it becomes “NULL”.

In the state shown in FIG. 13, the cache tag 1353 is the last link. Here, the head address “7806” of 1302 is stored in the LRU pointer F (303a) of the cache tag 1353, “NULL” is stored in the LRU pointer F (303a) of the cache tag 1302, and the cache is stored in the LRU pointer B (303b). This is realized by writing “8120” which is the head address of the tag 1353.
By removing these cache entries and LRU entries, the cache is invalidated, and the cache having other attributes is invalidated in the same procedure. After that, a page is newly secured from the non-volatile memory free entry 1341 as in the case described above.
This procedure is exactly the same as in steps S3 and S4 (step S9).
Thereafter, the write data from the host computer is written to the page of the address indicated by the newly acquired cache tag page, information indicating that the write writing is completed is returned to the host computer, and the write request is completed (step S5). ).

Hereinafter, an embodiment when a read request is received from the host computer shown in FIG. 11 will be described using a flowchart.
When the cache management unit 101 receives a read request from the host computer, the cache entry is determined using a hash at the address at which the read indicated by the request is performed. At this time, assuming that the address of the read request sent from the host computer is “12A000” and the cache management information is in the state shown in FIG. 13, it is indicated by the contents of the cache entry 1301 as in the case of the write request described above. The cache tag is sequentially traced, and the address specified as the storage address is searched. At this time, the storage address of the cache tag 1302 matches with “12A000” (steps S21 and S22).

  Thereafter, the page indicated by the page pointer of the cache tag 1302, that is, the information of “volatile memory page 0” is transmitted to the host computer, and the read request from the host computer is completed. The same applies to the case where the address indicated by the read request from the host computer is “36C00” and “47600”. When the corresponding address is “36C00”, “nonvolatile memory page 1” and the address is “47600”. In this case, the data of “nonvolatile memory page 2” is sent to the host computer, the fact that the read request is finished is also returned, and the read request is finished (step 24).

  In step S22, if data at the address specified by the read request is not found, that is, if the address specified by the read request and the storage address 307 of the cache tag 201 do not match, a new volatile memory space is available. A tag is taken out from the head of the entry 604, or if not, the head tag of the volatile Clean LRU entry is taken out, and a page storing data is obtained. If the address specified in the read request from the host computer is “5F000” and the hash value of the address “5F000” indicates the cache entry 1301, the link search for the cache entry 1301 is performed in the same manner as in step S21. Do. In this case, since there is no match with the storage address of each cache tag, it is determined that there is no corresponding cache tag (step S22).

  Thereafter, a new page is secured from the volatile memory. For this purpose, the first cache tag indicated by the contents of the volatile free entry 1351 is taken out. If there is no available cache tag in the volatile free entry 1351, it is extracted from the volatile Clean LRU entry and used. At this time, if the fetched cache tag is the cache tag 1352, the dirty information of the cache information 301 is set to Clean, the memory type is set to volatile, and the volatile LRU entry is stored in the cache tag 1352 in the same manner as described above. Linking (connection) to the end of 1311 and the end of the cache entry 1301 is performed.

Next, “5F000” is written to the storage address 307 as the address of the read request, and the data of the storage medium 104 specified by the address is stored in the page indicated by the address in the page pointer 302, that is, “volatile memory page 13”. Write (step S23).
Thereafter, the written data is sent to the host computer, and the read request is returned, and the read request is completed (step S24).
Hereinafter, an embodiment of the process at the time of restarting performed after the power is turned off will be described using the flowchart shown in FIG.
Immediately after the recovery from the power interruption, the page data on the volatile memory 103 is erased due to the power interruption, resulting in a state inconsistent with the cache management information on the nonvolatile memory 102. For this reason, the information of the page erased in the volatile memory 103 must be removed from the cache management information (described below).

FIG. 13 shows the state of the cache management information after the power is turned on again. First, during a recovery process, accepting a write request or read request from the host computer with inconsistent cache management information can cause a malfunction, so the read request or write request operation is temporarily suspended until the recovery process is complete. Stop. First, the pointer indicated by the volatile Clean LRU entry 1311 is referred to (step S31), and it is determined whether or not the pointer is a NULL pointer indicating the end (if NULL, the volatile memory to be processed is processed). The removal of the cache tag of the existing cache has been completed).

First, refer to the contents of the volatile Clean LRU entry. Here, since the cache tag 1302 is connected to the link, “7806” is referred to (step S31).
Next, it is determined whether or not the corresponding pointer is “NULL” (step S32).
Since the corresponding pointer is not “NULL”, it is removed from the volatile LRU entry 1311 and the cache entry 1301, and the cache tag 1302 taken out thereafter is connected to the volatile free entry 1351 to complete the operation.
Incidentally, the above-described series of processing is the same procedure as the cache invalidation processing in step S9 of FIG. 10 (steps S33 and S34). At this time, the link of the volatile Clean LRU entry is such that the content of the volatile Clean LRU entry is the start address of the cache tag 1312, the tag pointer B of the cache tag 1312 is the start address of the entry, and the tag pointer F is “NULL”. In this state, the process returns to steps S31 and S32 again to determine whether or not the content of the volatile Clean entry is “NULL”.

Here, since “6200” which is the head address of the cache tag 1312 is stored, the processing shifts to the next processing. As in the previous time, the cache tag 1312 is taken out. At this point, the content of the volatile Clean LRU entry is in a “NULL” state. Then, the process returns to step S31 to refer to the volatile Clean LRU entry again.
At this time, since the content of the volatile Clean LRU entry is “NULL”, all the caches to be invalidated are completed, and the process proceeds to step S35 (step S32). In step S35, reception of the read request or write request from the host computer that has been suppressed is started, and thereafter, processing for a normal read / write request is performed and the processing is terminated.

In each of the embodiments shown above, the connection to the link of the cache entry of a new or reused cache tag is attached at the end (end) of the link, but this is connected immediately after any cache entry. In this case, the same processing as that for the last connection is possible. The same applies to the nonvolatile empty entry and the volatile empty entry.
The volatile Clean LRU entry, non-volatile Dirty LRU entry, and non-volatile Clean entry were also connected at the end of the link (the end), but this is based on the basic LRU (first-in last-out algorithm) concept. Depending on the LRU algorithm and cache reuse optimization algorithm, it may be possible to connect to the middle or beginning of the link instead of the end of the link. Also in this case, it is possible to apply the process of connecting to the end of the link in the middle of the link.

  By performing these processes, the read data read from the medium can be stored in the volatile memory, the write data sent from the host can be stored in the non-volatile memory, and the volatile memory can be restored even after the power is restored. Invalidation of the cache lost above is performed, so that operation without contradiction is enabled thereafter. As a result, it is possible to reduce the amount of use of the nonvolatile memory, and as a result, it is possible to minimize the battery backup required for the nonvolatile memory.

  In this embodiment, it is assumed that the nonvolatile memory uses a volatile memory such as a DRAM and is backed up by a battery. However, the same applies to other nonvolatile semiconductor memories that do not require a battery backup, such as FeRAM and MRAM. It is applicable to. Although these non-volatile semiconductor memories are expensive, the storage system according to the present invention can reduce the amount of use of these expensive memories, thereby achieving another effect that the price can be reduced.

  Further, a similar effect can be obtained with a magnetic disk that is faster than a storage medium but is more expensive than a non-volatile memory (thus, not only a cache memory but also a so-called virtual storage device) The present invention can also be applied to the construction of a storage device having a structure (that is, a storage device that is mainly hierarchized by a magnetic disk device). In the above embodiment, the storage medium is a large-capacity and relatively low-speed storage medium such as a magnetic disk. However, as the storage medium, one or more storages are used separately from the storage medium. Also good.

  It should be noted that at least a part of the processing of each component of the storage system according to the present invention is executed by computer control, and the above processing is executed by the computer according to the procedures shown in the flowcharts of FIGS. The program to be shown may be distributed by storing it in a computer-readable recording medium such as a semiconductor memory, a CD-ROM, or a magnetic tape. A computer including at least a microcomputer, a personal computer, and a general-purpose computer may read and execute the program from the recording medium.

  The present invention can be suitably applied to cache control of a disk array, a cache of a magnetic disk built in a personal computer, a server, or the like, particularly a cache that requires backup with a large capacity battery. The present invention can also be applied to a hierarchical storage device mainly composed of a magnetic disk device, an optical disk device, etc., when a cache mechanism requiring a power failure guarantee is used.

1 is a configuration diagram showing an overall configuration of a storage system according to an embodiment of the present invention. It is a block diagram which shows the whole structure of the cache management information of the storage system which concerns on this Embodiment. 2 is a configuration diagram showing a configuration of a cache tag 202. FIG. 4 is a configuration diagram showing a page configuration on a nonvolatile memory 401. FIG. 3 is a configuration diagram showing a page configuration on a volatile memory 501. FIG. It is a block diagram which shows the link structure for empty page management. It is a block diagram which shows the LRU structure of the clean cache page allocated to a volatile memory. It is a block diagram which shows the LRU structure of the dirty cache page allocated to a non-volatile memory. It is a block diagram which shows the LRU structure of the clean cache page allocated to a non-volatile memory. It is a flowchart figure which shows the operation | movement at the time of the write request of the storage system which concerns on embodiment of this invention. It is a flowchart figure which shows the operation | movement at the time of the read request of the storage system which concerns on embodiment of this invention. It is a flowchart figure which shows the recovery operation after the power-off of the storage system which concerns on embodiment of this invention. It is explanatory drawing which shows an example of the initial value of the cache control information in the storage system which concerns on this Embodiment. It is explanatory drawing which shows the state figure as one Example of the cache control information in the storage system which concerns on this Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 Cache management means 102 Non-volatile memory 103 Volatile memory 104 Storage medium 201 Cache entry 202 Cache tag 301 Cache information 302 Page pointer 303 LRU pointer 303a LRU pointer F
303b LRU pointer B
304 Tag pointer 304a Tag pointer F
304b Tag pointer B
305 Memory type 306 Dirty information 307 Storage address 401 Non-volatile memory 501 Volatile memory 601 Non-volatile memory empty entry 602, 603 Cache tag 604 Volatile memory empty entry 605, 606 Cache tag 701 Volatile Clean LRU entry 702-704 Cache tag 801 Non-volatile dirty LRU entry 802 to 804 Cache tag 901 Nonvolatile Clean LRU entry 902 to 904 Cache tag

Claims (6)

A power failure is provided as a cache memory having a large storage device whose data input / output speed is slower than the requested data input / output speed of the host device, and for reducing the difference in data input / output speed between the host device and the large storage device. In a storage system comprising a non-volatile semiconductor memory having a battery for holding time and a volatile semiconductor memory,
When a data write request is sent from the host device, the write request data is temporarily stored in the nonvolatile semiconductor memory, and the write request data is stored in the nonvolatile semiconductor memory. Means for responding to the notification that the writing of the write request data has been completed;
When a data read request is sent from the host device, data matching the read request is read from the large storage device and stored in the volatile semiconductor memory. Thereafter, a data read request from the host device is received. Means for reading out the data stored in the volatile semiconductor memory and sending it to the host device when sent out;
When the page of the data stored in the volatile semiconductor memory exists at the time of recovery from the power interruption, the means for invalidating the page;
A storage system characterized by comprising: Means for verifying whether data having the same address as the write request data exists on the volatile semiconductor memory, as means executed when writing the write request data from the host device to the nonvolatile semiconductor memory; And a means for invalidating the data on the volatile semiconductor memory when it is found that the data of the same address exists on the volatile semiconductor memory. The storage system according to 1.   The storage system according to claim 1, wherein the host device includes a computer system.   The storage system according to claim 1, wherein the large storage device includes a magnetic disk device or an optical disk device. In a storage cache control method comprising a nonvolatile semiconductor memory having a battery for storing memory during a power failure, and a volatile semiconductor memory, and mitigating a difference in data input / output speed between a host device and a large storage device,
When a data write request is sent from the host device, the write request data is temporarily stored in the nonvolatile semiconductor memory, and the write request data is stored in the nonvolatile semiconductor memory. Responding with a notification that the writing of the write request data has been completed;
When a data read request is sent from the host device, data matching the read request is read from the large storage device and stored in the volatile semiconductor memory. Thereafter, a data read request from the host device is received. When sent, the step of reading the data stored in the volatile semiconductor memory and sending it to the host device;
When there is a page of the data stored in the volatile semiconductor memory at the time of recovery from a power failure, invalidating the page;
A storage cache control method comprising: A storage device comprising a nonvolatile semiconductor memory having a battery for storing memory during a power failure and a volatile semiconductor memory, which allows a computer to execute cache control to reduce a difference in data input / output speed between a host device and a large storage device. In the cache control program,
When a data write request is sent from the host device, the write request data is temporarily stored in the nonvolatile semiconductor memory, and the write request data is stored in the nonvolatile semiconductor memory. Responding with a notification that the writing of the write request data has been completed;
When a data read request is sent from the host device, data matching the read request is read from the large storage device and stored in the volatile semiconductor memory. Thereafter, a data read request from the host device is received. When sent, the step of reading the data stored in the volatile semiconductor memory and sending it to the host device;
When there is a page of the data stored in the volatile semiconductor memory at the time of recovery from a power failure, invalidating the page;
A storage cache control program comprising:

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