JPH10161926A - Memory control circuit for executing burst operation - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory control circuit which can reduce the current consumption and noises caused by switching without delaying access to a memory. SOLUTION: The respective high-order address bits of respective address terminals 1 are respectively latched through buffer circuits 4 and a decode circuit 5 for decoding them to the middle by a latch circuit 6 according to a control signal S1. When a control signal SO instructing burst operation is inputted, a counter circuit 7 applies the control signal S1 to the latch circuit 6, starts counting from the addresses inputted to address terminals 2 just prescribed times and successively outputs them to a decode circuit 8. The decode circuit 8 decodes the outputs of latch circuit 6 and counter circuit 7 and based on the result, only the specified part of memory cell 9 is made accessable. Therefore, switching due to the decode circuit 8 is reduced just for the component latched by the latch circuit 6.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to inputting an upper address bit and a lower address bit of an address signal at the start of a burst operation, and generating a predetermined number of consecutive lower address bits from the input lower address bits. The present invention relates to a memory control circuit that decodes data consisting of upper address bits and generated lower address bits, and sequentially accesses a predetermined portion of a corresponding memory cell based on a result of the decoding.

[0002]

2. Description of the Related Art In recent years, with the increase in the speed of microprocessors, the demand for high-speed access to memories has increased, and it has been proposed to access memories by burst operation as one means for responding to the demand. A word line and a column switch selection circuit in this memory use a logic circuit having a relatively large current driving capability in order to perform a high-speed operation. In addition, during the burst operation, the column switches of the memory cells are continuously selected, so that the number of switching operations per unit time increases. The increased number of switching times increases the current consumption, and the increased current consumption causes switching noise to occur, eventually causing the memory itself to malfunction. In addition, since a memory cell is selected by all address signals, an access delay due to skew between signals occurs, and this is a serious problem particularly in a large-capacity high-speed semiconductor memory having a burst function.

FIG. 3 shows a typical example of this type of related art, and shows a main portion of a synchronous SRAM having a burst function. Address signals for accessing a specific portion of the memory cell 19 are input to the address terminals 11 and 12. Address terminal 11 receives the corresponding upper address bits of the address signal, and address terminal 12 receives the corresponding lower address bits. A control signal S0 for instructing a burst operation is input to the input terminal 13. Each upper address bit is input to the decode circuit 18 via the buffer circuit 14, and each lower address bit is transmitted to the counter circuit 17 via the buffer circuit 15. Counter circuit 1
7 receives the control signal S0 from the input terminal 13 via the buffer circuit 16, counts a predetermined number of times starting from the address input to the address terminal 12, generates lower address bits, and outputs it to the decode circuit 18. Each time the counter circuit 17 generates the lower address bits, the decode circuit 18 fetches and decodes the upper address bits from the buffer circuit 14 and the lower address bits from the counter circuit 17, and decodes the corresponding memory based on the result. Make certain parts of the cell accessible. Therefore, the decoding circuit 18 must perform a switching operation for all address bits for each address signal.

[0004]

In the above-mentioned conventional memory, in order to avoid an increase in the number of switching operations and hence an increase in current consumption due to the switching operation, the size of transistors for driving word lines and column switches is reduced as much as possible. Or slowing the rising speed of the word line and column switch selection signals to solve the problem, but all have the problem of delaying the access time. In view of these problems, the present invention does not cause a delay in access to a memory, and
An object of the present invention is to provide a memory control circuit capable of reducing current consumption due to switching and reducing switching noise.

[0005]

In order to achieve the above object, the present invention provides an input means for inputting an upper address bit and a lower address bit of an address signal, respectively, and an input means for inputting at the start of a burst operation. Lower address bit generating means for sequentially generating a predetermined number of consecutive lower address bits from the lower address bits, and fetching upper address bits of an address signal at the start of a burst operation, and data corresponding to the fetched upper address bits. Until the end of the burst operation, the data is held unchanged and output to the decoding circuit, the upper address bit holding means, data corresponding to the upper address bits held by the upper address bit holding means, and lower address bits The data consisting of the lower address bits generated by the generation means is And over de, and having a decode circuit that enables sequential access to predetermined portions of a memory cell corresponding the result of decoding.

In the control circuit of the present invention, during each burst operation, while the lower address bit generation means sequentially generates a predetermined number of consecutive lower address bits, the upper address bit holding means sets the address at the start of the burst operation. The upper address bits of the signal are fetched, and the data corresponding to the fetched upper address bits is held unchanged until the burst operation ends. The decoding circuit decodes data consisting of the data corresponding to the upper address bits held by the upper address bit holding means and the lower address bits generated by the lower address bit generation means, and corresponds to the decoded result. A predetermined portion of the memory cell is made sequentially accessible.

[0007]

Next, an embodiment of the present invention will be described. FIG. 1 is a block diagram showing an example of a memory control circuit according to an embodiment of the present invention, and FIG. 2 is a timing chart for explaining the operation of the control circuit of the present invention in comparison with a conventional circuit. The block diagram of FIG. 1 shows a main part of the synchronous SRAM having a burst function, which is related to the present invention. Address signals for accessing a specific part of the memory cell 9 are input to the upper and lower address terminals 1 and 2. The corresponding upper address bits of the address signal are input to the upper address terminal 1, and the corresponding lower address bits are input to the lower address terminal 2. A control signal S0 instructing a burst operation is input to the input terminal 3 (in this example, a burst operation is performed when the input to the input terminal 3 is at a high level, and a non-burst operation is performed when the input to the input terminal 3 is at a low level).

Each upper address bit input to each upper address terminal 1 receives the output of the decode circuit 5 via a buffer circuit 4 and a decode circuit 5 for preliminarily decoding the upper address bits halfway. The signal is transmitted to the latch circuit 6 for latching. Among the decode circuit 5 and the latch circuit 6 constituting the upper address bit holding means, the latch circuit 6 performs the latch operation only when the control signal S1 for instructing the latch is given. Each lower address bit input to each lower address terminal 2 is
The signals are transmitted to the counter circuit 7 via the corresponding buffer circuits 4. When a control signal S0 for instructing a burst operation is input from the input terminal 3 via the buffer circuit 4, the counter circuit 7 supplies a control signal S1 for instructing a latch to the latch circuit 6 and an address input to the address terminal 2. And counts a predetermined number of times (in this example, counts up four times), and outputs an output to the decode circuit 8 each time.

The decode circuit 8 receives the output signal of the latch circuit 6 having the contents corresponding to the upper address bits and the output signal of the counter circuit 7, and combines them each time the output of the counter circuit 7 is received. Decoding, and based on the result, a specific portion of the memory cell corresponding to each count is made accessible. Read data from a specific part of the memory cell that has become accessible, or
Data writing is performed on the specific portion. Therefore, during the period of the burst operation, the data corresponding to the upper address bits that do not change is kept held by the latch circuit 6, so that the switching operation of the decode circuit 8 during that period is reduced.

For example, as shown in FIG. 2, in a burst period BT of a conventional synchronous SRAM or the like, a time t
Four rising basic clocks are input at 1, t2, t3 and t4. Corresponding to these basic clocks CL, the same upper address bit UA0 is applied to the decoding circuit 8 at times t11, t21, t31, and t41, respectively, and the switching operation is performed in the decoding circuit 8 each time. However, in this example, the first timing when a burst operation command is received,
That is, after the upper address bits are latched by the latch circuit 6 at the time t11, the output of the latch circuit 6 is not changed until the time t51 corresponding to the fall of the basic clock CL rising at the time t4. Less.

As apparent from the comparison shown in FIG. 2, during the burst operation in which the upper address bits do not change, the decoding circuit 8 is driven four times from time t11 to t41 in the conventional method. According to time t
Only once at 11. Therefore, current consumption due to switching is reduced, switching noise generated by current consumption is reduced, and malfunction due to switching noise does not occur. Also, in order to reduce current consumption, the size of transistors that drive word lines and column switches is not reduced, and the rising speed of word line and column switch selection signals is not slowed down. There is no delay in access time.

In the memory control circuit shown in FIG. 1, the decoding of the upper address bits is performed by the decoding circuit 5 and the decoding circuit 8, but the combination of the two makes the circuit complicated. It is not necessary to divide it as long as it is divided and can be processed even after merging. Further, although the decode circuit 5 is arranged in front of the latch circuit 6, it goes without saying that the decode circuit 5 may be arranged behind the latch circuit 6 in accordance with ease of actual arrangement on the substrate. That is, FIG. 1 shows that the memory control device of the present invention can flexibly cope with various changes or corrections such as the arrangement of each unit.

[0013]

As described above, in the control circuit of the present invention, in each burst operation, while the lower address bit generation means sequentially generates a predetermined number of consecutive lower address bits, the upper address bit holding means But,
The upper address bits of the address signal at the start of the burst operation are fetched, and the data corresponding to the fetched upper address bits are held unchanged until the burst operation is completed. Decoding data consisting of the data corresponding to the upper address bits held and the lower address bits generated by the lower address bit generation means, and sequentially accessing a predetermined portion of the corresponding memory cell according to the decoding result. Accordingly, the number of switchings related to the upper address bits in the burst operation period is reduced, the current consumption due to the switching is reduced, the switching noise generated by the current consumption is reduced, and the malfunction due to the switching noise does not occur. Also, in order to reduce current consumption, the size of transistors that drive word lines and column switches is not reduced, and the rising speed of word line and column switch selection signals is not slowed down. There is no delay in access time.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an example of a memory control circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of a control circuit of the present invention in comparison with a conventional circuit.

FIG. 3 is a block diagram showing a conventional example of a memory control circuit.

[Explanation of symbols]

1 ... upper address terminal, 2 ... lower address terminal, 3
…… Input terminal 4, buffer circuit, 5 …… Decode circuit
6 latch circuit, 7 counter circuit, 8 decode circuit, 9 memory cell.

Claims (6)

[Claims] An upper address bit of an address signal;
Input means for respectively inputting lower address bits; lower address bit generating means for sequentially generating a predetermined number of consecutive lower address bits from the lower address bits input to the input means at the start of a burst operation; Upper address bit holding means for capturing the upper address bits of the address signal at the time, holding the data corresponding to the captured upper address bits unchanged until the burst operation ends, and outputting the data to the decoding circuit; The data composed of the data corresponding to the upper address bits held by the upper address bit holding means and the lower address bits generated by the lower address bit generation means are decoded, and a predetermined portion of the corresponding memory cell is decoded according to the decoding result. Decode times to enable sequential access A memory control circuit, characterized in that, with and. 2. The apparatus according to claim 1, wherein said upper address bit holding means includes a spare decode circuit for preliminarily decoding upper address bits, and a latch circuit for latching an output of the spare decode circuit. 2. The memory control circuit according to 1. 3. The high-order address bit holding means includes a latch circuit for receiving and latching high-order address bits from the input means, and a spare decoding circuit for preliminary decoding an output of the latch circuit. 2. The memory control circuit according to claim 1, wherein: 4. The high-order address bit holding means is a latch circuit for receiving and latching high-order address bits from the input means, and the latch circuit stores the address bits themselves as data corresponding to the high-order address bits. The decoding circuit decodes data consisting of the upper address bits held by the latch circuit and the lower address bits generated by the lower address bit generating means, and decodes a predetermined portion of the corresponding memory cell according to the decoding result. 2. The memory control circuit according to claim 1, wherein the memory control circuit can sequentially access 5. The low-order address bit generating means is a counter circuit. When receiving a signal instructing a burst operation, the low-order address bit generation means causes the latch circuit to latch the output of the preliminary decode circuit and starts from the input lower-order address bits. Count up or down, generate a predetermined number of consecutive lower address bits,
3. The method according to claim 2, wherein the signal is passed to the decoding circuit.
A memory control circuit as described. 6. The input means includes: a plurality of upper address bit terminals to which upper address bits of an address signal are inputted; a plurality of upper buffer circuits respectively connected to the respective upper address bit terminals; A plurality of lower address bit terminals to which bits are input, a plurality of lower buffer circuits respectively connected to the lower address bit terminals, a burst input terminal for inputting a control signal for instructing a burst operation, and a burst input terminal. An input terminal buffer circuit connected thereto, wherein the upper address bit holding means receives an upper address bit from the upper buffer circuit, and preliminarily decodes the upper address bit; And a latch circuit for latching an output. The address bit generating means is a counter circuit, which, when receiving a signal instructing a burst operation from an input terminal buffer circuit, causes the latch circuit to latch the output of the preliminary decode circuit and count up starting from the input lower address bit. To generate a predetermined number of consecutive lower address bits, and deliver the generated lower address bits to the decoding circuit. The decoding circuit includes data corresponding to the upper address bits held by the upper address bit holding means, and lower address bits. 2. The memory control circuit according to claim 1, wherein the data composed of the lower address bits generated by the generation means is decoded, and a predetermined portion of the corresponding memory cell is made sequentially accessible according to the decoding result.