JPH10161780A - Portable terminal - Google Patents

Portable terminal

Info

Publication number
JPH10161780A
JPH10161780A JP8330410A JP33041096A JPH10161780A JP H10161780 A JPH10161780 A JP H10161780A JP 8330410 A JP8330410 A JP 8330410A JP 33041096 A JP33041096 A JP 33041096A JP H10161780 A JPH10161780 A JP H10161780A
Authority
JP
Japan
Prior art keywords
cpu
clock
keyboard
signal
portable terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8330410A
Other languages
Japanese (ja)
Inventor
Tetsushi Kumamoto
哲士 熊本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP8330410A priority Critical patent/JPH10161780A/en
Publication of JPH10161780A publication Critical patent/JPH10161780A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To provide a portable terminal reducing power consumption by detecting the operation of a keyboard to start a clock oscillator. SOLUTION: This portable terminal is provided with a CPU 1, the clock oscillator 5 and the operation keyboard 3 and communicates in a time division system. In this case, a key input detecting circuit 2 detecting the operation of the keyboard 3 and an interruption controller 4 are provided. When the portable terminal comes into a intermittently receiving state, the CPU 1 outputs a stoppage signal to stop a clock oscillating part 5 to enter a sleeping mode and when the keyboard 3 is operated, the circuit 2 detects it to send data to the CPU 1 and outputs a signal to an interruption controller 4. Then the controller 4 starts the part 5 and after the output becomes stable, the controller 4 supplies a clock to the CPU 1 and sends the signal to the CPU 1 to switch the sleeping mode to a normal mode.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は携帯電話機等の携帯
端末に関し、特に消費電力の少ない携帯端末に関するも
のである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a portable terminal such as a portable telephone, and more particularly to a portable terminal consuming less power.

【0002】[0002]

【従来の技術】図3はこの種の一般的な携帯端末の構成
例を示す図である。図示するように、携帯端末は基地局
と交信するアンテナ31、高周波信号処理を行うRF部
32、デジタルデ−タの処理を行うデジタル処理部3
3、押しボタンやキ−ボ−ド等で操作する操作部34、
マイクやスピ−カ等を具備する音声処理部35を具備し
ている。
2. Description of the Related Art FIG. 3 is a diagram showing a configuration example of a general portable terminal of this kind. As shown in the figure, a portable terminal includes an antenna 31 for communicating with a base station, an RF unit 32 for performing high-frequency signal processing, and a digital processing unit 3 for processing digital data.
3, an operation unit 34 operated by a push button, a keyboard, or the like;
The audio processing unit 35 includes a microphone, a speaker, and the like.

【0003】デジタル処理部33は高速のCPU(中央
処理装置)を具備し、音声信号の符号化/復号化、プロ
トコル処理、クロック制御及び制御信号等のデジタルデ
−タの処理及び当該携帯端末全体の制御を行う。
The digital processing unit 33 includes a high-speed CPU (Central Processing Unit), and processes digital data such as audio signal encoding / decoding, protocol processing, clock control and control signals, and the entire portable terminal. Control.

【0004】PHS方式携帯電話機やPDC(パーソナ
ル・デジタルセルラ)方式携帯電話機等の携帯端末で
は、通常TDMA(時分割多重接続)方式が採られ、制
御チャネルを使用して基地局と交信し、自分の所在を登
録し基地局からの呼出しに応答している。しかし、常
時、連続的に受信しているのではなく、例えば、PDC
方式携帯電話機では基地局から間欠的に受信を行い、そ
の間欠受信状態では最大36サブフレ−ム(1サブフレ
−ム=20ms)に1回6.6msの受信期間の割合で
受信を行い基地局と連絡している。
[0004] Portable terminals such as PHS portable telephones and PDC (personal digital cellular) portable telephones usually employ a TDMA (Time Division Multiple Access) system, which communicates with a base station using a control channel and transmits a signal to a base station. And responds to calls from the base station. However, it is not always continuously received, for example, PDC
In the intermittent reception state, the mobile phone receives intermittently from the base station, and in the intermittent reception state, performs reception once every 36 subframes (1 subframe = 20 ms) for a reception period of 6.6 ms. I'm in contact.

【0005】従来より携帯端末はバッテリを駆動電源と
するものが多く、そのため消費電力は極力小さいことが
望まれる。携帯端末における低消費電力化の一つとし
て、携帯端末が待機状態で間欠受信状態にあるときはC
PUをスリ−プモ−ドにしてクロックの供給を停止する
方法、又はクロックの周波数を下げる方法が採られてき
た。
[0005] Conventionally, many portable terminals use a battery as a driving power source, and thus it is desired that power consumption be as small as possible. One of the ways to reduce power consumption in a mobile terminal is to set C when the mobile terminal is in a standby state and is in an intermittent reception state.
A method in which the PU is put into a sleep mode to stop the supply of the clock or a method in which the frequency of the clock is reduced has been adopted.

【0006】また、スリ−プモ−ドに入ってもCPUは
自端末からの発呼を検知するために一定周期で通常モ−
ドに復帰し、キ−ボ−ドが押下されたか否かの検出動作
をしている。キーボードが押下されている場合はキ−の
スキャンを行い、押下されたキ−を認識し処理した後、
再びスリ−プモ−ドへ入ることを繰り返している。
[0006] Even in the sleep mode, the CPU operates in the normal mode at a constant period in order to detect a call from the terminal itself.
The operation returns to the step of detecting whether the keyboard has been pressed. When the keyboard is pressed, the key is scanned, and the pressed key is recognized and processed.
Repeatedly entering the sleep mode again.

【0007】[0007]

【発明が解決しようとする課題】しかしながら、上述し
たようにCPUは間欠受信中でもキ−押下を検知するた
め一定周期でスリ−プモ−ドから通常モ−ドに復帰しス
キャンするので、その間は消費電流が増大する。又、間
欠受信中でもクロックの発振器を停止すると、発振再開
時、出力に初期不安定期間があり、また、受信時のタイ
ミングを合わすことが難しいと云う問題があり、間欠受
信中はCPUへのクロック供給は停止しているが発振器
の動作は停止していない。そのためクロック発振器の消
費電流が増大すると云う問題があった。
However, as described above, the CPU returns from the sleep mode to the normal mode at regular intervals to detect a key press even during intermittent reception and scans. The current increases. Also, if the clock oscillator is stopped even during intermittent reception, there is a problem that the output has an initial unstable period when the oscillation is restarted, and it is difficult to adjust the timing at the time of reception. The supply is stopped, but the operation of the oscillator is not stopped. Therefore, there is a problem that the current consumption of the clock oscillator increases.

【0008】本発明は上述の点に鑑みてなされたもの
で、キ−ボ−ドの動作を検知しクロック発振器を起動す
ることにより消費電力を低減した携帯端末を提供するこ
とを目的とする。
SUMMARY OF THE INVENTION The present invention has been made in view of the above-described circumstances, and has as its object to provide a portable terminal which reduces power consumption by detecting operation of a keyboard and activating a clock oscillator.

【0009】[0009]

【課題を解決するための手段】上記課題を解決するため
本発明は、スリ−プモ−ド及び通常モ−ドの動作モ−ド
を有し高周波のクロック信号で作動するCPU、該クロ
ック信号を発振するクロック発振部及び操作用のキ−ボ
−ドを具備し、該クロック信号により時分割方式で通信
する携帯端末において、キ−ボ−ドが操作されたことを
検知するキ−入力検知手段、及び割込みコントロ−ラを
設け、携帯端末が間欠受信状態に入ったとき、CPUは
停止信号を出力しクロック発振部の動作を停止させスリ
−プモ−ドに入り、キ−ボ−ドが操作されるとキ−入力
検知手段はそれを検知しCPUへデ−タを送ると共に割
込みコントロ−ラへ信号を出力し、該割込みコントロ−
ラはクロック発振部を起動し、クロック発振部の出力が
安定した後クロック信号をCPUへ供給すると共に該C
PUへ信号を送りスリ−プモ−ドから通常モ−ドへ切替
ることを特徴とする。
SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a CPU operating in a sleep mode and a normal mode and operating with a high-frequency clock signal. A key input detecting means for detecting that a keyboard has been operated in a portable terminal having a clock oscillating section for oscillating and a keyboard for operation and communicating in a time-division manner by the clock signal. , And an interrupt controller, when the portable terminal enters the intermittent reception state, the CPU outputs a stop signal to stop the operation of the clock oscillating unit, enter the sleep mode, and operate the keyboard. When the key input detecting means detects this, the key input detecting means sends the data to the CPU and outputs a signal to the interrupt controller.
Starts the clock oscillating unit, and after the output of the clock oscillating unit is stabilized, supplies a clock signal to the CPU and
A signal is sent to the PU to switch from the sleep mode to the normal mode.

【0010】[0010]

【発明の実施の形態】以下、本発明の実施の形態例を図
面に基づいて詳細に説明する。図1は本発明の携帯端末
の構成例を示す図である。図示するように、本発明の携
帯端末はCPU1、キ−入力検知回路2、キ−ボ−ド
3、割込みコントロ−ラ4、12.6MHzのクロック
発振部5、送受信部/デジタル処理部6、音声部7、ア
ンテナ8を具備する構成である。
Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a diagram showing a configuration example of a mobile terminal of the present invention. As shown in the figure, the portable terminal of the present invention comprises a CPU 1, a key input detection circuit 2, a keyboard 3, an interrupt controller 4, a 12.6 MHz clock oscillating unit 5, a transmitting / receiving unit / digital processing unit 6, The configuration includes an audio unit 7 and an antenna 8.

【0011】通常受信状態(交信中)では携帯端末はア
ンテナ8で基地局からの電波を送受信し、受信信号は送
受信部/デジタル処理部6で処理され、音声部7のスピ
−カ/マイクを介して通話することができる。操作はキ
−ボ−ド3を通して行われ、CPU1の出力で全体を制
御している。本発明はCPU1を動作させるクロック発
振部5の起動/停止に関するもので、キ−ボ−ド3の入
力の有無を検知するキ−入力検知回路2及び割込みコン
トロ−ラ4を設け、キ−ボ−ド3が操作されると自動的
に12.6MHzのクロック発振部5が起動され、CP
U1へクロック信号が供給される。
In a normal reception state (during communication), the portable terminal transmits and receives radio waves from the base station using the antenna 8, the received signal is processed by the transmission / reception unit / digital processing unit 6, and the speaker / microphone of the audio unit 7 is used. You can make calls over. The operation is performed through the keyboard 3 and the whole is controlled by the output of the CPU 1. The present invention relates to starting / stopping of a clock oscillating unit 5 for operating a CPU 1, and includes a key input detecting circuit 2 for detecting the presence or absence of an input of a keyboard 3 and an interrupt controller 4, and a key board. -When the node 3 is operated, the 12.6 MHz clock oscillator 5 is automatically started, and the CP
A clock signal is supplied to U1.

【0012】図2は間欠受信時の携帯端末の動作フロ−
を示す。同図に従って間欠受信時の動作を説明する。C
PU1は通常受信状態では12.6MHzのクロック信
号で作動し、キ−ボ−ド3からの入力処理や受信処理等
の通常処理をしている(ステップST1)。そして通話
が終了か否かを判断し(ステップST2)、通話が終了
した場合は、CPU1はクロック発振部5へ停止信号を
送り(ステップST3)、クロック発振部5の作動を停
止し、12.6MHzのクロック信号のCPU1への供
給を停止する(ステップST4)。これによりCPU1
はスリ−プモ−ドに入る(ステップST5)。
FIG. 2 shows an operation flow of the portable terminal at the time of intermittent reception.
Is shown. The operation at the time of intermittent reception will be described with reference to FIG. C
PU1 operates in the normal reception state with a clock signal of 12.6 MHz and performs normal processing such as input processing from keyboard 3 and reception processing (step ST1). Then, it is determined whether or not the call has ended (step ST2). If the call has ended, the CPU 1 sends a stop signal to the clock oscillating unit 5 (step ST3) to stop the operation of the clock oscillating unit 5, and 12. The supply of the 6 MHz clock signal to the CPU 1 is stopped (step ST4). Thereby, CPU1
Enters the sleep mode (step ST5).

【0013】CPU1は出力ポ−トをロ−レベルにして
おき、キ−ボ−ド3のキ−が押下されたことを検出する
と(ステップST6)、そのことをキ−入力検知回路2
の出力にて認識する。該キ−入力検知回路2からCPU
1へデ−タを送り、割込みコントロ−ラ4へPIRQ
(プレ割込み)信号を送る(ステップST7)。この
時、12.6MHzの発振は停止しているが32KHz
のクロック(計時用)は作動しており、このクロック信
号でPIRQ信号を発生させる。
The CPU 1 keeps the output port at a low level, and detects that the key of the keyboard 3 has been pressed (step ST6).
Recognize by the output of From the key input detection circuit 2 to the CPU
Send data to 1 and PIRQ to interrupt controller 4
A (pre-interrupt) signal is sent (step ST7). At this time, the oscillation of 12.6 MHz is stopped, but it is 32 KHz.
The clock (for timing) is operating, and the PIRQ signal is generated by this clock signal.

【0014】割込みコントロ−ラ4はPIRQ信号を受
けると、起動信号を出力しクロック発振部5を起動する
(ステップST8)。該クロック発振部5の12.6M
Hzの出力信号が安定する時間を待って(ステップST
9)、CPU1へ12.6MHzのクロック信号を供給
する(ステップST10)。また、割込みコントロ−ラ
4は発振安定時間後IRQ(割込み)信号を出力し、C
PU1をスリ−プモ−ドから通常モ−ドに切替る。以後
はステップ1から繰り返す。
When receiving the PIRQ signal, the interrupt controller 4 outputs a start signal to start the clock oscillating unit 5 (step ST8). 12.6M of the clock oscillator 5
Hz until the output signal in Hz is stabilized (step ST
9) Supply a 12.6 MHz clock signal to CPU 1 (step ST10). The interrupt controller 4 outputs an IRQ (interrupt) signal after the oscillation stabilization time,
PU1 is switched from sleep mode to normal mode. Thereafter, the process is repeated from step 1.

【0015】以上述べたように本実施例ではスリ−プモ
−ドをキ−入力検知回路2、割込みコントロ−ラ4を設
け、キ−ボ−ド3を操作したときはじめてクロック発振
部5が動作し12.6MHzのクロックがCPU1へ供
給されると共に、CPU1が通常モ−ドへ切り替わるの
で、従来のように間欠受信中に周期的にキ−をスキャン
する必要がなく、また、クロック発振部5も駆動停止し
ているので消費電流も少なくなる。
As described above, in this embodiment, the sleep mode is provided with the key input detecting circuit 2 and the interrupt controller 4, and the clock oscillating section 5 operates only when the keyboard 3 is operated. Since the 12.6 MHz clock is supplied to the CPU 1 and the CPU 1 is switched to the normal mode, there is no need to periodically scan the key during intermittent reception as in the prior art. Since the driving is stopped, the current consumption is reduced.

【0016】[0016]

【発明の効果】以上説明したように本発明によれば、下
記のような優れた効果が期待される。キ−ボ−ドが操作
されたことを検知するキ−入力検知手段、及び割込みコ
ントロ−ラを設け、携帯端末が間欠受信状態に入ったと
き、CPUは停止信号を出力しクロック発振部の動作を
停止させスリ−プモ−ドに入り、キ−ボ−ドが操作され
るとキ−入力検知手段はそれを検知しCPUへデ−タを
送ると共に割込みコントロ−ラへ信号を出力し、該割込
みコントロ−ラはクロック発振部を起動し、クロック発
振部の出力が安定した後クロック信号をCPUへ供給す
ると共に該CPUへ信号を送りスリ−プモ−ドから通常
モ−ドへ切替るので、CPUの動作電流及びクロック発
振部の動作電流が低減できる。また、従来のように一定
周期でキ−ボ−ドをスキャンする必要がなくなるので、
スリ−プモ−ドの時間が長くなり消費電流も低減され
る。
As described above, according to the present invention, the following excellent effects are expected. A key input detecting means for detecting that the keyboard has been operated and an interrupt controller are provided, and when the portable terminal enters an intermittent receiving state, the CPU outputs a stop signal to operate the clock oscillating section. When the keyboard is operated and the keyboard is operated, the key input detecting means detects the input, sends data to the CPU, and outputs a signal to the interrupt controller. The interrupt controller activates the clock oscillating unit, and after the output of the clock oscillating unit is stabilized, supplies a clock signal to the CPU and sends a signal to the CPU to switch from the sleep mode to the normal mode. The operating current of the CPU and the operating current of the clock oscillator can be reduced. In addition, since it is not necessary to scan the keyboard at a constant cycle as in the related art,
The sleep mode time is prolonged, and the current consumption is reduced.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の携帯端末の構成例を示す図である。FIG. 1 is a diagram illustrating a configuration example of a mobile terminal according to the present invention.

【図2】間欠受信時の携帯端末の動作フロ−を示す図で
ある。
FIG. 2 is a diagram showing an operation flow of the portable terminal at the time of intermittent reception.

【図3】一般的な携帯端末の構成例を示す図である。FIG. 3 is a diagram illustrating a configuration example of a general portable terminal.

【符号の説明】[Explanation of symbols]

1 CPU 2 キ−入力検知回路 3 キ−ボ−ド 4 割込みコントロ−ラ 5 クロック発振部 6 送受信部/デジタル処理部 7 音声部 8 アンテナ DESCRIPTION OF SYMBOLS 1 CPU 2 Key input detection circuit 3 Keyboard 4 Interrupt controller 5 Clock oscillation part 6 Transmission / reception part / digital processing part 7 Audio part 8 Antenna

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 スリ−プモ−ド及び通常モ−ドの動作モ
−ドを有し高周波のクロック信号で作動するCPU、該
クロック信号を発振するクロック発振部及び操作用のキ
−ボ−ドを具備し、該クロック信号により時分割方式で
通信する携帯端末において、 前記キ−ボ−ドが操作されたことを検知するキ−入力検
知手段、及び割込みコントロ−ラを設け、 前記携帯端末が間欠受信状態に入ったとき、前記CPU
は停止信号を出力し前記クロック発振部の動作を停止さ
せスリ−プモ−ドに入り、 前記キ−ボ−ドが操作されると前記キ−入力検知手段は
それを検知し前記CPUへデ−タを送ると共に前記割込
みコントロ−ラへ信号を出力し、該割込みコントロ−ラ
は前記クロック発振部を起動し、該クロック発振部の出
力が安定した後クロック信号を前記CPUへ供給すると
共に該CPUへ信号を送りスリ−プモ−ドから通常モ−
ドへ切替ることを特徴とする携帯端末。
1. A CPU having an operation mode of a sleep mode and a normal mode and operating with a high-frequency clock signal, a clock oscillating section for oscillating the clock signal, and a keyboard for operation. A key input detecting means for detecting that the keyboard has been operated, and an interrupt controller, wherein the mobile terminal comprises: When entering the intermittent reception state, the CPU
Outputs a stop signal, stops the operation of the clock oscillating section, and enters a sleep mode. When the keyboard is operated, the key input detecting means detects the operation and outputs data to the CPU. And outputs a signal to the interrupt controller. The interrupt controller activates the clock oscillating unit, and supplies a clock signal to the CPU after the output of the clock oscillating unit is stabilized. Signal from sleep mode to normal mode.
Mobile terminal characterized by switching to a mobile terminal.
JP8330410A 1996-11-26 1996-11-26 Portable terminal Pending JPH10161780A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8330410A JPH10161780A (en) 1996-11-26 1996-11-26 Portable terminal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8330410A JPH10161780A (en) 1996-11-26 1996-11-26 Portable terminal

Publications (1)

Publication Number Publication Date
JPH10161780A true JPH10161780A (en) 1998-06-19

Family

ID=18232296

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8330410A Pending JPH10161780A (en) 1996-11-26 1996-11-26 Portable terminal

Country Status (1)

Country Link
JP (1) JPH10161780A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6802015B2 (en) * 2000-12-29 2004-10-05 Hewlett-Packard Development Company, L.P. Method for accelerating the speed of a CPU using a system command having an operation not associated with changing the speed of the CPU
US6826702B1 (en) 1999-09-28 2004-11-30 Nec Corporation Method and apparatus for reducing power consumption of a CPU in a radio set by adaptively adjusting CPU clock frequency according to CPU load
US6986070B2 (en) 2000-12-28 2006-01-10 Denso Corporation Microcomputer that cooperates with an external apparatus to be driven by a drive signal
JP2013200687A (en) * 2012-03-23 2013-10-03 Lapis Semiconductor Co Ltd Clock output control circuit, semiconductor device, electronic device, and clock output control method

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6826702B1 (en) 1999-09-28 2004-11-30 Nec Corporation Method and apparatus for reducing power consumption of a CPU in a radio set by adaptively adjusting CPU clock frequency according to CPU load
US6986070B2 (en) 2000-12-28 2006-01-10 Denso Corporation Microcomputer that cooperates with an external apparatus to be driven by a drive signal
US6802015B2 (en) * 2000-12-29 2004-10-05 Hewlett-Packard Development Company, L.P. Method for accelerating the speed of a CPU using a system command having an operation not associated with changing the speed of the CPU
JP2013200687A (en) * 2012-03-23 2013-10-03 Lapis Semiconductor Co Ltd Clock output control circuit, semiconductor device, electronic device, and clock output control method

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