JPH10154172A - Power consumption detection system of integrated circuit and recording medium recording computer program calculating power consumption of integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To detect an improvement area to save power consumption of an integrated circuit in an earlier stage. SOLUTION: A data holding operation count calculating means 29, a non reference data latch count calculating means 30 and an un-updated data latch count calculating means 31 calculate the number of data holding operations, non reference data storage operations and unupdated data storage operations of each register from connection information of an integrated circuit and a control condition at the time when data is sent to each register based on signal transition counts, and a power consumption calculating means 7 calculates power consumption that results from each operation from each signal transition count, load capacity and operation voltage. Thus, signal transitions in an integrated circuit which is designed in a function design process are discriminated between signal transitions that are necessary for processing and the ones that are not always necessary, and power consumption which results from the signal transitions that are not always necessary and is eliminable is detected.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit design, and more particularly to a power consumption detection system for an integrated circuit and a power consumption detection system for the integrated circuit, which are used for design evaluation for facilitating low power consumption of the integrated circuit. The present invention relates to a recording medium that stores a computer program that requires the following.

[0002]

2. Description of the Related Art At the logic circuit level, the power consumption P of a CMOS logic circuit, that is, the power consumed by charging and discharging a load capacitance, is represented by a load capacitance C, an operating voltage V, an operating frequency f,
P = αfCV ² (1) using the operation rate α. In order to improve accuracy, a leak current or a through current of a transistor may be considered.

An integrated circuit used for a portable information terminal or a communication device has a small power consumption value as one of its specifications. Therefore, the designer must design the circuit so that the power consumption of the circuit satisfies such specifications.

FIG. 16 shows a design flow of a general integrated circuit. First, specifications such as correspondence between input / output signals and power consumption are designed as a specification design. Next, as a functional design, a circuit at a register transfer level is designed by combining a register, an arithmetic unit, and the like. Next, for that purpose, as a logic circuit design, a gate level (logic level) circuit is designed by combining logic elements and the like constituting an arithmetic unit and the like by a logic synthesis technique or the like. Next, for this purpose, a layout-level circuit is designed as a packaging design by combining transistors constituting gates and the like.

In the power consumption estimating apparatus disclosed in Japanese Patent Application Laid-Open No. 5-126873, as shown in FIG. 17, a signal (node) of a signal (node) when a circuit obtained from a logic simulation or given switching information operates. The number of transitions (corresponding to the product of α and f in equation (1)) and the load capacity charged / discharged by each signal changing once (equation (1)
And the operating voltage (equivalent to V in equation (1))
Then, the power consumption is calculated from the above, and the power consumption of the entire circuit and each partial circuit is evaluated.

If it is found that the power consumption of the circuit does not satisfy the specifications, the power consumption must be reduced by improving the processing method.

[0007] If a significant circuit correction is required after the progress of the design process, the development period increases due to redesign. This is because a significant circuit modification cannot be made in the logic circuit design, and it may be necessary to start over from the functional design in order to greatly reduce the power consumption. Therefore, it is necessary to evaluate and estimate the power consumption at an earlier stage of the design process, and to proceed with the design so that redesign is not required as much as possible.

[0008]

As described above, when it is found that the power consumption of the circuit does not satisfy the specifications, the power consumption must be reduced by improving the processing method. For this purpose, it is necessary to find a location that consumes unnecessary or unnecessary power. However, according to the related art, although it is possible to evaluate whether or not the power consumption of the circuit satisfies the specification, it is not possible to present information on an unnecessary power consumption location. For this reason, when the specifications are not satisfied, it is difficult for the designer to know how to modify the circuit to reduce the power consumption, which makes it difficult to reduce the power consumption. is there.

[0009]

In order to solve the above-mentioned problems, a system for detecting power consumption of an integrated circuit according to the first aspect of the present invention provides a system for detecting the number of signal transitions of each element of an integrated circuit, a load capacitance, and an operating voltage of each signal. In the integrated circuit power consumption detection system for determining the power consumption of the integrated circuit from the above, among the signal transitions, signal transitions required for processing to be performed by the integrated circuit and unnecessary signal transitions are identified, and unnecessary signal transitions for processing are identified. An unnecessary power consumption detecting means for detecting the number of signal transitions and using the unnecessary number of signal transitions to determine unnecessary power consumption, which is power consumption due to unnecessary operation, is provided.

According to a ninth aspect of the present invention, there is provided a recording medium storing a computer program for determining the power consumption of an integrated circuit, wherein the number of signal transitions of each element of the integrated circuit, the load capacitance, and the operating voltage of each signal are used. A recording medium on which a computer program for calculating power consumption is recorded, wherein, among the signal transitions, signal transitions required for processing to be performed by an integrated circuit and unnecessary signal transitions are identified, and the number of signal transitions unnecessary for the processing is identified. And a computer program for calculating unnecessary power consumption, which is power consumption due to unnecessary operations, using the unnecessary signal transition count.

With the above configuration, information on how to modify the circuit to reduce the power consumption of the circuit can be obtained as follows. That is, the signal transitions at each element of the integrated circuit. As the number of signal transitions, the load capacitance charged and discharged by each signal changing once, and the operating voltage increase, power consumption increases. Increase. For example, the number of signal transitions of a logic circuit composed of CMOS or the like as described above is represented by the product of the operation rate α and the operation frequency f, and the power consumption of this logic circuit can be obtained from logic simulation or given switching information. The number of signal transitions of a signal (node) when the required circuit operates,
The load capacitance C charged and discharged by one change of each signal and the operating voltage V increase as the signal V increases.

However, the number of signal transitions includes the number of signal transitions for performing operations that are not necessarily required for the processing to be performed by the integrated circuit. Therefore, in the configuration of the present invention,
The unnecessary power consumption detecting means identifies signal transitions necessary for processing and unnecessary signal transitions, and detects and specifies the power consumption caused by the unnecessary signal transitions and the location thereof.

[0013] With this, it is possible to grasp the improvement points in the circuit where power consumption can be reduced, which could not be known by the prior art, and it is possible to take efficient measures for reducing power consumption. become.

The present invention can be applied not only to the register transfer level but also to a more concrete gate level circuit (logic circuit).

In addition, by providing a result output means for presenting the detected and consuming power that can be reduced and its power consumption value to the designer, efficient low power consumption design becomes possible.

According to a second aspect of the present invention, there is provided an integrated circuit power consumption detecting system according to the first aspect, wherein the unnecessary power consumption detecting means determines that a register of interest is controlled based on a control condition when data is transferred to the register. The number of times that the condition 1 that is true when the processing result depending on the data of the register at the preceding stage is stored therein is obtained, and from this number, the register of interest that is unnecessary for the processing holds the data of the register itself. By determining the number of operations, the power consumed by the operation of holding data is detected as the unnecessary power among the power consumed by the operation of the register.

With the above configuration, the locations and amounts of power consumption that can be reduced are obtained as follows. For example, a description will be given of an edge trigger type register as shown in FIG. In the figure, R1 and R2 are registers, and G1 and G
2 is a control signal, SEL is a selector, and CK is a clock signal. The register stores the data input signal in the register at the rising edge or the falling edge of the clock signal CK, and outputs the data at the same time. As for the data input of the register, either the data output of the register itself or the data propagated from the previous register is selected by the control signal.

In this configuration, "operation for retaining data" is intended as an operation unnecessary for processing of the integrated circuit.

This will be described with reference to FIG. In the figure, when the control signal G1 is 0, the register R1 latches data from the preceding stage. When the control signal G1 is 1, the register R
1 latches its own output.

In the figure, the operation indicated by 51 is an operation for the register R1 of interest to hold its own data output immediately before by self-feedback, and power is consumed by the clock. Since the same data is stored, the data output does not change, and power consumption due to this holding operation can be reduced.

In this way, the locations and amounts of power consumption that can be reduced are specified. This has the same effect as the first aspect.

The conventional power consumption prediction (analysis / estimation) system not only does not know where power consumption can be reduced, but also applies only when logic circuit design and packaging design are completed. . For this reason, if it is necessary to significantly reduce power consumption in order to satisfy the target specification, it is necessary to start over from functional design again, and the design period is greatly increased. However, the configuration of the present invention can be used in a function design process such as a register transfer level. As a result, it is possible to suppress an increase in the period of the redesign when significantly reducing the power consumption.

Further, since a countermeasure for reducing power consumption can be taken in an earlier design process, a synergistic effect can be brought about by using it together with a technology for reducing power consumption which can be applied in a later design process, and a great reduction in power consumption can be achieved. The effect of conversion can be obtained.

Further, in the prior art, even if an attempt is made to modify a circuit in order to reduce power consumption, circuit data used for that purpose is considerably embodied as a gate level (logic level) or a transistor level (layout level). Because it is data, it is difficult to modify the circuit. On the other hand, in the configuration of the present invention, since the power consumption at the register transfer level can be known, the circuit correction work can be performed efficiently.

According to a third aspect of the present invention, there is provided an integrated circuit power consumption detecting system according to the first aspect, wherein the unnecessary power consumption detecting means determines that a register of interest is controlled based on a control condition when data is transferred to the register. The number of times that the condition 1 that is true when the processing result depending on the data of the register at the preceding stage is stored therein is obtained, and the register at the next stage stores the processing result depending on the data of the register of interest internally. The number of times that the condition 2 that is sometimes true is satisfied is obtained, and from this number, the number of times that the register of interest stores therein data that is not referred to by the register in the next stage is obtained, thereby being consumed by the operation of the register. The power consumption is detected by storing data that is not referred to in the next stage as the unnecessary power, out of the power. It is.

With the above configuration, the locations and amounts of power consumption that can be reduced are obtained as follows. The description will be made with reference to the example of FIG. In the present configuration, “operation for storing data that is not referred to” is intended as an operation unnecessary for the processing of the integrated circuit.

This is an operation in which the register R1 stores the data internally even though the data output thereof is not referred to the register R2 of the next stage, as indicated by 52 in FIG. The power is consumed when the operation unit or the like caused by the power consumed by the clock or the data output of the register R1 operates. The data output of the register R1 is propagated to the register R2 in the next stage. Even if the register R1 stores data internally, its data output does not affect the result. Therefore, power consumption due to this operation can be reduced.

In this way, the locations and amounts of power consumption that can be reduced are obtained. This has the same effect as the configuration of the first and second aspects.

According to a fourth aspect of the present invention, there is provided an integrated circuit power consumption detecting system according to the first aspect, wherein the unnecessary power consumption detecting means determines that a register of interest is controlled based on a control condition when data is transferred to the register. The number of times that the condition 1 that is true when the processing result dependent on the data of the preceding register is stored therein is determined, and the preceding register further stores the processing result that further depends on the data of the preceding register. By obtaining the number of times that the condition 3 that is true when the condition is true is obtained, the number of times the data of the register preceding the register of interest is updated is obtained.
By calculating the number of times the register of interest stores internally the processing result depending on the data that has not been updated in the register at the preceding stage, the unnecessary power consumption of the register at the preceding stage is determined as the unnecessary power consumption of the register operating. It is characterized by detecting power consumption that is consumed by storing data that has not been updated internally.

With the above configuration, the locations and amounts of power consumption that can be reduced are obtained as follows. The description will be made with reference to the example of FIG. In this configuration, an operation that is not necessary for the processing of the integrated circuit is “an operation of storing data that has not been updated”.
It is intended for.

Description will be made again with reference to FIG. In the figure, when the control signal G2 is 0, the register R2 latches data from the register R1 at the preceding stage. When the control signal G2 is 1, the register R2 latches its own output.

In the figure, as indicated by reference numeral 53, the register R2 is an operation for storing data internally even though the data has not been updated in the register R1 in the preceding stage, and is consumed by the clock to the register R2. The power is consumed when the operation unit or the like caused by the output power or the data output of the register R2 operates. When the data from the preceding register R1 is selected by the control signal as the data input of the register R2 of interest, the data not updated in the preceding register R1 and the processing result depending on the data are newly stored inside. Even if the data is stored, the data output of the register R2 does not change and does not affect the operation result. Therefore, power consumption due to this operation can be reduced.

In this way, the places and amounts of power consumption that can be reduced are obtained. This has the same effect as the configuration of the first and second aspects.

According to a fifth aspect of the present invention, there is provided an integrated circuit power consumption detection system according to any one of the first to fourth aspects, wherein the unnecessary power consumption detection means is provided between all adjacent two nodes in the circuit. A signal propagation time series storage means for storing a sequence of times at which signal propagation occurs, and an order relationship between updating and reference of the value of each node from the signal propagation time series stored by the signal propagation time series storage means. And the sequence of the number of times signal propagation that is not necessarily required for the operation of the integrated circuit occurs and the time sequence based on the order relationship between the updating and reference of the value of each node obtained by the order relationship detecting unit. And unnecessary propagation detecting means for determining

With the above configuration, information on how to modify the circuit to reduce the power consumption of the circuit can be obtained as follows.

That is, in order to distinguish between data transfer necessary for the operation of the integrated circuit and unnecessary data transfer, first, the signal propagation time-series storage means stores data between all adjacent two nodes (points) in the circuit. (Time period) in which the signal propagation occurs. The node includes, for example, a register.

Next, the order relation detecting means obtains the order relation between the update of the value of each node and the reference from the time series of signal propagation stored as described above. That is, from the time series in which data transfer occurs, a series of times at which the data of each node is updated and a series of times referred to are obtained.

Next, the unnecessary propagation detecting means determines the number and time of occurrence of signal propagation that is not necessarily required for the operation of the integrated circuit, based on the order relation between the update of each node value and the reference obtained as described above. And the series of

Then, unnecessary power consumption detecting means obtains unnecessary power consumption which is power consumption due to the unnecessary signal propagation.

As described above, unnecessary power consumption is obtained by analyzing temporal information relating to data transfer, that is, a temporal causal relationship such as an order relationship between updating and reference of the value of each node.

Thus, in addition to the effect of the configuration according to any one of the first to fourth aspects, it is possible to more finely grasp an improved part in which power consumption can be reduced in the circuit, so that more efficient low power consumption can be obtained. It is possible to take measures for the realization.

According to a sixth aspect of the present invention, in the power consumption detecting system for an integrated circuit according to the fifth aspect of the present invention, the order relation detecting means determines the order relation between the update and reference of the value of each node as "attention." Operation 1 in which the register internally stores the processing result dependent on the data of the preceding register and updates the data ”and“ The processing result dependent on the data of the register of interest is referred to by the next-stage register and stored internally. And the unnecessary propagation detecting means uses the order relation obtained by the order relation detecting means to continuously execute the operation 1. By calculating the number of times, the number of times and the number of times the non-reference data latch operation, which is an unnecessary data transfer operation in which the register of interest stores data not referenced by the register of the next stage, is performed. It is characterized by determining the sequence.

With the above configuration, information on how to modify the circuit to reduce the power consumption of the circuit can be obtained as follows.

That is, in order to distinguish between data transfer between registers necessary for the operation of the integrated circuit and unnecessary data transfer, first, the signal propagation time series storage means stores the signal propagation time series as described above. Is done.

Next, the order relation detecting means determines the order relation between the update of the value of each node and the reference, that is, the sequence of the time at which the data of each register is updated and the sequence of the referenced time, Operation 1 in which the register to be updated internally stores the processing result dependent on the data of the preceding register and updates the data, and "the processing result dependent on the data of the register of interest is stored internally with reference to the register of the next stage." To update data 2).

Next, the unnecessary propagation detecting means obtains the number of times that the state where the operation 1 is continuously executed occurs using the order relation obtained as described above, so that the register of interest is The number of times the non-reference data latch operation, which is an unnecessary data transfer operation for internally storing data not referred to by the register of the stage, and the time series are obtained. That is, after the data is updated, an operation in which the data is continuously updated before the data is referred to is detected, and the number of times of non-reference data latch and the sequence of the non-reference data latch occurrence time are calculated.

The unnecessary power consumption detecting means is caused by unnecessary signal propagation, which is consumed by storing data not referenced in the next stage in the power consumed by the operation of the register. Unnecessary power consumption that can be reduced is calculated.

As described above, as the above-mentioned order relation between the updating and the reference of the value of each node, the unnecessary power consumption is obtained by analyzing the order relation concerning the operation of latching the data not referred to in the register. Thus, in addition to the effect of the configuration according to any one of claims 1 to 4, it is possible to more finely grasp an improved portion in the circuit in which power consumption can be reduced, thereby achieving more efficient and lower power consumption. Measures can be taken.

According to a seventh aspect of the present invention, in the integrated circuit power consumption detecting system according to the fifth aspect, the order relation detecting means sets the "attention" as the order relation between updating and reference of the value of each node. An operation 1 in which a register internally stores a processing result that depends on data in a preceding register and updates data ”and“ a processing in which a preceding register that transfers data to a register of interest is further dependent on data in a preceding register ” An operation 3 in which the result is internally stored and the data is updated is obtained, and the unnecessary propagation detecting means continuously executes the operation 1 using the order relation obtained by the order relation detecting means. Unnecessary data that stores the processing result depending on the data that has not been updated in the previous register It is characterized by determining the number and time series unupdated data latch operation that is a feeding operation is performed.

According to the above configuration, information on how to modify the circuit to reduce the power consumption of the circuit can be obtained as follows.

That is, in order to distinguish between data transfer between registers necessary for the operation of the integrated circuit and unnecessary data transfer, first, the signal propagation time series storage means stores the time series of signal propagation as described above. Is done.

Next, the order relation detecting means sets the order relation between the updating and reference of the value of each node, that is, the sequence of the time at which the data of each register is updated and the sequence of the referenced time as " Operation 1 in which the register to be updated internally stores a processing result that depends on the data in the preceding register and updates the data ”and“ the preceding register that transfers the data to the register of interest further depends on the data in the preceding register. Operation 3 for storing the processing result internally and updating the data ”is obtained.

Next, the unnecessary propagation detecting means continuously performs the operation 1 by using the order relation obtained as described above.
By determining the number of times the state where
The number of times and the sequence of times at which an unupdated data latch operation, which is an unnecessary data transfer operation for storing data in which a register of interest is not updated by a register at the preceding stage and a processing result dependent on the data, is performed. That is, after the register refers to the data of the preceding register, the operation of continuously referring to the data before the preceding register is not updated is detected, and the series of the number of times of unupdated data latch and the time of occurrence of unupdated data latch are detected. Is calculated.

Then, the unnecessary power consumption detecting means is caused by unnecessary signal propagation, which is consumed by storing therein data which has not been updated in the previous stage among power consumed by operation of the register. Unnecessary power consumption, which is power that can be reduced, is calculated.

As described above, as the above-mentioned order relation between the updating and reference of the value of each node, the unnecessary power consumption is obtained by analyzing the order relation concerning the operation of latching the data whose register has not been updated. Thus, in addition to the effect of the configuration according to any one of claims 1 to 4, it is possible to more finely grasp an improved portion in the circuit in which power consumption can be reduced, thereby achieving more efficient and lower power consumption. Measures can be taken.

According to an eighth aspect of the present invention, in the power consumption detecting system for an integrated circuit according to the fifth aspect, the order relation detecting means determines the order relation between the updating and reference of the value of each node as "attention." Operation 1 in which the register internally stores the processing result dependent on the data of the preceding register and updates the data ”and“ The processing result dependent on the data of the register of interest is referred to by the next-stage register and stored internally. 2 in which data is updated to a register of interest, and "operation 3 in which a preceding register for transferring data to a register of interest further stores therein a processing result dependent on the data of the preceding register and updates the data." Determining the number of times that the state where the operation 1 is continuously executed occurs using the order relation obtained by the order relation detecting means. More, the number and the time series of unnecessary data transfer operation to store the registers of interest is not referenced by the next register data therein is carried out, and,
The register of interest obtains the number of times an unnecessary data transfer operation in which a processing result dependent on data not updated in the register at the preceding stage is performed is performed and a series of times, and further, the unnecessary power consumption detecting means includes: Using the order relation obtained by the order relation detecting means, a data holding detecting means for obtaining the number of times the register of interest performs an operation of holding data and a time series, and a non-detection signal detected by the unnecessary propagation detecting means. A union of a period in which the reference data latch operation is performed, a period in which the unupdated data latch operation is performed, and a period in which the data holding operation detected by the data holding detection unit is performed is determined. Unnecessary operation period detecting means for obtaining a series of times at which unnecessary register operations occur.

According to the above configuration, information on how to modify the circuit to reduce the power consumption of the circuit can be obtained as follows.

That is, first, in the same manner as in claims 6 and 7, the unnecessary propagation detecting means obtains the number of times that the state where the operation 1 is continuously executed occurs, so that the register to be focused on is in the next stage. A sequence of the number and time of unnecessary data transfer operations in which data that is not referenced by the register is stored internally, and data whose target register has not been updated in the previous register and processing results dependent on that data are stored internally. The number of times the unnecessary data transfer operation is performed and the time series are stored.

The data holding detecting means obtains the number of times the register of interest performs data holding operation and the time series by using the order relation obtained by the order relation detecting means.

The unnecessary operation period detecting means includes a time series in which the non-reference data latch operation detected by the unnecessary propagation detecting means is performed, a time series in which the non-updated data latch operation is performed, and the data holding detecting means. And the time series in which the data holding operation detected is performed, ie,
A union of each period is obtained, and a series of times at which unnecessary register operations occur successively is obtained.

As described above, a period in which unnecessary register operations continuously occur is obtained. As a result, information on the detected unnecessary operation can be processed to provide the designer with useful information for reducing power consumption. That is, in addition to the effects of the configuration according to any one of claims 1 to 4,
In order to reduce power consumption, the designer can know the period during which the clock operation for driving the register can be stopped, so that more efficient power consumption reduction measures can be taken.

[0062]

BEST MODE FOR CARRYING OUT THE INVENTION

[Embodiment 1] An embodiment of the present invention will be described below with reference to FIGS.
As shown in FIG. 2, the present system 1 as an integrated circuit power consumption detection system includes an unnecessary circuit operation identification unit 2, a load capacity calculation unit 6, a power consumption calculation unit 7, and a result output unit 8. These constitute an unnecessary power consumption detecting means. The unnecessary circuit operation identifying means 2 includes a condition extracting means 3, a transition frequency calculating means 4, and an unnecessary circuit operating frequency calculating means 5.

As the present system 1, for example, a computer 60 as shown in FIG. 13 can be used. The computer 60 has a CPU (central processing unit) 6 therein.
1, a ROM (read only memory) 62, a RAM (random access memory) 63, an HDD (hard disk drive) 64, an FDD (floppy disk drive) 65, and a CRT (cathode tube) display 66 as an output unit. Via the HDD 64,
A hard disk 67 as a data storage unit is connected. A floppy disk 68 is connected via the FDD 65.

The output section outputs power consumption data described later as the result output means 8. In addition to the CRT display 66, a display device such as an LCD (liquid crystal display device) or a printing device such as a printer is provided. Can be used.

In the present system 1, the unnecessary circuit operation identifying means 2, the load capacity calculating means 6, and the power consumption calculating means 7 can be realized as functional modules comprising the CPU 61 and a computer program. This computer program is stored in the ROM 62 as a recording medium or in an external storage device such as the floppy disk 68 or the hard disk 67, and is stored in the RAM when the system starts up.
63.

The user, that is, the designer of the electronic circuit, stores in advance the above-mentioned various data such as various circuit data and operating voltage in the data storage section. These various data are input from the data storage unit to the unnecessary circuit operation identifying unit 2 and the load capacity calculating unit 6.

As will be described later, the load capacity calculating means 6
This is to calculate the load capacity of each signal. The condition extracting means 3 extracts a register transfer condition, a next-stage register reference condition, and a preceding-stage register update condition. The number-of-transitions calculation means 4 calculates the number of transitions of the signal.

FIG. 1 shows details of the unnecessary circuit operation identifying means 2. The condition extracting means 3 includes a data flow graph extracting means 2
1, a register transfer condition extracting means 22, a next-stage register reference condition extracting means 23, and a preceding register updating condition extracting means 24.

The number-of-transitions calculating means 4 includes the number-of-clock-supplying-times calculating means 25 and the number-of-registrations-for-register-transfer-conditions calculating means 2
6, a next-stage register reference condition satisfaction count calculation means 27 and a preceding-stage register update condition satisfaction count calculation means 28 are provided.

The unnecessary circuit operation number calculation means 5 includes a data holding operation number calculation means 29, a non-reference data latch number calculation means 30, and an unupdated data latch number calculation means 31.
have.

Circuit data (circuit description at functional level and connection information at logical level) Operation specification of input / output signals of integrated circuit The terminal of the minimum unit component constituting a circuit such as an arithmetic unit and a logical circuit is once A load capacity operating voltage charged / discharged by the change is input to each means from the data storage unit.

The circuit data is circuit connection information, such as a netlist and a cell library. In the prior art, circuit connection information at a gate level (logic level) or a transistor level (layout level)
However, in this embodiment, in addition to the above, circuit connection information at the register transfer level can be used, and when circuit connection information at the register transfer level is used, Most effective in reducing power.

The above includes test patterns, switching information, and the like.

The above is expressed in a broader sense as a power consumption library in FIG. 2 as basic data (parameters) for each element for calculating power consumption. These may include a through current, a leak current, and the like.

The data flow graph extracting means 2
1 extracts a clock signal supplied to a register, connection information between registers, a load capacity of a path between registers to which data is transferred, and information of a control condition when data is referred to between registers.

As described above, in the present system, instead of the conventional means for calculating the number of signal transitions, the register transfer condition extracting means 22, as shown in the dashed box in FIG. 2 and shown in FIG.
The next-stage register reference condition extracting means 23 and the preceding-stage register update condition extracting means 24 determine from the control conditions when data is referenced between the registers extracted above: a register transfer condition (RTC); Condition (RC) ・ Extract pre-stage register update condition (UC).

The register transfer condition (RTC) is a condition that is true when the register of interest stores therein any of the registers in the preceding stage and a processing result dependent on the data. Next-stage register reference condition (R
C) is a condition that is true when any of the registers from the register of interest to the register at the next stage stores therein the data of the register of interest and the processing result dependent on the data. The preceding register update condition (UC) is a condition that becomes true when any of the registers in the preceding stage of the register of interest updates data.

The clock supply frequency calculation means 25, the register transfer condition satisfaction frequency calculation means 26, the next register reference condition satisfaction frequency calculation means 27, and the preceding register update condition satisfaction frequency calculation means 28 are: The number of times the register transfer condition is satisfied (RTA) The number of times the next-stage register reference condition is satisfied (RA) The number of times the previous-stage register update condition is satisfied (UA)

The clock supply count (CA) is the number of times the clock is supplied to the register per unit time.
The number of times the register transfer condition is satisfied (RTA) is the number of times that the register transfer condition (RTC) is satisfied per unit time. The number of times the next-stage register reference condition is satisfied (RA) is the number of times that the next-stage register reference condition (RC) is satisfied per unit time. Number of times the previous-stage register update condition was satisfied (U
A) is the number of times that the pre-stage register update condition (UC) is satisfied per unit time.

By providing these means, it is possible to identify necessary signal transitions and unnecessary signal transitions, and to obtain the number of unnecessary signal transitions.

Further, the power consumption calculating means 7 of the present system
Is the power consumption that can be reduced. 1. Power consumption of data holding operation (HP) The power consumption of the operation of storing data that is not referenced (N
RP) 3. The power consumption (NUP) of the operation of storing data that has not been updated is calculated.

The power consumption (HP) of the data holding operation is as follows.
From the number of times the clock of each register is supplied and the number of times the register transfer condition is satisfied, the number of operations for holding the register value is obtained by the data holding operation number calculating means 29 shown in FIG. This is the power consumption resulting from the operation for retaining data, which is obtained from the load capacity connected to the register and the operating voltage. This is one of the unnecessary power consumption.

The power consumption (NRP) of the operation of storing data that is not referred to is determined based on the number of times the register transfer condition of each register is satisfied and the number of times that the next-stage register reference condition is satisfied. Non-reference data latch frequency calculating means 30 shown in FIG.
And the power consumption resulting from the operation of internally storing data that is not referred to by the register, which is obtained from the number of times, the load capacity connected to each register, and the operating voltage. This is one of the unnecessary power consumption.

The power consumption (NUP) of the operation of storing data that has not been updated is determined by the number of times that each register satisfies the register transfer condition and the number of times that the preceding register update condition is satisfied. The number of times the data is stored internally is obtained by the unupdated data latch frequency calculating means 31 shown in FIG. 1, and the data whose register has not been updated, which is obtained from the number of times and the load capacity and the operating voltage connected to each register, is internally stored. This is the power consumption due to the storing operation. This is one of the unnecessary power consumption.

The present system is provided with means for discriminating between a circuit operation required for processing to be performed by the integrated circuit and an unnecessary circuit operation as described above, and holds data of a register, which is an unnecessary circuit operation. The number of times the operation, the operation of storing unreferenced data internally, and the operation of storing unupdated data internally are determined, and the power consumed due to unnecessary operations and the location thereof are detected. .

[0086] As shown in FIG.
Is detected by the above means by the result output means 8,
The places where the power that can be reduced are consumed and the power consumption values are presented to the designer of the electronic circuit. The designer designs based on the result. For this reason, efficient low power consumption design becomes possible.

Further, since a countermeasure for reducing power consumption can be taken in an earlier design process, a synergistic effect is brought about by using it together with a technology for reducing power consumption which can be applied in a later design process, and a great reduction in power consumption is achieved. The effect of conversion can be obtained.

Further, in the prior art, even if an attempt is made to modify a circuit in order to reduce power consumption, circuit data used for that purpose is considerably embodied as a gate level (logic level) or a transistor level (layout level). Because it is data, it is difficult to modify the circuit. On the other hand, in the above configuration, since the power consumption at the register transfer level can be known, the circuit correction work can be performed efficiently.

Next, the procedure for performing the power consumption detecting operation will be described below. 1. First, the following conditions are extracted for all the registers. First, the data flow graph extracting means 21 controls the connection information of the registers and the control conditions when data is referred to between the registers based on the circuit diagram of the register transfer level shown in FIG. Is represented by a data flow graph as shown in FIG. 7 to FIG. Then, the following processing is performed.

Hereinafter, as shown in FIGS. 6 and 7, each register is represented by a, b, c, d, e, and f, and is represented by x as a representative. Each control circuit and its corresponding data transfer condition between registers are represented by the same symbol, that is, G
a, Gb, Gc, Gs, Ge, and Gf. The clock signal is represented by CLK. Input data is represented by D1, D2, and D3. The output signals are represented by O1 and O2. The clock name supplied to each register is CKNx (where x
Are a, b, c, d, e, and f corresponding to the register names). These are all CLK here. The power consumed by a single clock supply to each register is CKPx (where x is a, b, c, d, e, f, corresponding to the register name). The power consumed by a single change in the data output of each register x is DOPx (where x is a,
b, c, d, e, f). The operating voltage is V, and the value is 3 in this case.

Extraction of Register Transfer Condition (RTC) The register transfer condition is a condition that becomes true when the register of interest stores therein the data from the preceding register and the processing result dependent on the data of the preceding register. is there.

This is because when one or more data transfer paths from the preceding register are extracted from the data flow graph by using the register transfer condition extracting means 22, and data is transferred on each data transfer path. Is obtained by calculating the logical sum of the control conditions. When this condition becomes true, the register of interest stores therein the data of the register at the preceding stage and the processing result depending on the data. However, when there is no preceding register, data transfer to the register always occurs.

As shown in FIGS. 8 and 9, the register d
Pay attention to. The RTC in the register d is defined as RTCd. Similarly, for registers a, b, c, e, and f, R
TCa, RTCb, RTCc, RTCe, and RTCf.

Data is transferred to the register d when: Gs = 1, the data from the register a is stored via the multiplier. When Gs = 1 or Gs = 0, the multiplier or adder is stored. The data from the register c is stored via the adder when Gs = 0 when Gs = 0.

Therefore, the register transfer condition RTCd of the register d is satisfied when any of the above three conditions is true, that is, RTCd = (Gs = 1) or (Gs = 1 or Gs = 0) or (Gs = 0) ) (2).

RTCa, RTCb, RTCc, RTC
e and RTCf are similarly obtained.

Extraction of Next-Stage Register Reference Condition (RC) The next-stage register reference condition means that one of the registers at the next stage of the register of interest is used to output the data of the register of interest or the data output of the register of interest. This condition is true when the dependent processing result is stored internally.

This is because the next stage register reference condition extracting means 2
3, the data transfer path to the next-stage register is extracted from the data flow graph, and is extracted by calculating the logical sum of the control conditions when data is transferred on the data transfer path. When this condition becomes true, the data output of the register of interest and the processing result depending on the data output are stored in one of the registers in the next stage. However,
When there is no next-stage register, data is always referred to.

Similarly, attention is paid to the register d. Hereinafter, RC in the register d is referred to as RCd. Similarly, for registers a, b, c, e, and f, RCa, RCb, RC
c, RCe, and RCf.

The data in the register d is referred to when the register e stores the data via the NOT circuit when Gd = 1, and when the register f stores the data when Gf = 1.

Therefore, the next-stage register reference condition RCd of the register d is obtained when either of the above two conditions is true, that is, RCd = (Ge = 1) or (Gf = 1) (3) .

RCa, RCb, RCc, RCe, RCf
Is similarly obtained.

Extraction of Pre-Register Register Update Condition (UC) The pre-stage register update condition is a condition that becomes true when any of the registers at the preceding stage of the register of interest updates data.

This means that the pre-stage register update condition extracting means 2
(4) extracting one or more data transfer paths to the preceding register from the data flow graph, obtaining the register transfer conditions of the individual previous registers, and calculating the logical sum of the register transfer conditions (RTC) Extract by When this condition becomes true, the data is updated in one of the registers in the preceding stage. However, it is assumed that data is always updated when there is no preceding register.

Similarly, attention is paid to the register d. Hereinafter, UC in the register d is referred to as UCd. Similarly, for registers a, b, c, e, and f, UCa, UCb, UC
c, UCe, and UCf.

The input data to the register d is updated when Ga = 1, the data in the register a is updated, when Gb = 1, the data is updated in the register b, and when Gc = 1, the register is updated. Since the data is updated to the register c, the condition UCd for updating the register at the preceding stage of the register d is used.
Is when any of the above three conditions is true, that is, UCd = (Ga = 1) or (Gb = 1) or (Gc = 1) (4)

UCa, UCb, UCc, UCe, UCf
Is similarly obtained.

The above extraction is performed. The order of extraction of the three conditions does not matter.

2. Calculation of the Numbers of CA, RTA, RA, and UA Next, as shown in FIGS. 10 and 11, the number of times that each of the following conditions per unit time is satisfied for each register as shown in FIGS. Is calculated.
For this, for example, a dynamic method by simulation or a static method by propagation of switching information can be used.

That is, the clock supply frequency calculating means 25
Is the number of times C that the clock signal is supplied to each register.
Ask for A. The number of times RTA in which the register transfer condition RTC is satisfied is obtained by the register transfer condition satisfaction number calculation means 26. The next-stage register reference condition satisfaction count calculation means 27 calculates the number of times RA that the next-stage register reference condition RC is satisfied. The number of times UA in which the preceding-stage register update condition UC is satisfied is obtained by the preceding-stage register updating condition satisfaction number calculating means. Note that the CAs for the registers a, b, c, d, e, and f are CAa, CAb, CAc, CAd, CAd, respectively.
CAe and CAf. The same applies to RTA, RA, and UA.

However, when the register transfer condition RTC is always satisfied, the number of times the clock is supplied as the number of times the condition is satisfied RTA is set to the same value. When the next-stage register reference condition RC and the previous-stage register update condition UC are always satisfied, the number of times RA and UA are satisfied are the same as the number of times RTA is satisfied.

In this embodiment, it is assumed that the number of times shown in FIG. 11 has been obtained for each register shown in FIG.

3. HP, NR for all registers
Calculation of P and NUP Next, the following powers are obtained for each register.

The power consumed by the operation of holding data in the register (HP) By using the data holding operation number calculating means 29 and the power consumption calculating means 7 shown in FIG. (The number of times RTA becomes true), the number of times CA supplied with the clock, and the load capacitance C that is charged and discharged by supplying the clock once to the register of interest.
From KC and the operating voltage V, HP = (CA-RTA) × CKC × V ² (5) When HP> 0, the power consumption can be reduced; otherwise, there is no power consumption that can be reduced. In the present embodiment, HPa to HPf of each register are as follows.

[0115] HPa = (CAa-RTAa) × CKCa × V 2 = (10-7) × 1 × 3 2 = 27 (6) HPb = (CAb-RTAb) × CKCb × V 2 = (10-10) × ^{1 × 3 2 = 0 (7} ) HPc = (CAc-RTAc) × CKCc × V 2 = (10-3) × 1 × 3 2 = 63 (8) HPd = (CAd-RTAd) × CKCd × V 2 = ^{(10-10) × 1 × 3 2} = 0 (9) HPe = (CAe-RTAe) × CKCe × V 2 = (10-6) × 1 × 3 2 = 36 (10) HPf = (CAf-rTAf) × CKCf × V ² = (10−3) × 1 × 3 ² = 63 (11) In FIG. 7, as described above, for example, CKCa ×
The value of V ^2, expressed as a power CKPa consumed by the clock is supplied once to register a, it is also shown that value. The same applies to the registers b, c, d, e, and f.

Power consumed by storing data that is not referenced internally (NRP) Register transfer to a register of interest occurs using the non-reference data latch frequency calculation means 30 and the power consumption calculation means 7 shown in FIG. (The number of times the register transfer condition becomes true RTA), the number of times that the data output of the register of interest is referenced by the next-stage register (the number RA of times that the next-stage register reference condition becomes true), and the data of the register of interest. Load capacity DOC charged / discharged when output changes once
NRP = (RTA-RA) × DOC × V ² (12) When NRP> 0, the power consumption can be reduced, otherwise, there is no power consumption that can be reduced.
In the present embodiment, NRPa to NRPf of each register are as follows.

[0117] NRPa = (RTAa-RAa) × DOCa × V 2 = (7-7) × 10 × 3 2 = 0 (13) NRPb = (RTAb-RAb) × DOCb × V 2 = (10-10) × ^{15 × 3 2 = 0 (14} ) NRPc = (RTAc-RAc) × DOCc × V 2 = (3-3) × 5 × 3 2 = 0 (15) NRPd = (RTAd-RAd) × DOCd × V 2 = ^{(10-6) × 2 × 3 2} = 72 (16) NRPe = (RTAe-RAe) × DOCe × V 2 = (6-6) × 3 × 3 2 = 0 (17) NRPf = (rTAf-RAf) ^{× DOCf × V 2 = (3-3} ) × 2 × 3 2 = 0 (18) in addition, in FIG. 7, as described above, for example, Doca ×
The value of V ^2, expressed as a power DOPa consumed by the data output of the register a is changed once, and are also shown its value. The same applies to the registers b, c, d, e, and f.

Power consumed by storing unupdated data inside (NUP) Register transfer to the register of interest using unupdated data latch count calculating means 31 and power consumption calculating means 7 shown in FIG. (The number of times RTA where the register transfer condition becomes true), the number of times the register preceding the register of interest updates the data (the number of times UA where the preceding register update condition becomes true), and the data output of the register of interest Is changed once, and the load capacity DOC is charged and discharged.
From the operating voltage V, NUP = (RTA−UA) × DOC × V ² (19) When NUP> 0, the power consumption can be reduced. Otherwise, there is no power consumption that can be reduced.
In the present embodiment, NUPa to NUPf of each register are as follows.

NUPa = (RTAa−UAa) × DOCa × V ² = (7−7) × 10 × 3 ² = 0 (20) NUPb = (RTAb−UAb) × DOCb × V ² = (10−10) × ^{15 × 3 2 = 0 (21} ) NUPc = (RTAc-UAc) × DOCc × V 2 = (3-3) × 5 × 3 2 = 0 (22) NUPd = (RTAd-UAd) × DOCd × V 2 = ^{(10-10) × 2 × 3 2} = 0 (23) NUPe = (RTAe-UAe) × DOCe × V 2 = (6-10) × 3 × 3 2 = -108 (24) NUPf = (rTAf-UAf ^{) × DOCf × V 2 = (} 3-10) × 2 × 3 2 = -126 (25) 4. Calculation of Power Consumption of Entire Circuit Using the power consumption calculating means 7 shown in FIGS. 1 and 2, the number of state transitions N of each signal in the circuit, the load capacitance C of the minimum unit component connected to each signal, From the operating voltage V, the power consumption P of the whole circuit is calculated by P = Ｐ (N × C) × V ² (26). In the present embodiment, it is assumed that P = 1000 has been obtained by calculation.

[0120] 5. Result Output Using the result output means 8 shown in FIG. 2, for all the registers, the register names and the calculated reducible power consumption H
Outputs P, NRP, and NUP.

In this embodiment, the power consumption P of the entire circuit
= 1000, (a) Power consumption NRPD when data not referenced by register d is stored internally 72 (b) Power consumption HPc when register c performs an operation of holding data HPc = 63 (c) Register Power consumption when f performs data holding operation HPf = 63 (d) Power consumption when register e performs data holding operation HPe = 36 (e) When register a performs data holding operation Is output as reducible power consumption.

If the circuit of the register transfer level in FIG. 6 is reduced in power consumption based on the above result, for example, a circuit as shown in FIG. 12 can be obtained. That is,
The clock is controlled by the control circuits Ga, Gb, Gc, Gs, Ge,
And Gf, each register (af)
, And a gated clock is supplied to each register only when necessary. This eliminates signal transitions that occur when unnecessary data is propagated, thereby achieving low power consumption.

[Embodiment 2] Another embodiment of the present invention will be described below with reference to FIGS. 2, 14 and 15. For convenience of explanation, members having the same functions as the members shown in the drawings of the above-described embodiment are denoted by the same reference numerals, and description thereof will be omitted.

The power consumption detection system for an integrated circuit according to the present embodiment has the same load capacity calculation means 6, power consumption calculation means 7, and result output means 8 as in the first embodiment shown in FIG. ing. Further, an unnecessary circuit operation identifying means 42 shown in FIG. 14 is provided instead of the unnecessary circuit operation identifying means 2 shown in FIG. Unnecessary power consumption detecting means is constituted by the load capacity calculating means 6, the power consumption calculating means 7, the result output means 8 and the unnecessary circuit operation identifying means 42. All of the above-mentioned means are the same as in the first embodiment.
And a computer program.

As shown in FIG. 14, the unnecessary circuit operation identification means 42 includes a data flow graph extraction means 21, a clock operation / data transfer time series storage means for storing a clock operation and a time series in which data transfer occurs. (Signal propagation time series storage means) 71, update / reference time series calculation means (order relation detection means) 72 for calculating a time series of register data update and data reference, data holding operation time series calculation means (data Holding detection means) 73, non-reference data latch frequency / time series calculation means (unnecessary propagation detection means) 74, unupdated data latch frequency / time series calculation means (unnecessary propagation detection means) 75, and unnecessary register operation occurrence period detection means (Unnecessary operation period detection means) 76 is provided.

Next, an outline of the unnecessary circuit operation identifying operation will be described. 1. A control condition when data is referred to between registers is set as a register transfer condition, and the condition is extracted by the data flow graph extracting means 21.

[0127] 2. The clock operation / data transfer time series storage means 71 performs a simulation or the like and stores the time at which all register transfer conditions are satisfied.

3. For all the registers, (a) the data holding operation time series calculating means 73 refers to the time series of the clock operation supplied to drive the register of interest and the data stored in the register by referring to the data of the register in the preceding stage. Is obtained from the time series of the operation of updating the data.

(B) In the non-reference data latch frequency / time series calculation means 74, the register of interest refers to the register of the preceding stage to store data therein, and before the data is referred to the next stage, The number of times of internal storage with reference to the next data is counted, and the number is referred to as the number of non-reference data latches (NRA) of the register of interest. In addition, a series of times at which the non-reference data latch operation occurs is calculated.

(C) In the unupdated data latch count / time-series reference means 75, after the register of interest refers to the register of the preceding stage and stores the data therein, the data is noted before the data of the register of the preceding stage is updated. The number of times the register refers to the data again is counted, and the number is referred to as the unupdated data latch operation number (NUA) of the register of interest. Further, a series of times at which an unupdated data latch operation occurs is calculated.

With these operations, the number of unnecessary data latch operations (NRA and NUA) is obtained.

4. The power NRP consumed by storing the unreferenced data in the register is calculated by the following equation: NRP = NRA × DOC × V ² (27), similarly to the equation (12) in the first embodiment.

5. The power NUP consumed by storing the data that has not been updated in the register is determined by the following equation: NUP = NUA × DOC × V ² (28), similarly to the equation (19) in the first embodiment.

6. For each register, a period during which an unnecessary register transfer operation continuously occurs is obtained using the unnecessary register operation occurrence period detecting means 76.

For each register, the sequence of the time (clock cycle) at which the data holding operation occurs, which is obtained by the data holding operation time series calculating means 73, the number of non-reference data latch times, and the time series calculating means 74 The sequence of the time at which the obtained non-reference data latch operation occurs. The number of times of the unupdated data latch operation. The time at which the unupdated data latch operation occurs obtained by the time series calculating means 75. These sequences are merged. This is performed by obtaining a sequence of times at which unnecessary register operations occur.

The first time in the time series of the unnecessary register operation is recorded as the start time of the unnecessary register operation generation period. Subsequently, scanning is performed toward the newest time, and when an unnecessary register operation occurs at successive times, that time is recorded (updated) as the end time of the unnecessary register operation occurrence period, and the number of consecutive occurrences is increased by one. When the times are not continuous, the start time and end time of the unnecessary register operation occurrence period recorded so far are recorded as the unnecessary register operation occurrence period, and the start time is updated.

Next, a specific example of the calculation of the number of non-reference data latches and the calculation of the number of unupdated data latches will be described. As shown in FIG. 15, the register a and the control circuit G
b, a register b, a control circuit Gc, and a register c. The control condition when data is transferred from the register a to the register b is represented by Gb as in the circuit name. Register b
The control condition when the data is transferred from the register to the register c is represented by Gc, like the circuit name. The registers a, b, and c are supplied with a clock in each clock cycle. It is assumed that the register a stores the data inside the register with reference to the data of the preceding register every clock cycle. Cycle1, cycle each successive clock cycle
2, ..., cycle12. Transfer the data x1, x2,
..., x12. Arrows RT1 to RT11 in the figure
Indicates that data is transferred between registers.

(Calculation of Number of Non-reference Data Latch) Attention is paid to the register b. In cycle2 (arrow RT1), register b
Refers to the data x1 of the register a and stores it internally. Since this data x1 is referred to by the register c in cycle 3 (RT2), it is not wasteful that the register b stores the data x1.

However, in cycle 7 (RT6), register b
The next data x7 is stored in the register b in cycle 8 (RT7) before the data x6 stored in is stored in the register c in the next stage. Therefore, data x6 is stored in register b
(RT6) is a useless operation (non-reference data latch operation).

Looking at the cycles from cycle 1 to cycle 12, the register b stores six data of x1, x4, x6, x7, x8, x11. Of those, the register c refers to
x1, x4, x7, x8. Therefore, the register b stores two unreferenced data, and the number of non-reference data latches NRAb is two.

On the other hand, in this data transfer example,
When data transfer is analyzed by the method described in the first embodiment,
Since the number of times RTAb at which the register b refers to the data of the register a at the preceding stage is six, and the number of times RAb at which the register b is referred to from the register c at the next stage is five, the number of non-reference data latches of the register b NRAb is given by NRAb = RTAb-RAb = 6-5 = 1 (29), and the number of non-reference data latches is one.

An example of detecting the non-reference data latch operation will be described. A reference flag is provided for each register. This reference flag is reset when the register updates the data, that is, when the data in the register at the preceding stage is referred to and stored internally. On the other hand, when the stored data is referred to, that is, when the next-stage register refers to the data and stores it internally, the reference flag is set.

Here, if the reference flag is not set when the register of interest stores data, it means that the data stored in the previous cycle was not referred to the register of the next stage. At this time, the number of non-reference data latches of the register of interest is increased by one. On the other hand, when the register of interest stores data, if the reference flag has already been set in that register, the data stored in the previous cycle has been effectively used, that is, referred to by the next-stage register. It will be.

(Calculation of Unupdated Data Latch Number) Attention is paid to the register c. In cycle3 (arrow RT2), register c
Refers to the data x1 of the register b and stores it internally. The register c also refers to the data of the register b in cycle 5 (RT3). However, this data is available in cycle3 (RT
This is the same as the data x1 referred to in 2), and this data does not need to be stored again. Therefore, cycl
The operation (RT3) of storing this data in the register c at e5 is a useless operation (unupdated data latch operation).

Looking at the cycles from cycle 1 to cycle 12, the register c stores the data of the register b five times (RT2, RT3, RT5, RT8, RT10), but four types of x1, x4, x7, x8 Only the data is stored. Therefore, the register c stores one unupdated data, and the number NUA of unupdated data latches is one.

In contrast, in this data transfer example,
When data transfer is analyzed by the method described in the first embodiment,
Since the number of times RTAc in which the register c refers to the data of the register b in the preceding stage is 5 and the number of times UAc in which the register b refers to the data in the register a of the preceding stage is 6, the number of unupdated data latches in the register c is NUAc is as follows: NUAc = RTAc−UAc = 5−6 = −1 (30) Since this is a negative value, the unupdated data latch count is zero.

An example of detecting the non-reference data latch operation will be described. An update flag is provided for each register. It is assumed that this update flag is set when the register updates the data, that is, when the data is stored internally with reference to the data of the register in the preceding stage. On the other hand, when the stored data is referred to, that is, when the register of the next stage refers to the data and stores it internally, the reference flag is reset.

Here, when the register of interest refers to the data of the register of the preceding stage, if the reference flag, that is, the reference flag of the register of the preceding stage is not set, the register of interest refers to the data that has not been updated. Will do. At this time, the number of unupdated data latches of the register of interest is increased by one. On the other hand, when the register of interest refers to the data of the register at the preceding stage, if the update flag has already been set in the register of the reference destination, the register of interest stores the updated data internally .

(Calculation of Unnecessary Register Operation Occurrence Period) Focusing on the register b, the sequence of the time (clock cycle) at which the data holding operation of the register b occurs is {3, 4, 6,
10, 11}. The time sequence at which the non-reference data latch operation occurs is {7, 12}. The sequence of times at which the unupdated data latch operation occurs is φ (empty set: none). When these three sequences are merged, the sequence of times when the unnecessary register operation of the register b occurs is {3, 4, 6,
7, 10, 11, 12}. From this, when a series of times at which unnecessary register operations occur continuously is obtained,
{3, 4}, {6, 7}, {10, 11, 12}, and the designer can understand that unnecessary register operations are continuously occurring over a maximum of three clock cycles.

[0150]

As described above, the integrated circuit power consumption detection system according to the first aspect of the present invention provides an integrated circuit based on the number of signal transitions of each element of the integrated circuit, the load capacitance, and the operating voltage of each signal. In the integrated circuit power consumption detection system for determining the power consumption of the integrated circuit, among the signal transitions, signal transitions required for processing to be performed by the integrated circuit and unnecessary signal transitions are identified, and the number of signal transitions unnecessary for the processing is determined. This configuration includes an unnecessary power consumption detecting unit that detects the unnecessary power consumption, which is the power consumption resulting from the unnecessary operation, by using the number of unnecessary signal transitions.

The recording medium on which the computer program for determining the power consumption of the integrated circuit according to the ninth aspect is recorded can be obtained from the number of signal transitions of each element of the integrated circuit, the load capacitance, and the operating voltage of each signal. A recording medium on which a computer program for calculating power consumption is recorded, wherein, among the signal transitions, signal transitions required for processing to be performed by an integrated circuit and unnecessary signal transitions are identified, and the number of signal transitions unnecessary for the processing is identified. And a computer program for calculating the unnecessary power consumption, which is the power consumption due to the unnecessary operation, using the unnecessary signal transition count.

Therefore, it is possible to present information on unnecessary power consumption points in the circuit, and to know the designer how to correct the circuit to reduce the power consumption when the specification is not satisfied. Therefore, there is an effect that it is possible to take efficient measures for reducing power consumption.

According to a second aspect of the present invention, there is provided an integrated circuit power consumption detection system, wherein the unnecessary power consumption detection means determines that a register of interest is controlled based on a control condition when data is transferred to the register. The number of times that the condition 1 that is true when the processing result depending on the data of the register at the preceding stage is stored therein is obtained, and from this number, the register of interest that is unnecessary for the processing holds the data of the register itself. By calculating the number of operations, the power consumed by the data holding operation is detected as the unnecessary power among the power consumed by the operation of the register.

According to a third aspect of the present invention, there is provided an integrated circuit power consumption detection system, wherein the unnecessary power consumption detection means determines that a register of interest is controlled based on a control condition when data is transferred to the register. The number of times that the condition 1 that is true when the processing result depending on the data of the register at the preceding stage is stored therein is obtained, and the register at the next stage stores the processing result depending on the data of the register of interest internally. The number of times that the condition 2 that is sometimes true is satisfied is obtained, and from this number, the number of times that the register of interest stores therein data that is not referred to by the register in the next stage is obtained, thereby being consumed by the operation of the register. The power consumption is detected by storing data that is not referred to in the next stage as the unnecessary power in the power.

According to a fourth aspect of the present invention, there is provided an integrated circuit power consumption detecting system according to the first aspect, wherein the unnecessary power consumption detecting means determines that a register of interest is controlled based on a control condition when data is transferred to the register. The number of times that the condition 1 that is true when the processing result dependent on the data of the preceding register is stored therein is determined, and the preceding register further stores the processing result that further depends on the data of the preceding register. By obtaining the number of times that the condition 3 that is true when the condition is true is obtained, the number of times the data of the register preceding the register of interest is updated is obtained.
By calculating the number of times the register of interest stores internally the processing result depending on the data that has not been updated in the register at the preceding stage, the unnecessary power consumption of the register at the preceding stage is determined as the unnecessary power consumption among the power consumed by the operation of the register. This is a configuration for detecting power consumption that is consumed by storing data that has not been updated internally.

Therefore, in each of the configurations of claims 2 to 4, in addition to the effect of the configuration of claim 1, it is possible to suppress an increase in the period of redesign when significantly reducing power consumption. It has the effect of being able to do so.

Further, since a countermeasure for reducing power consumption can be taken in an earlier design process, a synergistic effect can be brought about by using it together with a technology for reducing power consumption which can be applied in a later design process, and a great reduction in power consumption can be achieved. The effect that the effect of the conversion can be obtained is produced.

Further, since the power consumption at the register transfer level can be known, there is an effect that the circuit correction work can be performed efficiently.

According to a fifth aspect of the present invention, there is provided an integrated circuit power consumption detecting system according to any one of the first to fourth aspects, wherein the unnecessary power consumption detecting means is provided between all adjacent two nodes in the circuit. A signal propagation time series storage means for storing a sequence of times at which signal propagation occurs, and an order relationship between updating and reference of the value of each node from the signal propagation time series stored by the signal propagation time series storage means. And the sequence of the number of times signal propagation that is not necessarily required for the operation of the integrated circuit occurs and the time sequence based on the order relationship between the updating and reference of the value of each node obtained by the order relationship detecting unit. And unnecessary propagation detecting means for obtaining

According to a sixth aspect of the present invention, in the power consumption detecting system for an integrated circuit according to the fifth aspect of the present invention, the order relation detecting means determines the order relation between updating and reference of the value of each node as "attention." Operation 1 in which the register internally stores the processing result dependent on the data of the preceding register and updates the data ”and“ The processing result dependent on the data of the register of interest is referred to by the next-stage register and stored internally. And the unnecessary propagation detecting means uses the order relation obtained by the order relation detecting means to continuously execute the operation 1. By calculating the number of times, the number of times and the number of times the non-reference data latch operation, which is an unnecessary data transfer operation in which the register of interest stores data not referenced by the register of the next stage, is performed. It is configured to determine the sequence.

According to a seventh aspect of the present invention, in the power consumption detecting system for an integrated circuit according to the fifth aspect, the order relation detecting means sets the "attention" as the order relation between updating and reference of the value of each node. An operation 1 in which a register internally stores a processing result that depends on data in a preceding register and updates data ”and“ a processing in which a preceding register that transfers data to a register of interest is further dependent on data in a preceding register ” An operation 3 in which the result is internally stored and the data is updated is obtained, and the unnecessary propagation detecting means continuously executes the operation 1 using the order relation obtained by the order relation detecting means. Unnecessary data that stores the processing result depending on the data that has not been updated in the previous register Un-updated data latch operation that is a feeding operation is configured to determine a sequence number and time to be performed.

In the power consumption detection system for an integrated circuit according to the eighth aspect, in the configuration according to the fifth aspect, the order relation detecting means may select "attention" as the order relation between updating and reference of the value of each node. Operation 1 in which the register internally stores the processing result dependent on the data of the preceding register and updates the data ”and“ The processing result dependent on the data of the register of interest is referred to by the next-stage register and stored internally. 2 in which data is updated to a register of interest, and "operation 3 in which a preceding register for transferring data to a register of interest further stores therein a processing result dependent on the data of the preceding register and updates the data." Determining the number of times that the state where the operation 1 is continuously executed occurs using the order relation obtained by the order relation detecting means. More, the number and the time series of unnecessary data transfer operation to store the registers of interest is not referenced by the next register data therein is carried out, and,
The register of interest obtains the number of times an unnecessary data transfer operation in which a processing result dependent on data not updated in the register at the preceding stage is performed is performed and a series of times, and further, the unnecessary power consumption detecting means includes: Using the order relation obtained by the order relation detecting means, a data holding detecting means for obtaining the number of times the register of interest performs an operation of holding data and a time series, and a non-detection signal detected by the unnecessary propagation detecting means. A union of a period in which the reference data latch operation is performed, a period in which the unupdated data latch operation is performed, and a period in which the data holding operation detected by the data holding detection unit is performed is determined. Unnecessary operation period detection means for obtaining a series of times at which unnecessary register operations occur.

Therefore, in each of the configurations of claims 5 to 8, in addition to the effect of the configuration of claim 1, the designer can understand the period during which the clock operation can be stopped, and In this case, it is possible to grasp in detail the improvement points where power consumption can be reduced and the power consumption that can be reduced, and it is possible to take more effective measures for reducing power consumption.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an unnecessary circuit operation identifying means in one configuration example of a power consumption detection system for an integrated circuit according to the present invention.

FIG. 2 is a block diagram showing a schematic configuration of the entire system of FIG. 1;

FIG. 3 is a circuit diagram illustrating a configuration example of a register driven by a clock.

FIG. 4 is an explanatory diagram showing an example of a clock supplied to a register in FIG. 3 and timing waveforms of data input and data output.

FIG. 5 is an explanatory diagram showing an example of a clock supplied to a register in FIG. 3 and timing waveforms of data input and data output.

FIG. 6 is a circuit diagram showing an example of a circuit at a register transfer level.

FIG. 7 is an explanatory diagram showing an example of a data flow graph corresponding to FIG. 6;

FIG. 8 is an explanatory diagram showing an example of a data flow graph.

FIG. 9 is an explanatory diagram showing an example of extraction of a register transfer condition, a next-stage register reference condition, and a previous-stage register update condition.

FIG. 10 shows a register transfer condition, a next-stage register reference condition,
FIG. 9 is an explanatory diagram showing an example of extracting a preceding-stage register update condition.

FIG. 11 is an explanatory diagram showing an example of the result of calculating the number of times the condition is satisfied;

FIG. 12 is a circuit diagram showing an example of a circuit of a register transfer level with reduced power consumption.

FIG. 13 is a block diagram showing a configuration of a computer for realizing the present system.

FIG. 14 is a block diagram showing a configuration of a main part of another configuration example of the integrated circuit power consumption detection system according to the present invention.

FIG. 15 is an explanatory diagram showing a state of data transfer between registers.

FIG. 16 is an explanatory diagram showing a design flow of a general integrated circuit.

FIG. 17 is a block diagram illustrating a configuration example of a conventional power consumption prediction device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 System (power consumption detection system of integrated circuit) 2 Unnecessary circuit operation identification means 3 Condition extraction means 4 Transition number calculation means 5 Unnecessary circuit operation number calculation means 6 Load capacity calculation means 7 Power consumption calculation means 8 Result output means 21 Data flow Graph extraction means 22 Register transfer condition extraction means 23 Next stage register reference condition extraction means 24 Previous stage update condition extraction means 25 Clock supply frequency calculation means 26 Register transfer condition satisfaction frequency calculation means 27 Next stage register reference condition satisfaction frequency calculation means 28 Previous stage Register update condition satisfaction count calculation means 29 Data holding operation count calculation means 30 Non-reference data latch count calculation means 31 Unupdated data latch count calculation means 42 Unnecessary circuit operation identification means 60 Computer 61 CPU 62 ROM 63 RAM 64 HDD 65 FDD 66 CRT display (output unit) 67 Hard disk (data storage unit) 68 Floppy disk 71 Clock operation / data transfer time series storage means (signal propagation time series storage means) 72 Update / reference time series calculation means (order relation detection means) 73 data Holding operation time series calculation means (data holding detection means) 74 Non-reference data latch frequency / time series calculation means (unnecessary propagation detection means) 75 Unupdated data latch frequency / time series calculation means (unnecessary propagation detection means) 76 Unnecessary register operation Generation period detecting means (unnecessary operation period detecting means) CK, CLK Clock signal G1, G2 Control signal Ga, Gb, Gc, Ge, Gf, Gs Control circuit R1, R2 Register SEL selector a, b, c, d, e, f register

Claims (9)

[Claims] An integrated circuit power consumption detection system for determining the power consumption of an integrated circuit from the number of signal transitions of each element of an integrated circuit, a load capacitance, and an operating voltage of each signal. Identify the signal transitions necessary for the processing to be performed and the unnecessary signal transitions, detect the number of signal transitions unnecessary for the processing, and use the unnecessary signal transitions to calculate the power consumption due to unnecessary operation. A power consumption detection system comprising unnecessary power consumption detection means for obtaining unnecessary power consumption. 2. The method according to claim 1, wherein said unnecessary power consumption detecting means is true when a register of interest stores therein a processing result dependent on data of a register in a preceding stage from a control condition when data is transferred to the register. The number of times that the condition 1 is satisfied is obtained. From this number, the number of operations in which the register of interest, which is unnecessary for processing, retains its own data, is obtained. ,
The power consumption detection system according to claim 1, wherein power consumption consumed by an operation of retaining data is detected as the unnecessary power consumption. 3. The unnecessary power consumption detecting means becomes true when a target register internally stores a processing result dependent on data of a preceding register from a control condition when data is transferred to the register. The number of times that the condition 1 is satisfied is determined. The number of times that the condition 2 that is true when the next-stage register internally stores the processing result depending on the data of the register of interest is satisfied. By calculating the number of times the register internally stores data that is not referenced by the register at the next stage, of the power consumed by operating the register,
2. The power consumption detection system according to claim 1, wherein the unnecessary power consumption is detected by storing data that is not referred to in the next stage. 4. An unnecessary power consumption detecting means, based on a control condition when data is transferred to a register, becomes true when a register of interest stores therein a processing result dependent on data of a register in a preceding stage. The number of times that the condition 1 is satisfied is obtained, and the register of interest is obtained by obtaining the number of times that the condition 3 that is true when the preceding register further stores therein the processing result depending on the data of the previous register is true. The number of times the data in the register at the previous stage is updated is calculated, and the number of times that the register of interest stores internally the processing result dependent on the data that has not been updated by the register at the previous stage is calculated from the number of times. Of the power consumed by
2. The power consumption detection system according to claim 1, wherein the unnecessary power consumption is detected by storing data that has not been updated in a previous stage. 5. The signal propagation time series storage means for storing a series of times at which signal propagation occurs between all adjacent two nodes in a circuit, said unnecessary power consumption detection means; An order relation detecting means for obtaining an order relation between the update and reference of the value of each node from the time series of signal propagation stored by the means; and an update and reference of the value of each node obtained by the order relation detecting means. 5. The unnecessary propagation detecting means according to claim 1, further comprising: an unnecessary propagation detecting means for calculating the number of times of signal propagation that is not necessarily required for the operation of the integrated circuit and the sequence of time based on the order. Power consumption detection system. 6. The order relation detecting means, as the order relation between the update and reference of the value of each node, includes: "a register of interest stores therein a processing result dependent on data of a register at a preceding stage, and stores data therein. An update operation 1 ”and an“ operation 2 of updating the data by internally storing the result of processing that depends on the data of the register of interest with reference to the next register ”are obtained. However, by using the order relation obtained by the above-mentioned order relation detecting means to determine the number of times that the state in which the operation 1 is continuously executed occurs, the data of which the register of interest is not referred to by the next-stage register is internally stored. 6. The power consumption detection system according to claim 5, wherein the number of times the non-reference data latch operation, which is an unnecessary data transfer operation stored in the memory, and the time series are obtained. 7. The above-mentioned order relation detecting means, as the above-mentioned order relation between the updating and reference of the value of each node, includes: The order relationship between “operation 1 for updating” and “operation 3 for updating data by internally storing a processing result dependent on data of the register in the previous stage, in which the register in the previous stage for transferring data to the register of interest” is obtained. The unnecessary propagation detecting means obtains the number of times that the state in which the operation 1 is continuously performed occurs using the order relation obtained by the order relation detecting means, so that the register of interest is a register in the preceding stage. Determining the number of times an unupdated data latch operation, which is an unnecessary data transfer operation that internally stores a processing result dependent on data that has not been updated, and a time series. The power consumption detection system according to claim 5, wherein: 8. The above-mentioned order relation detecting means determines, as the order relation between the updating and reference of the value of each node, that a register of interest internally stores a processing result dependent on data of a register at a preceding stage and stores data therein. "Operation 1 for updating", "Operation 2 for updating the data by internally referencing the processing result dependent on the data of the register of interest" and "Operation 2 for updating the data to the register of interest" The register is
And an operation 3 for internally storing a processing result dependent on the data of the register in the preceding stage and updating the data, and the unnecessary propagation detecting means determines the order relation obtained by the order relation detecting means. The number of times an unnecessary data transfer operation in which a register of interest stores therein data that is not referred to by a register at the next stage is performed by calculating the number of times that a state in which the operation 1 is continuously executed is used. And a sequence of times and times at which unnecessary data transfer operations in which a register of interest depends on data that has not been updated in the register at the preceding stage and in which unnecessary data transfer operations are performed are obtained. Using the order relation obtained by the order relation detecting means, the power consumption detecting means performs the number of times and the time at which the register of interest performs an operation of retaining data. Data holding detecting means for determining a sequence, a period during which a non-reference data latch operation detected by the unnecessary propagation detecting means is performed, a period during which an unupdated data latch operation is performed, and a time period detected by the data holding detecting means. Find the union with the period during which the data holding operation is performed,
6. The power consumption detection system according to claim 5, further comprising an unnecessary operation period detecting unit for obtaining a series of times at which the unnecessary register operation continuously occurs. 9. A recording medium storing a computer program for calculating power consumption of an integrated circuit from the number of signal transitions of each element of an integrated circuit, a load capacitance, and an operating voltage of each signal, wherein: Identify signal transitions required for processing to be performed by the integrated circuit and unnecessary signal transitions, detect the number of signal transitions unnecessary for processing, and use the number of unnecessary signal transitions to determine the power consumption due to unnecessary operation. A recording medium on which a computer program for determining unnecessary power consumption is recorded.