JPH10150356A - Cmos semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an integrated circuit that is possible to realize both low power consumption and a high speed operation by eliminating a through-current while keeping high speed signal propagation through impedance matching. SOLUTION: In an integrated circuit that terminates a signal line 4 with a resistor, an absolute value of a threshold voltage of a PMOSFET 6 and an NMOSFET 7 consisting of a logic gate Inv2 is made nearly to a half or over of an intermediate voltage between a 1st power supply voltage Vdd and a 2nd power supply voltage Vss so as to eliminate inconvenience that both the PMOSFET 6 and the NMOSFET 7 consisting of the logic gate Inv2 are put ON to prevent a through-current from flowing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS semiconductor integrated circuit, and more particularly, to a CMOS semiconductor integrated circuit using CMOS technology, which is suitable for use in a CMOS semiconductor integrated circuit that handles high-speed signals.

[0002]

2. Description of the Related Art As the speed of a signal handled by a semiconductor integrated circuit increases, the propagation delay time of the signal may increase due to the reflection of the signal due to the impedance mismatch between the transistor output, wiring, and transistor input. It is becoming a problem. For example, it is assumed that the ratio between the wiring and the transistor output impedance is 20 (usually, in a CMOS logic gate, the input impedance is much larger than the output impedance, so that the input side may be considered as total reflection).

In this case, the signal is not stable unless reflected and reflected 20 times (exactly 19 and a half times) because of reflection.
The signal propagation delay time is 39 times as long as the time when the first signal waveform arrives. Therefore, in a digital integrated circuit, it is preferable to reduce the signal propagation delay time by performing input / output impedance matching as performed in an analog high-frequency circuit.

As a conventional technique for impedance matching as described above, Japanese Patent Application Laid-Open No. H06-163630 discloses an output circuit section composed of a plurality of transistors, and the number of transistors connected by wire bonding in accordance with the impedance of an external circuit. Is selected, and the gate width of the transistor is adjusted so that the impedance of the output circuit unit is matched with the external circuit to reduce the signal propagation delay.

More specifically, for example, three bonding wires are connected to a lead frame, and impedance matching is performed using the gate width of two transistors, or one bonding wire is connected to the lead frame. ,
Impedance matching is performed using the gate width of one transistor.

[0006]

However, an I / O circuit for exchanging signals with an external circuit originally has a lower signal speed than an internal circuit, and is not suitable from the viewpoint of improving the circuit operation of the entire integrated circuit. Had little contribution.

If this technique is incorporated into an internal circuit, the gate width of the transistor is changed in accordance with the impedance of the wiring. However, the impedance of the wiring is usually several tens of Ω, and the unit gate width of the transistor (1 μm).
The impedance per m) is several kΩ.

Accordingly, Japanese Patent Application Laid-Open No. 06-16363 discloses
When trying to match the impedance using the method disclosed in Japanese Patent Publication No. 0, there is a problem that the gate width of the transistor becomes too large, several tens to several hundreds of μm. Also, there is a problem that the input impedance of a large logic gate cannot be matched by using this method alone.

Therefore, it is usually necessary to terminate the signal line using a resistor to match the input and output impedances. However, when a configuration is used in which impedance matching is performed using a resistor, the potential at the input portion of the transistor that receives a signal becomes an intermediate potential that is separated from both the positive power supply and the negative power supply. For this reason, both the PMOSFET and the NMOSFET of the CMOS circuit may be turned on, and when both are turned on, there is a problem that a through current is generated.

SUMMARY OF THE INVENTION In view of the above problems, the present invention can provide a CMOS semiconductor integrated circuit that achieves both low power consumption and high speed operation by eliminating through current while enabling higher speed signal propagation by performing impedance matching. The purpose is to be.

[0011]

SUMMARY OF THE INVENTION A CMOS semiconductor integrated circuit according to the present invention is an integrated circuit for performing impedance matching by terminating a signal line with a resistor.
The absolute value of the threshold voltage of the MOSFET and the NMOSFET is set to be substantially half or more of the intermediate potential between the first power supply voltage and the second power supply voltage.

Another feature of the present invention is that
The absolute value of the threshold voltage of each of the PMOSFET and the NMOSFET is set to be equal to or more than a quarter of the first power supply voltage and the second power supply voltage.

According to another feature of the present invention, in an integrated circuit for performing impedance matching by terminating a signal line with a resistor, a first resistor is provided as a resistor for terminating the signal line. And the second resistor are connected in series to form two terminating resistor circuits, and one of the two terminating resistor circuits is connected to the signal line and the first power supply voltage. And the other terminal resistor circuit is connected between the signal line and the second power supply voltage, and the gate terminal is connected in parallel with the second resistor in the one terminal resistor circuit. A PMOSFET connected to the output terminal of the input logic gate is connected, and an NMOSFET whose gate terminal is connected to the output terminal of the input logic gate is connected in parallel with the second resistor in the other terminating resistor circuit. And, wherein the one and the first resistor and the resistance value of the second resistor constituting the other terminal resistor circuit, the resistance value of the first resistor and R _1, a second resistor of the resistor the value is taken as _{R 2, {R 1 (R} 1 + R 2) /
The value (2R ₁ + R ₂ ) 値 is set to be equal to the impedance of the signal line.

Another feature of the present invention is that the one terminating resistor circuit is connected to a positive terminating power supply voltage higher than the first power supply voltage, and the other terminating resistor circuit is connected to the other terminating power supply voltage. The resistor circuit is connected to a negative terminal power supply voltage lower than the second power supply voltage.

Another feature of the present invention is that in an integrated circuit for performing impedance matching by terminating a signal line with a resistor, a PMOSF constituting a logic gate is provided.
Connecting the substrate of the PMOSFET among the ET and the NMOSFET to a positive terminal power supply voltage higher than the first power supply voltage of the internal circuit via a resistor, and connecting to a signal line via a capacitor; The NMOSFET
Is connected to a negative terminal power supply voltage lower than the second power supply voltage of the internal circuit via a resistor, and to a signal line via a capacitor.

Since the present invention comprises the above technical means, the CM
PMOSFET and NM constituting OS semiconductor integrated circuit
Both of the OSFETs will not turn on, and the PM
It is possible to perform impedance matching that reliably prevents a through current generated when both the OSFET and the NMOSFET are turned on.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of a CMOS semiconductor integrated circuit according to the present invention will be described with reference to the drawings. FIG.
1 shows a circuit diagram of a CMOS semiconductor integrated circuit of the present invention.
In the figure, as the logic gate, an inverter In of a CMOS configuration composed of a PMOSFET and an NMOSFET is used.
Although v1 and v2 are shown as an example, of course, NAND,
Other logic gates such as NOR may be used. For ease of understanding, the description will be made assuming that the output impedance of the logic gate is 0Ω and the input impedance is ∞Ω (infinity).

In FIG. 1, reference numeral 1 denotes an inverter I on the driving side.
The nv1 PMOSFET 2 and the drive-side inverter In
v1 NMOSFET. Reference numeral 3 denotes a resistor for performing impedance matching of the output of the drive-side inverter Inv 1, and its value is equal to the characteristic impedance Z ₀ of the wiring 4.

Reference numeral 5 denotes a resistor for matching the input impedance of the driven-side inverter Inv 2, the value of which is also equal to the characteristic impedance Z ₀ of the wiring 4. Reference numeral 6 denotes a PMOSFET of the driven inverter Inv2, and reference numeral 7 denotes an NMOSFET of the driven inverter Inv2.

The aforementioned PMOSFETs 1 and 6, NMOS
The absolute values of the threshold voltages of the FETs 2 and 7 are set to be larger than a quarter of the value of the power supply voltage (Vdd-Vss). It is preferable in terms of circuit operation that the intermediate potential Vctt connecting the resistor 5 terminating the input of the driven-side inverter Inv1 is set to the center value (Vdd + Vss) / 2 of both power supplies.

Next, the operation of the circuit of FIG. 1 will be described. The potential Vout of the output terminal of the drive-side inverter Inv1 is
The maximum value is the value of the positive power supply Vdd. At this time, the potential Vin of the input terminal of the inverter Inv2 on the driven side is V
The median value of out and Vctt, that is, a size of about ／ from the bottom of the power supply voltage width.

In a normal circuit, the threshold voltage of the transistor is 1/10 to 1/5 of the power supply voltage width, so that PM
The OSFET 6 is not turned off, and a through current flows. However, in the circuit of this embodiment, the PMOSFET 6
The threshold voltage of both the NMOSFET 7 and the power supply voltage (Vdd)
−Vss) or more, so that PMOSFET 6
It becomes FF. Therefore, the driven inverter Inv2
, No through current flows, so that low power consumption can be achieved.

On the other hand, when the potential Vout of the output terminal of the drive-side inverter Inv1 is the negative power supply Vss, NM
Since the OSFET 7 is turned off, no through current flows through the driven inverter Inv2 in this case as well. As a result, in this case as well, the flow of through current is suppressed, and power consumption can be reduced.

[0024] In the above description, the input of the driven-side inverter Inv2 has been terminated with the resistor 5 to the intermediate potential Vctt, as shown in FIG. 2, 2 with a value of 2 · Z ₀ The two resistors 8 and 9 may terminate both the positive power supply voltage Vdd and the negative power supply voltage Vss. Also in this case, the circuit operation is exactly the same, and in this case, the resistor 8,
Since there is no need to create an intermediate potential Vctt for connecting the circuit 9, there is an advantage that the circuit configuration is simplified.

By the way, in an actual device, the input impedance is sufficiently large (10 ⁴ times or more) with respect to the characteristic impedance Z _{0 of the} wiring, so that there is no problem even if the input impedance is considered to be infinite. However, since the output impedance is not always “0Ω”, it is necessary to consider this when performing impedance matching.

Hereinafter, a method of performing impedance matching of the output of the inverter Inv1 on the driving side will be described with reference to FIG. First, when impedance matching is not performed, or when the output impedance R _OUT of the logic gate 10 (FIG.
, The resistance is equal to the characteristic impedance Z _{0 of the} wiring 4, that is, the logic gate 10
When the output impedance of the logic gate 10 is Z ₀ , the output terminal of the logic gate 10 is directly connected to the wiring 4 as shown in FIG.

Next, when the output impedance R _OUT of the logic gate 10 is smaller than the characteristic impedance Z _{0 of the} wiring 4, as shown in FIG. Inserts the resistor 3 of R in series, and (R
_OUT + R) = as a Z _0, the impedance matching.

When the output impedance R _OUT of the logic gate 10 is larger than the characteristic impedance Z ₀ of the wiring 4, the output terminal is directly connected to the wiring 4 as shown in FIG. The output terminal is connected to the intermediate potential Vctt through a resistor 11 having a value of R, and R _OUT
• Impedance matching is performed so that R / (R _OUT + R) = Z ₀ .

In this case, as shown in FIG. 3D, two resistors 12 and 13 (each having a resistance of 2
Even if the output terminals are connected to the positive power supply voltage Vdd and the negative power supply voltage Vss via R), the same effect can be obtained.

FIG. 4 is a circuit diagram showing another configuration of the CMOS semiconductor integrated circuit of the present invention. Note that the configuration of the inverter Inv1 on the driving side is the same as that of the circuit shown in FIG. 1 and is omitted, and only the driven side is shown. In the figure, although an inverter is used as an example of a logic gate, NAND, N
Other logic gates such as OR may be used.

The first resistor 15 and the second resistor 14 are arranged between the signal line and the positive terminal power supply voltage Vdd2 (Vdd2> Vdd) higher than the positive power supply voltage (Vdd) of the internal circuit. The resistor 17 and the fourth resistor 16 are disposed between the signal line and the negative terminal power supply voltage Vss2 (Vss2 <Vss) lower than the negative power supply voltage (Vss) of the internal circuit.

In parallel with the second resistor 14, a PM whose gate terminal is connected to the output terminal of the input logic gate is provided.
OSFET 18 is connected. Further, an NMOSFET 19 whose gate terminal is connected to the output terminal of the input logic gate is connected in parallel with the fourth resistor 16.

The resistance value of these terminating resistors 14 and 16 is R ₂ . The resistance value of the first resistor 15 and third resistor 17 is R _1. The first resistance value R ₁ and the second resistance value R ₂ are R ₁ (R ₁ + R ₂ ) / (2 · R ₁ +
R ₂ ) = Z ₀ . The above-mentioned terminal power supply voltages Vdd2 and Vss2 can be easily generated by a charge pump circuit (not shown).

Next, the operation of the circuit shown in FIG. 4 will be described. When the output on the driving side is “H”, the output on the driven side becomes “L”. That is, since the output of the inverter Inv2 composed of the PMOSFET 6 and the NMOSFET 7 becomes “L”,
MOSFET18 is ON, NMOSFET19 is OFF
Becomes

Therefore, since the second resistor 14 is short-circuited, the resistance value of the input terminal of the inverter Inv2 to the positive terminal power supply voltage Vdd2 becomes smaller, and the potential of the input terminal rises. , PMOSFET 6 is reliably turned off. Thereby, also in the case of the circuit of FIG. 4, the through current can be reliably suppressed, and both high-speed operation and low power consumption can be achieved. The same operation is performed when the output on the driving side is "L". In this case, the NMOSFET 7 is turned off, the through current can be suppressed, and both high speed and low power consumption can be achieved.

In the present embodiment, since the potential of the positive terminal power supply voltage Vdd2 is higher than the first power supply voltage Vdd, the potential of the input terminal can be raised by that amount, and the PMOSFET 6 is turned off further. It can be done reliably.

Further, since the potential of the negative terminal power supply voltage Vss2 is lower than the second power supply voltage Vss, the potential of the input terminal can be reduced by that amount, and the NMOSFET
7 can be more reliably turned off.

FIG. 5 is a circuit diagram showing still another configuration of the integrated circuit of the present invention. Since the configuration on the driving side is the same as that in FIG. 1, the description is omitted, and FIG. 5 shows only the driven side. Although an inverter is used as an example of a logic gate in FIG. 5, other logic gates such as a NAND and a NOR may be used.

In this embodiment, the PMOSFET 6
(Body) is connected to a positive terminal power supply voltage Vdd2 (Vdd2> Vdd) higher than the positive power supply voltage (Vdd) of the internal circuit via a resistor 20 having a resistance value R, and via a capacitor 21. Connected to signal line.

The substrate (body) of the NMOSFET 7
Are connected to the negative terminal power supply voltage Vss2 (Vss) lower than the negative power supply voltage (Vss) of the internal circuit through the resistor 22 having the resistance value R.
2 <Vss) and the capacitor 2
3 to a signal line.

Considering the operation of the circuit of FIG. 5 configured as described above, when the signal is not changed, the PMOSF
The potential Vpb of the substrate (body) of ET6 is the positive terminal power supply voltage Vdd2.

The substrate (body) of the NMOSFET 7
Is the negative terminal power supply voltage Vss2,
Threshold voltage Vtp of PMOSFET 6, NMOSFE
Each of the threshold voltages Vtn of T7 is deep (absolute value is large). Therefore, PMOSFET 6, NM
One of the OSFETs 7 is turned off, so that a through current can be suppressed and low power consumption can be realized.

Next, consider the case where a rising signal is input from the driving inverter. The potential Vin at that time,
FIG. 6 shows changes in Vpb, Vnb, Vtp, Vtn and the potential Vint of the output terminal. In FIG. 6, the values in the case where the resistors 20 and 22 and the capacitors 21 and 23 are not provided are indicated by dotted lines. The potential Vpb, NM of the substrate (body) of the PMOSFET 6 in accordance with the rise of the signal.
The potential Vnb of the substrate (body) of the OSFET 7 rises,
As a result, the threshold voltage Vtp, N
The threshold voltage Vtn of the MOSFET 7 decreases (PM
The absolute value of the threshold voltage Vtp of the OSFET 6 increases).

Therefore, the PMOSFET 6 is quickly turned off.
, And the NMOSFET 7 is turned on earlier, so that the fall of the output signal Vint is earlier, the signal propagation delay time is shorter, and high-speed operation is possible, as shown in FIG.

In the above, the input of the driven-side inverter is terminated to the potential Vctt by the resistor 5, but as shown in FIG. 7, the resistor 8 having the resistance value of 2 · Z ₀ is connected to Vdd or Vdd2. And the resistor 9 also having a resistance value of 2 · Z ₀ may be terminated to Vss or Vss2. Even in this case, the circuit operation is exactly the same, and there is no need to create the intermediate potential Vctt, and the circuit configuration is simplified.

[0046]

【Example】

(First Embodiment) Next, a first embodiment will be described with reference to FIG. 1 is the PMOSFE of the drive side inverter
T and 2 are NMOSFETs of the drive side inverter.
Reference numeral 3 denotes a resistor for performing impedance matching of the output of the inverter on the driving side, and its resistance value is set to be equal to the characteristic impedance Z ₀ of the wiring 4 = 30Ω. Reference numeral 5 denotes a resistor for matching the impedance of the input of the inverter on the driven side, and its value is set to be equal to the characteristic impedance of the wiring 4 of 30Ω.

6 and 7 are the PMs constituting the CMOS.
OSFET and NMOSFET, their PMO
The CMOS on the driven side is constituted by the CMOS comprising the SFET 6 and the NMOSFET 7.

The above-mentioned PMOSFETs 1 and 6, NMOS
The absolute values of the threshold voltages of the FETs 2 and 7 are 1.5% which is 30% of the value of the power supply voltage (Vdd−Vss) = 5V.
V. The potential Vctt for connecting the resistor 5 terminating the input of the driven-side inverter was set to the center value (Vdd + Vss) / 2 of both power supplies = 2.5V.

The potential Vo of the output terminal of the inverter on the driving side
When ut is Vdd, the potential Vin of the input terminal of the driven-side inverter is ３ = 75% from the bottom of the power supply voltage width. On the other hand, in this embodiment, the PMOSFET is also NM
Since the absolute value of the threshold voltage of the OSFET is 1.5 V, which is 30% of the power supply voltage, the PMOSFET is turned off.
As a result, the through current was suppressed and the power consumption was reduced. Also, the potential Vout below the inverter on the driving side
Similarly, when Vss was Vss, the NMOSFET was turned off, the through current was suppressed, and low power consumption was achieved.

(Second Embodiment) Next, a second embodiment will be described with reference to FIG. The configuration of the driving side circuit is shown in FIG.
The description is omitted because it is the same as that of FIG. Connect the terminating resistors 14 and 15 to the positive power supply voltage (Vd
d = 3.3V), the positive terminal power supply voltage Vdd2 = 4.
3V, and the terminating resistors 16 and 17 are arranged between the signal line and the negative terminal power supply voltage Vss2 = −1.0 V lower than the negative power supply voltage (Vss = 0 V) of the internal circuit. Here, the characteristic impedance Z ₀ of the wiring is 60Ω.

In parallel with the terminating resistor 14, the PMOSFET 1 whose gate terminal is connected to the output terminal of the input logic gate
Connect 8 Further, in parallel with the terminating resistor 16, the gate terminal is an NMOSF connected to the output terminal of the input logic gate.
ET19 is connected. And the terminating resistors 14, 1
The value of 6 was R ₂ = 160Ω, and the values of the terminating resistors 15 and 17 were R ₁ = 80Ω.

These resistors R₁, And R_TwoIs R
₁(R₁+ R_Two) / (2 · R₁+ R _Two) = Z₀(= 60
Ω). Note that the terminal power supply voltage Vd
The voltage of d2 = 4.3V and Vss2 = -0.1V
It is generated by a dipump circuit (not shown).

When the output on the driving side is "H", the PMOSF
ET18 is ON, NMOSFET 19 is OFF,
The PMOSFET 6 is turned off, the through power can be suppressed, and both high speed and low power consumption can be achieved. Also, when the output on the driving side is “L”, the same operation is performed.
T7 is turned off, the through current can be suppressed, and both high speed and low power consumption can be achieved.

(Third Embodiment) Next, a third embodiment of the present invention will be described with reference to FIG. The configuration on the driving side is the same as that in FIG. 1 and thus is omitted, and only the driven side is shown. PM
The substrate (body) of the OSFET 6 is connected via the resistor 20 to the positive terminal power supply voltage Vdd2 = 5.0 V higher than the positive power supply voltage (Vdd = 3.0 V) of the internal circuit, and to the signal line via the capacitor 21. , NMOSFET 7 is connected to a negative power supply voltage (V
ss = 0 V) lower than the negative terminal power supply voltage Vss2 = −2.
0 V was connected to the signal line via the capacitor 23.

When the signal has not changed, the PMOSFE
The potential Vpb of the substrate (body) of T6 is Vdd2, NMO
The potential Vnb of the substrate (body) of the SFET 7 is Vss2. Therefore, the PMOSFET 6, NMOSF
Since the absolute value of the threshold voltage of ET7 is high,
Either PMOSFET 6 or NMOSFET 7 is OF
F, the through current was suppressed, and low power consumption was realized.

FIG. 6 shows the potentials Vin, Vpb and V of the input terminals when a rising signal is input from the inverter on the driving side.
5 shows changes in nb, Vtp, Vtn and the potential Vint of the output terminal. The values without the resistors 20, 22 and the capacitors 21, 23 are shown by dotted lines.

In accordance with the rise of the signal shown in FIG. 6A, the PMOSFE as shown in FIGS.
T6 substrate (body) potential Vpb, NMOSFET 7
The potential Vnb of the substrate (body) increases. As a result, the threshold voltage Vtp of the PMOSFET 6 and the threshold voltage Vtn of the NMOSFET 7 decrease as shown in (d) and (e) (because the threshold voltage Vtp of the PMOSFET 6 is a negative value, the "absolute value Is even larger).

Therefore, the PMOSFET 6 is quickly turned off.
As the signal becomes F, the NMOSFET 7 is turned on earlier, so that the output signal Vint falls earlier as shown in FIG. As a result, the signal propagation delay time was shortened, and high-speed operation was achieved.

[0059]

As described above, according to the present invention, in a circuit for shortening a signal propagation delay time by impedance matching, a PMOSFE forming a logic gate is provided.
The absolute values of the threshold voltages of T and NMOSFET
Since the power supply voltage is set to approximately half or more of the intermediate potential between the power supply voltage and the second power supply voltage, it is possible to prevent both the PMOSFET and the NMOSFET constituting the CMOS circuit from turning on. Thereby, the PMOSFET and the NMOSF
When both of the ETs are turned on, it is possible to perform impedance matching in which the inconvenience that a through current flows is reliably prevented, and both low power consumption and high-speed operability can be reliably realized.

According to another feature of the present invention, two terminating resistor circuits are formed by connecting the first resistor and the second resistor in series, and one terminating resistor circuit is connected to Connected between the signal line and the first power supply voltage, the other terminating resistor circuit is connected between the signal line and the second power supply voltage, and the first terminal is connected to the first power supply voltage according to the polarity of the input signal. Since one of the resistors is short-circuited, it is possible to prevent both the PMOSFET and the NMOSFET from being simultaneously turned on, thereby reducing power consumption and realizing high-speed operation.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an example of a CMOS semiconductor integrated circuit of the present invention.

FIG. 2 is a circuit diagram showing another configuration example of the CMOS semiconductor integrated circuit of the present invention.

FIG. 3 is a circuit diagram illustrating a termination method of a driving-side logic gate.

FIG. 4 is a circuit diagram of another configuration of the CMOS semiconductor integrated circuit of the present invention.

FIG. 5 is a circuit diagram of still another configuration of the CMOS semiconductor integrated circuit of the present invention.

FIG. 6 is a diagram for explaining the operation of the circuit of FIG. 6;

FIG. 7 is a circuit diagram of still another configuration of the CMOS semiconductor integrated circuit of the present invention.

[Explanation of symbols]

1,6 PMOSFET 2,7 NMOSFET 3,5 Resistor 21,23 Capacitor 4 Wiring Vdd Positive power supply voltage (first power supply voltage) Vss Negative power supply voltage (second power supply voltage) Z ₀ Characteristic impedance of signal line Vcttt Middle potential

Claims (5)

[Claims] 1. An integrated circuit for performing impedance matching by terminating a signal line with a resistor, comprising: a PMOSFET and an NMOS FE forming a logic gate.
A CMOS semiconductor integrated circuit, wherein an absolute value of a threshold voltage of T is set to be approximately half or more of an intermediate potential between a first power supply voltage and a second power supply voltage. 2. The PMOSFET and the NMOSFET.
The absolute value of the threshold voltage of the first power supply voltage and the second power supply voltage is set to one-fourth or more of the absolute value of the threshold voltage.
3. The CMOS semiconductor integrated circuit according to 1. 3. An integrated circuit for performing impedance matching by terminating a signal line with a resistor, wherein a first resistor and a second resistor are connected in series as a resistor for terminating the signal line. And one of the two terminating resistor circuits is connected between the signal line and the first power supply voltage, and the other terminating resistor circuit is connected to the second terminating resistor circuit. A PMOSFET having a circuit connected between the signal line and a second power supply voltage and having a gate terminal connected to an output terminal of an input logic gate in parallel with a second resistor in the one termination resistor circuit; And an NM whose gate terminal is connected to the output terminal of the input logic gate in parallel with the second resistor in the other terminating resistor circuit.
Connect OSFET, the one and the first resistor and the resistance value of the second resistor constituting the other terminal resistor circuit, the resistance value of the first resistor and R _1, a second resistor Wherein the value of {R ₁ (R ₁ + R ₂ ) / (2R ₁ + R ₂ )} is set to be equal to the impedance of the signal line when the resistance of the device is R _2. Semiconductor integrated circuit. 4. The method according to claim 1, wherein the one terminating resistor circuit is connected to the first
And the other end of the resistor circuit is connected to a negative terminal power supply voltage lower than the second power supply voltage. Item 4. A CMOS semiconductor integrated circuit according to item 3. 5. An integrated circuit for performing impedance matching by terminating a signal line with a resistor, wherein a PMOSFET and an NMOS FE constituting a logic gate are provided.
T, connecting the substrate of the PMOSFET to a positive terminal power supply voltage higher than a first power supply voltage of the internal circuit via a resistor, and connecting the substrate to a signal line via a capacitor; Wherein the substrate is connected to a negative terminal power supply voltage, which is lower than the second power supply voltage of the internal circuit, via a resistor, and to a signal line via a capacitor.