JPH10150191A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an element process technique of forming a mask for ion- implantation use in a self-alignment and to provide a method of manufacturing a new vertical power device. SOLUTION: N<+> source regions 60a and 60b formed using a mask for trench processing use have the relation of a self-alignment with cap oxide films 90a and 90b on the upper parts of a trench and the cap oxide films on the upper parts of the trench have the relation of a self-alignment with the end parts of sidewalls 120a and 120b, whereby the positions of the regions 60a and 60b and the positions of the end parts of the sidewalls 120a and 120b both result in being decided on the bias of the end parts of step parts on the upper parts of the trench. Thereby, the sidewalls 120a and 120b are respectively sure to be positioned on the regions of the regions 60a and 60b. Accordingly, it becomes possible to form a mask for implantation use in a self-alignment.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a MOSFET having a trench gate structure.
(UMOS) and IGBT (Insulated Gat)
The present invention relates to a method for manufacturing a vertical insulated gate semiconductor device, such as eBicolorTransistor.

[0002]

[Background Art]

(1) A UMOSFET having a trench gate has attracted attention as a next-generation power MOSFET because its on-resistance can be reduced more easily than a conventional planar power MOSFET.

In the UMOSFET, it is important to reduce the on-resistance, and one of the techniques for reducing the on-resistance is to "make a planar pattern of a source (n ⁺ ) region into a ladder shape" ( For example, JP-A-7-2235
672).

In Japanese Patent Application Laid-Open No. Hei 7-2235672, first, a ladder-shaped source region is formed, and thereafter, the impurity diffusion mask used for forming the source is removed, and a new mask for trench processing is formed by photolithography. Then, the trench (groove) is processed.

(2) On the other hand, in order to improve the breakdown strength of the power MOSFET, it is necessary to increase the impurity concentration in the surface portion of the P-type body layer. Hereinafter, this will be described.

FIG. 23A shows a vertical power MOSFET.
2 shows a configuration example of (UMOSFET). Multiple MOSFE
The inductance load L is driven by T500a to 500n, and one MOSFET is
N ⁺ substrate 400, N ^- epitaxial layer 402, body P
Layer 404, source layers (N ⁺ ) 406a and 406b, gate insulating film 410, gate electrode 408, source electrode 412
a, 412b.

In the figure, reference numerals Q1 and Q2 are parasitic NPN transistors, reference numerals D1 and D2 are parasitic diodes, and reference numeral R is a parasitic resistance (including a body contact resistance) of a body P layer. Reference number 42
0 is a power supply.

FIG. 23B shows an equivalent circuit of the device shown in FIG.

A parasitic diode D1 and a resistor R are connected in series between a source (S) and a drain (D) of the MOSFET (M), and a parasitic NPN transistor Q1 is connected in parallel with a series path of D1 and R. Are interposed.

As shown in FIG. 23A, when the MOS transistor (M) changes from on to off, the breakdown current IB1 is reduced by the diode D1 (D2) due to the back electromotive force of the inductance load (L). ) And the resistor R1
Flow through (R2). At this time, the resistance R1 (R2)
When the voltage drop generated at both ends of the parasitic bipolar transistor Q1 (Q2) exceeds the base-emitter voltage (V _BE ) of the parasitic bipolar transistor Q1 (Q2), the parasitic bipolar transistor Q1 (Q2) turns on and an excessive breakdown current IB2 causes the transistor Q1 ( The flow concentrates on Q2), and in most cases, the junction is destroyed or the silicon or wiring is melted, and the element is destroyed.

In particular, when a power MOSFET or the like is used for controlling a vehicle, the load on the vehicle is mostly constituted by an inductance load such as a motor or a solenoid valve. Therefore, it is extremely important to avoid avalanche breakdown caused by inductance back electromotive force. It is. As described above, avalanche breakdown is a phenomenon that leads to breakdown due to the operation of a parasitic bipolar transistor existing in a power MOSFET structure, and it is necessary to suppress the operation of the parasitic bipolar transistor in order to achieve high breakdown strength.

For this purpose, the resistance value of the resistor R1 (R2) in FIGS. 23A and 23B is reduced, and the voltage drop in the resistor R1 (R2) when the breakdown current IB1 flows causes parasitic resistance. It must be lower than the base-emitter voltage (V _BE ) of the bipolar transistor Q1 (Q2). Therefore, it is important to reduce the resistance by increasing the concentration of P-type impurities on the surface of body P layer 404.

In the conventional method for manufacturing a MOSFET,
High concentration on the surface of this P-type body region (formation of P ⁺ layer)
Is performed by forming a mask using a photolithography technique and introducing impurities into the surface of the P-type body region by an ion implantation method.

[0014]

As described above, since the step of increasing the impurity concentration on the surface of the body P layer is performed using the photolithography technique, it is necessary to allow for a margin (alignment) for alignment with the trench gate. Which limits the reduction of the source area.

Further, a ladder-like source region and a trench (groove)
This also hinders further miniaturization of the source region, since it is necessary to consider the positioning error of the source region.

The present invention has been made in view of such problems, and one of its objects is to provide a novel element process technology for enabling further miniaturization of devices. Another object is to promote the miniaturization of the device by making the manufacturing process of the vertical power device self-aligned, and to further reduce the on-resistance of the transistor.

[0017]

[Means for Solving the Problems]

(1) In one method of manufacturing a semiconductor device according to the present invention, a sidewall is formed in contact with a side wall of a step portion on an upper portion of a trench, thereby forming a first conductive layer formed using a mask for processing the trench. A step of covering at least a part of the mold region; and a step of introducing a second conductivity type impurity using the sidewall as a mask.

The first conductivity type region formed using the trench processing mask and the trench (and the step on the trench) are in a self-aligned relationship. Also, the step on the trench and the end of the sidewall are in a self-aligned relationship. Therefore, both the position of the region of the first conductivity type and the position of the end of the sidewall are determined based on the trench (the end of the step on the trench). Therefore, the side wall is always located on the region of the first conductivity type. Therefore, it is possible to form a mask for ion implantation in a self-aligned manner without using photolithography technology.

Therefore, the process can be simplified, and the device can be miniaturized because there is no need to consider the alignment margin.

(2) When the above-described element processes are used, the vertical power device manufacturing process can be self-aligned to promote the miniaturization of the device and to further reduce the on-resistance of the transistor. This is another invention according to the present application, and its contents are as follows. In the following invention, the “cap insulating layer”
Corresponds to the above-mentioned “step portion above the trench”.

That is, a second semiconductor layer of the second conductivity type is formed on the first semiconductor layer of the first conductivity type, and the first semiconductor layer having a ladder-like planar pattern is formed on a surface portion of the second semiconductor layer. A conductive impurity region is formed, a groove penetrating a part of the second semiconductor layer and reaching the first semiconductor layer is formed, and a gate electrode material is formed inside the groove via a gate insulating film. The surface of the gate electrode material is filled with a cap insulating layer, and the surface of the impurity region of the first conductivity type having the ladder-like planar pattern and the second surface of the second conductivity type are filled.
A method of manufacturing a semiconductor device, wherein a common electrode is connected to the surface of the semiconductor layer of the second type, and the surface of the second semiconductor layer of the second conductivity type to which the electrode is connected has a high impurity concentration; Forming a first portion forming a first conductivity type impurity region having the ladder-like planar pattern along the groove; and forming the first portion of the ladder-like planar pattern in a direction intersecting with the first portion. Forming a second portion having a higher impurity concentration than the first portion, forming a first conductivity type impurity region having: and covering a surface of the gate electrode material filled in the trench Forming a sidewall with reference to an end of the cap insulating layer, and covering at least a part of the surface of the first portion with the sidewall; and masking the cap insulating layer and the sidewall with a mask. And introducing a second conductivity type impurity into the surface of the second portion and the second semiconductor layer to increase the impurity concentration on the surface of the second semiconductor layer. It is assumed that.

The present invention is a method of manufacturing a semiconductor device which realizes high concentration of the surface of a body P layer by self-alignment.

That is, a low impurity concentration first portion in a ladder-shaped first conductivity type impurity region (a source region in the case of a power MOSFET and an emitter region in the case of an IGBT) is formed along a groove (trench). In the direction intersecting (preferably perpendicular to) the first portion, the second
Is formed, the first portion having a low impurity concentration is covered with a sidewall with reference to the trench end (the end of the cap insulating film), and impurities of the second conductivity type are introduced into the entire surface by ion implantation. . A series of steps are all self-aligned.

Since the impurity concentration on the surface of the body P layer is increased and the resistance is reduced, the breakdown strength of the element is not reduced.

On the other hand, since the second portion of the ladder-shaped impurity region of the first conductivity type has a high impurity concentration, the first portion of the impurity region of the second conductivity type is implanted by ion implantation.
There is no problem because the conductivity type is maintained and an impurity concentration sufficient for practical use can be ensured.

Since the first portion of the ladder-shaped impurity region has a low impurity concentration, excessive diffusion due to the heat treatment is prevented, so that the first portions are connected to each other due to the heat treatment. There is no inconvenience that would occur.
Since the first portion is covered with the sidewall with the sidewall end (the end of the cap insulating film) as a reference, impurities of the second conductivity type are not introduced by ion implantation, so that the conductivity type is reduced. There is no problem of inversion or increase of the resistance value.

In this way, the surface of the body P layer can be made highly concentrated without using a mask using photolithography technology. Therefore, there is no need to provide a margin in consideration of a mask shift or the like, and the device can be further miniaturized and the on-resistance of the transistor can be reduced.

[0028]

BEST MODE FOR CARRYING OUT THE INVENTION

(1) Structure of Power MOSFET Employing Trench Gate FIG. 19 shows a cross-sectional structure of a vertical power MOSFET employing a trench gate according to the present embodiment.

In this vertical MOSFET, a body P layer 20 is formed on the N ⁺ layer 5 and the N ⁻ layer 10 serving as a drain, and a P ⁺ layer 130 is formed on the surface of the body P layer 20. I have.

Gate insulating films 70a and 70b are formed on the inner wall surface of the trench, and the inside of the trench is filled with gate electrode layers 80a and 80b made of polysilicon. The surface is covered with cap oxide films 90a and 90b.

On the surface of body P layer 20, source layers (n) are in contact with gate insulating films 70a and 70b.
⁺ ) 60a, 60b and the like are formed.

Then, on the substrate surface, the source electrode 2
00 is formed in contact with the P ⁺ layer 130 and the source layers (n ⁺ ) 60a and 60b on the surface of the body P layer 20, and the drain electrode 220 is formed on the back surface of the substrate.

When the transistor is turned on, an on-current I flows from the back surface (drain) of the substrate to the front surface (source) of the substrate. Gate insulating film 70 of body P layer 20
The region in contact with a and 70b is the channel region.

FIG. 20 shows an equivalent circuit of a MOSFET having such a structure. In the figure, “G” is a gate, “D” is a drain, and “S” is a source.
The potential of the channel region is the source potential and is stabilized. Since the P ⁺ layer 130 is formed on the surface of the body P layer 20, the parasitic resistance (FIG. 23A,
The resistance value of the resistor R) shown in FIG. 3B is small, and the structure is such that the parasitic transistor is difficult to turn on.

When the N ⁺ layer 5 on the back surface of the substrate shown in FIG. 19 is replaced with a P ⁺ layer, an IGBT is obtained. IGBT
Is an inverted Darlington transistor with a MOS top, in which case the N ⁺ layers 60a and 60b function as emitters, and the P ⁺ layer on the back surface of the substrate functions as a collector.

The present invention can be similarly applied not only to a power MOSFET but also to an IGBT. Hereinafter, a power MOSFET will be described as an example.

(2) Power M using trench gate
Hereinafter, a method for manufacturing the power MOSFET according to the present embodiment will be described with reference to FIGS.

FIGS. 1 to 13 are cross-sectional views of the device in each step showing the main parts of the main steps of the manufacturing process according to the present embodiment. FIGS. 14 to 18 are shown in FIGS. FIGS. 3A and 3B are auxiliary drawings (plan view and cross-sectional view) for facilitating understanding of a manufacturing process to be performed. FIG. 14 (a),
17B corresponds to FIG. 2, FIGS. 15A and 15B correspond to FIG. 3, FIGS. 16A and 16B correspond to FIG.
FIGS. 18A to 18C correspond to FIG. 7 and FIGS.
Corresponds to FIG.

In FIG. 1 to FIG. 13, the N ⁺ layer 5 in FIG. 19 is omitted. The source region of the transistor of this embodiment is formed in a ladder-like pattern when viewed in plan. Further, a stripe-shaped portion along the trench of the ladder-shaped source is defined as a first portion, and a portion orthogonal to the first portion is defined as a second portion.

Step 1 First, as shown in FIG. 1, a silicon nitride film (Si) is formed on the drain layer (N ⁻ ) 10 and the body P layer (P ⁻ ) 20.
₃ N ₄₎ a trench mask 30 is formed consisting, followed by ion implantation of arsenic (As). At this time, the dose amount is about 3 × 10 ¹⁴ atms / cm ^2, which is about one digit lower than the impurity concentration for forming a normal source. This is for the following reason.

The impurities introduced in this step are activated and diffused by a later heat treatment in a sacrificial oxidation step and a gate insulating film forming step, and are thereby converted into the first portion (along the trench) which is a component of the ladder-like source region. Stripe-shaped portion). Therefore, if the amount of the N-type impurity introduced in this step is too large, the diffusion due to the heat treatment may progress too much and the diffusion layer may become too deep. Can not be achieved.
Therefore, the impurity concentration is kept low.

Step 2 Next, as shown in FIG. 2, sidewalls 40a and 40b are formed in contact with both end surfaces of the trench mask 30. The sidewalls 40a and 40b are formed by CVD using S
An SiO ₂ film is formed on the entire surface of the substrate, and is subjected to RIE (reactive ion etching) to form an S ₂ O ₃ film on the trench mask 30.
It is formed by removing the iO ₂ film.

The reason why the sidewalls 40a and 40b are formed is to determine the positional relationship between the trench and the source region by self-alignment. This will be described in the following steps.

FIGS. 14A and 14B are a plan view and a cross-sectional view of the device in this step. In (a), only a main part is extracted and drawn in the plan view.
(B) is sectional drawing which follows the AA line of the device shown to (a).

Step 3 As shown in FIG. 3, the substrate is vertically etched by RIE with reference to the ends of the sidewalls 40a and 40b to form trenches 50a and 50b.

At this time, the side walls 40a, 40b
Is formed, a part of the arsenic (As) introduced in the step 1 (FIG. 1) remains without being removed even after performing anisotropic etching.

FIGS. 15A and 15B are a plan view and a cross-sectional view of the device in this step. (B)
FIG. 3 is a cross-sectional view of the device shown in FIG.

Step 4 Subsequently, as shown in FIG. 4, damage to the substrate caused by trench processing is recovered by sacrificial oxidation and removal of the sacrificial oxide film. A part of the remaining arsenic (As) is activated by the heat treatment (1000 ° C. or higher) at the time of the sacrificial oxidation, and the first portions 60a and 60b, which are constituent parts of the ladder-like source region (N ⁺ ), are formed. Is done.

That is, the sacrificial oxidation step also serves as the step of forming the source region (first portion).

Instead of sacrificial oxidation, for example, chemical dry etching (CDE) may be performed to remove damage due to etching.

Step 5 As shown in FIG. 5, the inner wall surface of the trench is oxidized by heat treatment to form gate oxide films 70a and 70b. By the heat treatment at this time, the first portion 60a of the source region,
60b extends outward. The impurity concentration of the first portion is 1
It is about × 10 ¹⁹ atms / cm ³ .

FIGS. 16A and 16B are a plan view and a sectional view of the device in this step. (B)
FIG. 3 is a cross-sectional view of the device shown in FIG.

If sacrificial oxidation is not performed in step 4, this step also serves as the step of forming the first portion of the source region.

In this manner, the first portions 60a and 60b of the source region are automatically formed along the trench. That is, the first portions 60a and 60b are formed in a self-aligned manner with respect to the trench. Therefore, there is no need to provide a margin (margin) in consideration of the mask displacement, and the device can be miniaturized. This leads to a reduction in the on-resistance of the transistor.

Step 6 Next, as shown in FIG. 6, gate electrodes 80a and 80b made of polysilicon are embedded in the trench. This burying is performed by removing unnecessary portions by RIE after depositing polysilicon.

As the polysilicon, either non-doped polysilicon or doped polysilicon can be used.

Step 7 Next, as shown in FIG. 7, a trench mask (Si ₃ N ₄ )
Using the mask 30 as a mask, the surface of the polysilicon filling the trench is oxidized (locally oxidized) to form cap oxide films 90a and 90b. Trench mask (S
Since i ₃ N ₄ ) 30 is also used as an oxidation mask, cap oxidation can be performed in a self-aligned manner. Since the cap oxide films 90a and 90b expand in volume during oxidation, a step is formed between the cap oxide films 90a and 90b and the surface of the substrate.

Then, a trench mask (Si ₃ N ₄ ) 30
Is removed.

Step 8 Next, as shown in FIG. 8, in the direction orthogonal to the trench,
The resist masks 100a, 100b, 100c are formed. This photoresist step does not hinder a series of continuous self-alignment processes, since it is sufficient that the relative positional relationship between the respective resist masks is maintained and absolute position accuracy is not required.

Then, arsenic (As) is introduced into the substrate surface by ion implantation. The dose in this case is shown in FIG.
Larger than the dose in the case of 3 × 10 ¹⁵ atms /
cm ² or more.

Even if the dose is increased in this manner, since the formation of the gate structure (high-temperature heat treatment for forming a gate oxide film) has already been completed, there is no fear that the impurity layer is unnecessarily spread.

Step 9 As shown in FIG. 9, the arsenic (As) introduced in Step 8 is activated by heat treatment (800 ° C., about 20 minutes).
Second portions 110a and 110b, which are constituent portions of the ladder-shaped source region (N ⁺ ), are formed. N of this second part
The type impurity concentration is preferably set to 1 × 20 atms / cm ³ or more.

As a result, the first portions 60a, 60b
And the second portions 110a and 110b are connected to form a source region having a ladder-like pattern. The ladder-shaped source region contributes to a reduction in on-resistance of the transistor.

FIGS. 17A to 17C are a plan view and a cross-sectional view of the device in this step. (A) is a plan view of the device, (b) is a cross-sectional view along line AA in (a), and (c) is a cross-sectional view along line BB in (a).

Step 10 Next, as shown in FIG. 10, the cap oxide films 90a, 90
side walls 120a, 120 with reference to the end of b
b is formed. The formation method of the sidewalls 120a and 120b is as follows.
0b (the combination of CVD and RIE), and therefore the sidewalls 120a, 120b
Are formed in a self-aligned manner without going through a photolithography process.

The sidewalls 120a, 120b
Covers at least a main part of the first portions 60a and 60b of the ladder-like source region extending in a stripe shape along the trench. These sidewalls 120a, 12
Ob functions as a mask when introducing P-type impurities into the surface of the body P layer in the next step.

It is desirable that the sidewalls 120a and 120b completely cover the first portions 60a and 60b of the source region. However, even if the end portions of the sidewalls 40a and 40b do not match the end positions of the first portions 60a and 60b of the source region, and a part of the first portion protrudes, there is actually a problem. There is no.

This is because the channel of the vertical MOS transistor is formed by the gate insulating film 70a formed on the inner wall of the trench.
70b, and is formed in a portion in contact with 70b.
This is because if the impurity concentration of a portion connected to the channel is equal to or higher than a predetermined value, the channel sufficiently functions as a source.

Step 11 Subsequently, as shown in FIG. 11, boron fluoride (BF ₂ ) as a P-type impurity is ion-implanted over the entire surface of the substrate. B
The reason for using F ₂ is to enable extremely shallow ion implantation by using impurities having a large mass.
In this case, the dose amount of BF ₂ is 1 × 10 ¹⁵ atms /
cm ² or less.

By implanting BF ₂ , the impurity concentration on the surface of body P layer 20 is increased, the resistance value on the surface of body P layer is reduced, and the contact resistance when a source electrode is connected later is also reduced. . Therefore, the parasitic transistor is not easily turned on, and destruction of the MOSFET can be suppressed.

On the other hand, BF ₂ is also implanted into the second portions (N ⁺ ) 110a and 110b, which are constituent parts of the ladder-shaped source region, and the implanted P-type impurities are directed in the direction of increasing the source resistance. Works.

However, since the concentration of the N-type impurity in the second portions 110a and 110b is as high as 1 × 20 atms / cm ³ or more, there is almost no problem in practice.

FIG. 21 shows the results of an experiment for verifying this. FIG. 21 shows that the N-type impurity concentration is 1 × 10 ^20.
When a P-type impurity (BF ² ) is ion-implanted into a semiconductor substrate of / cm ³ , the dose of the P-type impurity changes according to the change in dose.
FIG. 11 is a graph showing the results of actually measuring how the contact resistance changes when a metal electrode is connected to the substrate surface.

As the introduction amount of the P-type impurity is increased, the contact resistance is gradually increased, but the dose amount is 1 × 10 ¹⁵ atms / cm ² (in terms of impurity concentration, N
(About 1/3 of the impurity of the mold substrate), the contact resistance is about 24Ω, and it can be seen that a sufficiently low contact resistance (source contact resistance) is realized.

On the other hand, the dose of the P-type impurity is 1 × 10 ¹⁵
At about atms / cm ² , the impurity concentration on the surface of the body P layer 20 is at a level that does not cause any problem, and the contact resistance to the body P layer can be suppressed low. Therefore, the parasitic transistor is less likely to be turned on, and element destruction can be suppressed.

Step 12 The ion-implanted BF ₂ is activated by annealing at 900 ° C. for about 30 minutes, and a P ⁺ layer 130 is formed on the surface of the body P layer 20 as shown in FIG. As described above, the contact resistance to the body P region can be obtained without any problem, and the element destruction accompanying the operation of the parasitic bipolar transistor can be suppressed.

Step 13 If necessary, as shown in FIG.
10a and 110b are removed.

FIGS. 18A to 18C are plan and sectional views of the device in this step. (A) is a plan view of the device, (b) is a cross-sectional view along line AA in (a), and (c) is a cross-sectional view along line BB in (a).

FIG. 22 shows the flow of the manufacturing process described above.

That is, first, a trench mask is formed (Step 300), and an N-type impurity is introduced (Step 3).
02) Then, a sidewall is formed (step 30).
4) Yes.

Next, a trench is formed (step 30).
6), sacrificial oxidation, removal of the sacrificial oxide film, and gate oxidation are performed to form a first stripe-shaped source region along the trench.
Is formed (step 308).

Next, a gate electrode is formed (step 31).
0), cap oxidation is performed (step 312).

Next, a resist mask is formed in a direction orthogonal to the trench (step 314), and then a ladder-shaped source region is formed by introducing an N-type impurity and performing heat treatment (step 316).

Next, a sidewall covering the first portion of the source is formed (step 318), and a P-type impurity is introduced using the sidewall as a mask to form a body P.
A P ⁺ layer is formed on the surface of the layer (step 320).

As described above, by using the self-alignment many times in succession, it becomes possible to manufacture an extremely fine element without useless space.

The present invention can be widely applied to the manufacture of a semiconductor device using a trench. In particular, MOSFET, IGB
It is widely applicable to the manufacture of vertical insulated gate devices such as T and insulated gate thyristors.

[0087]

[Brief description of the drawings]

FIG. 1 is a perspective sectional view of a main part showing a first step in an embodiment of a method of manufacturing a semiconductor device according to the present invention.

FIG. 2 is a perspective cross-sectional view of a main part showing a second step of the embodiment of the method for manufacturing a semiconductor device according to the present invention;

FIG. 3 is a perspective sectional view of a main part showing a third step of the embodiment of the method for manufacturing a semiconductor device according to the present invention;

FIG. 4 is a perspective sectional view of a main part showing a fourth step of the embodiment of the method for manufacturing a semiconductor device according to the present invention;

FIG. 5 is a perspective sectional view of a main part showing a fifth step of the embodiment of the method for manufacturing a semiconductor device according to the present invention;

FIG. 6 is a perspective sectional view of a main part showing a sixth step of the embodiment of the method for manufacturing a semiconductor device according to the present invention;

FIG. 7 is a perspective sectional view of a main part showing a seventh step of the embodiment of the method for manufacturing a semiconductor device according to the present invention;

FIG. 8 is a perspective sectional view of an essential part showing an eighth step of the embodiment of the method for manufacturing a semiconductor device of the present invention.

FIG. 9 is a perspective sectional view of a main part showing a ninth step of the embodiment of the method for manufacturing a semiconductor device according to the present invention;

FIG. 10 shows an embodiment of a method for manufacturing a semiconductor device according to the present invention;
It is a perspective sectional view of the important section showing a 10th process.

FIG. 11 shows an embodiment of a method for manufacturing a semiconductor device according to the present invention;
It is a perspective sectional view of the important section showing an 11th process.

FIG. 12 shows an embodiment of a method for manufacturing a semiconductor device according to the present invention;
It is a perspective sectional view of the important section showing a twelfth process.

FIG. 13 shows an embodiment of a method of manufacturing a semiconductor device according to the present invention;
It is a perspective sectional view of an important section showing a 13th process.

14A is a plan view of the device in the step of FIG. 2, and FIG. 14B is a cross-sectional view of the device in the step of FIG.

15A is a plan view of the device in the step of FIG. 3, and FIG. 15B is a cross-sectional view of the device in the step of FIG.

16A is a plan view of the device in the step of FIG. 5, and FIG. 16B is a cross-sectional view of the device in the step of FIG.

17A is a plan view of the device in the step of FIG. 7, FIG. 17B is a cross-sectional view of the device along line AA in the plan view of FIG. 17A, and FIG. FIG. 3 is a cross-sectional view of the device taken along line BB in the plan view of FIG.

18A is a plan view of the device in the step of FIG. 13, FIG. 18B is a cross-sectional view of the device along the line AA in the plan view of FIG. FIG. 3 is a cross-sectional view of the device taken along line BB in the plan view of FIG.

FIG. 19 is a cross-sectional view of a main part of a vertical MOSFET manufactured through the steps of FIGS.

FIG. 20 is a diagram showing an equivalent circuit of the device of FIG. 19;

FIG. 21 shows a result of actually measuring a change in contact resistance of an N-type region when a P-type impurity (BF ₂ ) is ion-implanted into a surface of a silicon substrate having an N-type impurity concentration of 1 × 10 ²⁰ / cm ^3. FIG.

FIG. 22 is a view illustrating a process flow of a method of manufacturing a semiconductor device according to an embodiment of the present invention;

23A is a cross-sectional view of a device for explaining a mechanism of element destruction in a power MOSFET (UMOS), and FIG. 23B is a diagram showing an equivalent circuit of the device shown in FIG.

[Explanation of symbols]

10 drain layer 20 body P layer 30 trench mask _{(Si 3 N 4) 40a,} 40b side wall 50a, 50b trenches 60a, 60b first portion 70a constituting the ladder-like source region (N ^+), 70b a gate oxide film 80a , 80b Gate electrode material layer (polysilicon) 90a, 90b Cap oxide film 100a, 100b, 100c Resist mask 110a, 110B Second portion constituting ladder-shaped source region (N ⁺ ) 120a, 120b Sidewall 200 Source electrode 220 Drain electrode

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Sachiko Kawaji 41-cho, Yokomichi, Nagakute-cho, Aichi-gun, Aichi Prefecture Inside Toyota Central Research Laboratory Co., Ltd. (72) Inventor Toshio Murata Nagakute-cho, Aichi-gun, Aichi 41 No. 1, Yokomichi, Chuchu, Toyota Central Research Institute, Inc.

Claims (1)

[Claims] A step of forming a sidewall in contact with a side wall of a step portion above the trench, thereby covering at least a part of a first conductivity type region formed using a processing mask for the trench; Introducing a second conductivity type impurity using the sidewall as a mask.