JP3489358B2 - Method for manufacturing semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a MOSFET having a trench gate structure.
(UMOS) and IGBT (Insulated Gat)
e Bipolar Transistor) and the like, and a method for manufacturing a vertical insulated gate semiconductor device.

[0002]

[Background technology]

(1) A UMOSFET having a trench gate is attracting attention as a next-generation power MOSFET because it can easily reduce the on-resistance as compared with a conventional planar power MOSFET.

In UMOSFETs, it is important to reduce the on-resistance, and one technique for reducing the on-resistance is to "make the planar pattern of the source (n ⁺ ) region into a ladder pattern" ( For example, Japanese Patent Laid-Open No. 7-2235
672).

In Japanese Unexamined Patent Publication No. 7-2235672, first, a ladder-shaped source region is formed, then the impurity diffusion mask used for forming the source is removed, and a new mask for trench processing is formed by a photolithography technique. However, the trench is processed.

(2) On the other hand, in order to improve the breakdown resistance of the power MOSFET, it is necessary to increase the impurity concentration in the surface portion of the P-type body layer. This will be described below.

FIG. 23 (a) shows a vertical power MOSFET.
The structural example of (UMOSFET) is shown. Multiple MOSFE
The inductive load L is driven by T500a to 500n, and one MOSFET is
N ⁺ substrate 400, N ⁻ epitaxial layer 402, body P
Layer 404, source layers (N ⁺ ) 406a and 406b, gate insulating film 410, gate electrode 408, source electrode 412
a, 412b.

In the figure, reference numbers Q1 and Q2 are parasitic NPN transistors, reference numbers D1 and D2 are parasitic diodes, and reference number R is a parasitic resistance of the body P layer (including body contact resistance). Note that reference numeral 42
0 is a power supply.

FIG. 23 (b) shows an equivalent circuit of the device of FIG. 23 (a).

A parasitic diode D1 and a resistor R are connected in series between the source (S) and the drain (D) of the MOSFET (M), and the parasitic NPN transistor Q1 is connected in parallel with the series path of D1 and R. The collector-emitter path of is interposed.

As shown in FIG. 23A, when the MOS transistor (M) changes from on to off, the breakdown current IB1 is caused by the back electromotive force of the inductance load (L) and the diode D1 (D2) is generated. ) And resistor R1
Flow through (R2). At this time, the resistance R1 (R2)
When the voltage drop across both ends exceeds the base-emitter voltage (V _BE ) of the parasitic bipolar transistor Q1 (Q2), the parasitic bipolar transistor Q1 (Q2) is turned on, and an excessive breakdown current IB2 causes the transistor Q1 ( It flows concentratedly in Q2), and in most cases, junction breakdown or melting of silicon or wiring occurs and the element is destroyed.

In particular, when a power MOSFET or the like is used for vehicle control, most of the in-vehicle load is an inductance load such as a motor or a solenoid valve, so it is extremely important to avoid avalanche breakdown caused by an inductance back electromotive force. Is. As described above, the avalanche breakdown is a phenomenon that leads to the breakdown with the operation of the parasitic bipolar transistor existing in the power MOSFET structure, and it is necessary to suppress the operation of the parasitic bipolar transistor in order to realize a high breakdown resistance.

To this end, the resistance value of the resistor R1 (R2) in FIGS. 23A and 23B is reduced, and the voltage drop in the resistor R1 (R2) when the breakdown current IB1 flows is parasitic. It must be lower than the base-emitter voltage (V _BE ) of the bipolar transistor Q1 (Q2). Therefore, it is important to increase the concentration of P-type impurities on the surface of the body P layer 404 to reduce the resistance.

In the conventional MOSFET manufacturing method,
Increasing the concentration of the surface of this P-type body region (formation of P ⁺ layer)
Is performed by forming a mask using a photolithography technique and introducing impurities into the surface of the P-type body region by an ion implantation method.

[0014]

As described above, since the step of increasing the impurity concentration on the surface of the body P layer is performed by using the photolithography technique, it is necessary to allow a margin for alignment with the trench gate. There is a limit to the reduction of the source area.

In addition, a ladder-shaped source region and a trench
This also hinders further miniaturization of the source region because it is necessary to consider the alignment error with the.

The present invention has been made by paying attention to such problems, and one of the objects thereof is to provide a novel element process technology for enabling further miniaturization of devices. Another object of the present invention is to self-align the manufacturing process of a vertical power device to promote device miniaturization and further reduce the on-resistance of a transistor.

[0017]

(1) One of the methods for manufacturing a semiconductor device according to the present invention is a semiconductor device having a trench gate structure.
A method of manufacturing a conductor device, comprising:
A trench processing mask is formed on the top surface of the semiconductor layer
Step of introducing impurities of one conductivity type and the trench processing
Of forming a first sidewall on a sidewall of a mask for use
And the trench processing mask and the first sidewall.
A trench as a mask to form a trench in the semiconductor layer.
And the gate oxidation formed on the inner wall of the trench
A process for forming a gate electrode in the trench through a film.
And the surface of the semiconductor layer on the gate electrode.
A step of forming a cap insulating film having a step portion between them,
A small amount of the semiconductor layer in which the impurity of the first conductivity type has been introduced.
Side wall of the stepped portion of the cap insulating film on at least a part
A step of forming a second sidewall on the
Second conductivity is applied to the semiconductor layer using the sidewall as a mask
And a step of introducing a type impurity.

The first conductivity type region formed using the trench processing mask and the trench (and the stepped portion above the trench) have a self-alignment relationship. Further, the stepped portion above the trench and the end portion of the second sidewall have a self-alignment relationship. Therefore, the position of the region of the first conductivity type
The position of the end portion of the second sidewall is both determined based on the trench (the end portion of the stepped portion above the trench). Therefore, the second sidewall is always located above the first conductivity type region. Therefore, the ion implantation mask can be formed by self-alignment without using the photolithography technique.

Therefore, the process can be simplified and the device can be miniaturized because it is not necessary to consider the alignment margin.

(2) By using the above element processes, it becomes possible to self-align the manufacturing process of the vertical power device to promote the miniaturization of the device and further reduce the on-resistance of the transistor. This is another invention related to the present application, and the contents are as follows. In the following invention, "cap insulating layer"
Corresponds to the above-mentioned “step portion above the trench”.

That is, the second semiconductor layer of the second conductivity type is formed on the first semiconductor layer of the first conductivity type, and the first semiconductor layer having the ladder-shaped plane pattern is formed on the surface portion of the second semiconductor layer. A conductivity type impurity region is formed, a groove that penetrates a portion of the second semiconductor layer and reaches the first semiconductor layer is formed, and a gate electrode material is formed inside the groove through a gate insulating film. The surface of the gate electrode material is filled with the cap insulating layer, the surface of the impurity region of the first conductivity type having the ladder-shaped plane pattern and the second conductivity type second region.
A method for manufacturing a semiconductor device, wherein a common electrode is connected to the surface of the semiconductor layer, and the surface of the second semiconductor layer of the second conductivity type to which the electrode is connected has a high impurity concentration, A step of forming a first portion forming the first conductivity type impurity region having the ladder-shaped plane pattern along the groove; and the ladder-shaped plane pattern in a direction intersecting with the first portion. Forming a second portion having a higher impurity concentration than the first portion, which constitutes a first-conductivity-type impurity region having: and covering the surface of the gate electrode material filled in the groove. Forming a side wall with reference to an end of the cap insulating layer and covering at least a part of the surface of the first portion with the side wall; and masking the cap insulating layer and the side wall. And a second conductivity type impurity is introduced into the surfaces of the second portion and the second semiconductor layer to increase the impurity concentration of the surface of the second semiconductor layer. It is what

The present invention is a method of manufacturing a semiconductor device, which realizes a high concentration of the surface of the body P layer by self-alignment.

That is, a first portion having a low impurity concentration in a ladder-shaped first conductivity type impurity region (source region in a power MOSFET, emitter region in the case of an IGBT) is formed along a trench (trench), and A second high impurity concentration in the direction intersecting (preferably orthogonal to) the first portion
Part is formed, and the first part having a low impurity concentration is covered with a sidewall having the trench end (the end part of the cap insulating film) as a reference, and the second conductivity type impurity is introduced into the entire surface by ion implantation. . The series of processes are all self-aligned.

Since the impurity concentration on the surface of the body P layer increases and the resistance becomes low, the breakdown resistance of the element does not decrease.

On the other hand, since the second portion of the ladder-shaped first conductivity type impurity region has a high impurity concentration, even if the second conductivity type impurity is introduced by ion implantation,
Since the conductivity type is maintained and the impurity concentration sufficient for actual use can be secured, no problem occurs.

Further, since the first portion of the ladder-shaped impurity region has a low impurity concentration, excessive diffusion due to the heat treatment is prevented, so that the first portions are connected to each other due to the heat treatment. There is no inconvenience.
Since the first portion is covered with the side wall with the side wall end (the end portion of the cap insulating film) as a reference, impurities of the second conductivity type are not introduced by ion implantation, and the conductivity type The problem of inversion and increase of resistance does not occur.

In this way, the surface concentration of the body P layer can be increased without using the mask formation using the photolithography technique. Therefore, it is not necessary to provide a margin in consideration of mask shift and the like, and it is possible to further miniaturize the device and reduce the on-resistance of the transistor.

[0028]

BEST MODE FOR CARRYING OUT THE INVENTION (1) Structure of Power MOSFET Employing Trench Gate FIG. 19 shows a sectional structure of a vertical power MOSFET adopting a trench gate according to this embodiment.

In this vertical MOSFET, a body P layer 20 is formed on the N ⁺ layer 5 and the N ⁻ layer 10 to be drains, and a P ⁺ layer 130 is formed on the surface portion of the body P layer 20. There is.

Gate insulating films 70a and 70b are formed on the inner wall surfaces of the trenches, and gate electrode layers 80a and 80b made of polysilicon are filled inside the trenches to form the gate electrode layers 80a and 80b. The surface is covered with cap oxide films 90a and 90b.

Further, in the surface portion of the body P layer 20, the source layer (n is in contact with the gate insulating films 70a and 70b).
⁺ ) 60a, 60b, etc. are formed.

Then, on the surface of the substrate, the source electrode 2
00 is formed in contact with the P ⁺ layer 130 on the surface of the body P layer 20 and the source layers (n ⁺ ) 60a and 60b, and the drain electrode 220 is formed on the back surface of the substrate.

When the transistor is turned on, an on-current I flows from the back surface (drain) of the substrate to the front surface (source) of the substrate. Gate insulating film 70 of body P layer 20
The region in contact with a and 70b becomes the channel region.

An equivalent circuit of a MOSFET having such a structure is shown in FIG. In the figure, "G" is a gate, "D" is a drain, and "S" is a source.
The potential of the channel region is the source potential and is stabilized. Since the P ⁺ layer 130 is formed on the surface of the body P layer 20, parasitic resistance (FIG. 23A,
The resistance value of the resistor R in (b) is small, and the parasitic transistor is hard to turn on.

When the N ⁺ layer 5 on the back surface of the substrate shown in FIG. 19 is replaced with a P ⁺ layer, an IGBT is obtained. IGBT
Is a MOS top inverted Darlington transistor. In this case, the N ⁺ layers 60a and 60b serve as emitters, and the P ⁺ layer on the back surface of the substrate serves as a collector.

Although the present invention can be applied not only to the power MOSFET but also to the IGBT, the power MOSFET will be described below as an example.

(2) Power M adopting a trench gate
Manufacturing Method of OSFET Hereinafter, a manufacturing method of the power MOSFET according to the present embodiment will be described with reference to FIGS.

FIGS. 1 to 13 are sectional views of the device for each step showing the main parts of the main steps of the manufacturing process of this embodiment, and FIGS. 14 to 18 are shown in FIGS. 3 is an auxiliary drawing (plan view and cross-sectional view) for facilitating the understanding of the manufacturing process performed. FIG. 14 (a),
FIG. 15B corresponds to FIG. 2, FIGS. 15A and 15B correspond to FIG. 3, FIGS. 16A and 16B correspond to FIG.
18 (a) to 18 (c) correspond to FIG. 7, and FIGS.
Corresponds to FIG.

Incidentally, in FIGS. 1 to 13, the N ⁺ layer 5 of FIG. 19 is omitted. In addition, the source region of the transistor of this embodiment is formed in a ladder pattern when seen in a plan view. A stripe-shaped portion along the trench of the ladder-shaped source is referred to as a first portion, and a portion orthogonal to the first portion is referred to as a second portion.

Step 1 First, as shown in FIG. 1, a silicon nitride film (Si) is formed on the drain layer (N ⁻ ) 10 and the body P layer (P ⁻ ) 20.
_A trench mask 30 made of ₃ N ₄ ) is formed, and then arsenic (As) is ion-implanted. The dose amount at this time is about 3 × 10 ¹⁴ atms / cm ^2, which is about one digit lower than the impurity concentration for normal source formation. This is for the following reason.

The impurities introduced in this step are activated and diffused by a heat treatment in a later sacrificial oxidation step or a step of forming a gate insulating film, and the impurities are introduced into the first portion (along the trench) which constitutes the ladder source region. It becomes a striped part). Therefore, if the amount of N-type impurities introduced in this step is too large, the diffusion due to the heat treatment may proceed too much and the diffusion layer may become too deep. To prevent this, if the distance between the trenches is increased, the device Cannot be realized.
Therefore, the impurity concentration is kept low.

Step 2 Next, as shown in FIG. 2, sidewalls 40a and 40b are formed in contact with both end surfaces of the trench mask 30. These sidewalls 40a and 40b are S
An SiO ₂ film is formed on the entire surface of the substrate, and RIE (reactive ion etching) is performed to remove S on the trench mask 30.
It is formed by removing the iO ₂ film.

The sidewalls 40a and 40b are formed in order to determine the positional relationship between the trench and the source region by self-alignment. This will be described in the following steps.

14A and 14B are a plan view and a sectional view of the device in this step. In (a), the plan view is drawn by extracting only the main part.
(B) is sectional drawing which follows the AA line of the device shown to (a).

Step 3 As shown in FIG. 3, the substrate is vertically etched by RIE using the ends of the sidewalls 40a and 40b as a reference to form trenches 50a and 50b.

At this time, the side walls 40a, 40b
Due to the formation of Al, some of the arsenic (As) introduced in step 1 (FIG. 1) remains without being removed even after anisotropic etching.

15A and 15B are a plan view and a sectional view of the device in this step. (B)
[Fig. 4] is a sectional view taken along line AA of the device shown in (a).

Step 4 Subsequently, as shown in FIG. 4, the damage of the substrate due to the trench processing is recovered by sacrificial oxidation and removal of the sacrificial oxide film. A part of the remaining arsenic (As) is activated by the heat treatment at the time of sacrificial oxidation (1000 ° C. or higher) to form the first parts 60a and 60b which are the constituent parts of the ladder-shaped source region (N ⁺ ). To be done.

That is, the sacrificial oxidation step also serves as the step of forming the source region (first portion).

Instead of sacrificial oxidation, for example, chemical dry etching (CDE) may be performed to remove the damage due to etching.

Step 5 As shown in FIG. 5, the inner wall surface of the trench is oxidized by heat treatment to form gate oxide films 70a and 70b. By the heat treatment at this time, the first portion 60a of the source region,
60b extends outward. The impurity concentration of the first portion is 1
It is about × 10 ¹⁹ atms / cm ³ .

16A and 16B are a plan view and a sectional view of the device in this step. (B)
[Fig. 4] is a sectional view taken along line AA of the device shown in (a).

If sacrificial oxidation is not performed in step 4, this step also serves as the step of forming the first portion of the source region.

In this way, the first portions 60a and 60b of the source region are automatically formed along the trench. That is, the first portions 60a and 60b are formed in self-alignment with the trench. Therefore, it is not necessary to provide a margin in consideration of the displacement of the mask and the like, and the device can be miniaturized. This leads to a reduction in the on resistance of the transistor.

Step 6 Next, as shown in FIG. 6, gate electrodes 80a and 80b made of polysilicon are buried in the trench. This burying is performed by removing unnecessary portions by RIE after depositing polysilicon.

As the polysilicon, either undoped one or doped polysilicon can be used.

Step 7 Next, as shown in FIG. 7, a trench mask (Si ₃ N ₄ ) is used.
The surface of the polysilicon filled in the trench is oxidized (local oxidation) using 30 as a mask to form cap oxide films 90a and 90b. Trench mask (S
Since i ₃ N ₄ ) 30 is also used as an oxidation mask, cap oxidation can be performed by self-alignment. Since the cap oxide films 90a and 90b expand in volume during oxidation, a step is formed between the cap oxide films 90a and 90b and the surface of the substrate.

Then, the trench mask (Si ₃ N ₄ ) 30
To remove.

Step 8 Next, as shown in FIG. 8, in the direction orthogonal to the trench,
Resist masks 100a, 100b, 100c are formed. This photoresist process does not interfere with a series of continuous self-alignment processes as long as the relative positional relationship between the resist masks is maintained and absolute position accuracy is not required.

Then, arsenic (As) is introduced into the substrate surface by the ion implantation method. The dose in this case is shown in Fig. 1.
Larger than the dose amount in the case of 3 × 10 ¹⁵ atms /
It is preferably at least cm ² .

Even if the dose amount is increased in this way, since the formation of the gate structure (the high temperature heat treatment for forming the gate oxide film) has already been completed, the impurity layer does not unnecessarily spread.

Step 9 As shown in FIG. 9, the arsenic (As) introduced in Step 8 is activated by heat treatment (800 ° C., about 20 minutes),
Second portions 110a and 110b, which are constituent portions of a ladder-shaped source region (N ⁺ ) are formed. N of this second part
The type impurity concentration is preferably 1 × 20 atms / cm ³ or more.

As a result, the first portions 60a, 60b
And the second portions 110a and 110b are connected to form a source region having a ladder pattern. The ladder shape of the source region contributes to reduction of the on-resistance of the transistor.

Plan views and cross-sectional views of the device in this step are shown in FIGS. 17 (a) to 17 (c). (A) is a top view of a device, (b) is sectional drawing which follows the AA line in (a), (c) is sectional drawing which follows the BB line in (a).

Step 10 Next, as shown in FIG. 10, cap oxide films 90a, 90 are formed.
Side walls 120a, 120 based on the end of b
b is formed. The sidewalls 120a and 120b are formed by the sidewalls 40a and 4a in step 2 (FIG. 2).
0b formation method (combination of CVD and RIE), and therefore the sidewalls 120a, 120b
Is also formed in a self-aligned manner without a photolithography process.

The side walls 120a and 120b
Covers at least a major part of the first portions 60a and 60b of the ladder-shaped source region extending in stripes along the trench. This side wall 120a, 12
0b functions as a mask when the P-type impurity is introduced into the surface of the body P layer in the next step.

It is desirable that the sidewalls 120a and 120b completely cover the first portions 60a and 60b of the source region. However, even if the positions of the end portions of the sidewalls 40a and 40b do not match the positions of the end portions of the first portions 60a and 60b of the source region and a part of the first portion protrudes, it is actually a problem. There is no.

This is because the channel of the vertical MOS transistor is the gate insulating film 70a formed on the inner wall of the trench,
Of the source region, which is formed in a portion in contact with 70b,
This is because if the impurity concentration of the portion connected to the channel is equal to or higher than a predetermined value, it functions sufficiently as a source.

Step 11 Subsequently, as shown in FIG. 11, boron fluoride (BF ₂ ) which is a P-type impurity is ion-implanted on the entire surface of the substrate. B
The reason why F ₂ is used is that it enables extremely shallow ion implantation by using an impurity having a large mass.
The dose of BF ₂ in this case is 1 × 10 ¹⁵ atms /
It is not more than cm ² .

The implantation of BF ₂ increases the impurity concentration on the surface of the body P layer 20, lowers the resistance value on the surface of the body P layer, and reduces the contact resistance when the source electrode is connected later. . Therefore, it is difficult for the parasitic transistor to turn on, and destruction of the MOSFET can be suppressed.

On the other hand, BF ₂ is also implanted into the second portions (N ⁺ ) 110a and 110b which are the constituents of the ladder-shaped source region, and the implanted P-type impurities tend to increase the source resistance. To work.

However, since the concentration of the N-type impurities in the second portions 110a and 110b is as high as 1 × 20 atms / cm ³ or more, there is practically no problem.

FIG. 21 shows the result of an experiment for demonstrating this. FIG. 21 shows that the N-type impurity concentration is 1 × 10 ^20.
When a P-type impurity (BF ² ) is ion-implanted into a semiconductor substrate of / cm ³ in accordance with the change in the dose amount of the P-type impurity,
It is the figure which made the graph the result of having measured how contact resistance changes when a metal electrode was connected to the substrate surface.

The contact resistance gradually increases as the introduction amount of the P-type impurity increases, but the dose amount is 1 × 10 ¹⁵ atms / cm ² (in terms of impurity concentration, N
Even if it is about 1/3 of the impurities of the mold substrate), the contact resistance is about 24Ω, and it can be seen that a sufficiently low contact resistance (source contact resistance) is realized.

On the other hand, the dose of P-type impurities is 1 × 10 ^15.
If it is about atms / cm ² , the impurity concentration on the surface of the body P layer 20 is at a level without any problem, and the contact resistance with respect to the body P layer can be suppressed low. Therefore, it is difficult for the parasitic transistor to turn on, and element destruction can be suppressed.

Step 12 The ion-implanted BF ₂ is activated by annealing at 900 ° C. for about 30 minutes, and a P ⁺ layer 130 is formed on the surface of the body P layer 20 as shown in FIG. As described above, it becomes a contact resistance to the body P region without any problem, and it is possible to suppress the element destruction due to the operation of the parasitic bipolar transistor.

Step 13 If necessary, as shown in FIG.
10a and 110b are removed.

Plan views and cross-sectional views of the device in this step are shown in FIGS. 18 (a) to 18 (c). (A) is a top view of a device, (b) is sectional drawing which follows the AA line in (a), (c) is sectional drawing which follows the BB line in (a).

The flow of the manufacturing process described above is shown in FIG.

That is, first, a trench mask is formed (step 300) and N-type impurities are introduced (step 3).
02), followed by formation of sidewalls (step 30)
4) Do.

Next, a trench is formed (step 30).
6), sacrificial oxidation, removal of the sacrificial oxide film, and gate oxidation are performed to form the first stripe-shaped source region along the trench.
Is formed (step 308).

Next, a gate electrode is formed (step 31
0), cap oxidation is performed (step 312).

Next, a resist mask is formed in a direction orthogonal to the trench (step 314), and subsequently, N-type impurities are introduced and heat treatment is performed to form a ladder-shaped source region (step 316).

Next, a sidewall is formed to cover the first portion of the source (step 318), P-type impurities are introduced using this sidewall as a mask, and the body P is removed.
A P ⁺ layer is formed on the surface of the layer (step 320).

As described above, by continuously using self-alignment many times, it is possible to manufacture an extremely fine element with no wasted space.

The present invention can be widely applied to the manufacture of semiconductor devices using trenches. In particular, MOSFET, IGB
It is widely applicable to the manufacture of vertical insulated gate devices such as T and insulated gate thyristors.

[0087]

[Brief description of drawings]

FIG. 1 is a perspective sectional view of an essential part showing a first step of an embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 2 is a perspective sectional view of an essential part showing a second step of the embodiment of the method for manufacturing the semiconductor device of the present invention.

FIG. 3 is a perspective sectional view of an essential part showing a third step of the embodiment of the method for manufacturing the semiconductor device of the present invention.

FIG. 4 is a perspective sectional view of an essential part showing a fourth step of the embodiment of the method for manufacturing the semiconductor device of the present invention.

FIG. 5 is a perspective sectional view of an essential part showing a fifth step of the embodiment of the method for manufacturing the semiconductor device of the present invention.

FIG. 6 is a perspective sectional view of an essential part showing a sixth step of the embodiment of the method for manufacturing the semiconductor device of the present invention.

FIG. 7 is a perspective sectional view of an essential part showing a seventh step of the embodiment of the method for manufacturing the semiconductor device of the present invention.

FIG. 8 is a perspective sectional view of an essential part showing an eighth step of the embodiment of the method for manufacturing the semiconductor device of the present invention.

FIG. 9 is a perspective sectional view of an essential part showing a ninth step of the embodiment of the method for manufacturing the semiconductor device of the present invention.

FIG. 10 shows an embodiment of a method for manufacturing a semiconductor device of the present invention,
It is isometric view sectional drawing of the principal part which shows a 10th process.

FIG. 11 shows an embodiment of a method for manufacturing a semiconductor device of the present invention,
It is isometric view sectional drawing of the principal part which shows the 11th process.

FIG. 12 shows an embodiment of a method for manufacturing a semiconductor device of the present invention,
It is isometric view sectional drawing of the principal part which shows the 12th process.

FIG. 13 shows an embodiment of a method for manufacturing a semiconductor device of the present invention,
It is isometric view sectional drawing of the principal part which shows the 13th process.

14A is a plan view of the device in the step of FIG. 2, and FIG. 14B is a cross-sectional view of the device in the step of FIG.

15A is a plan view of the device in the process of FIG. 3, and FIG. 15B is a sectional view of the device in the process of FIG.

16A is a plan view of the device in the step of FIG. 5, and FIG. 16B is a sectional view of the device in the step of FIG.

17 (a) is a plan view of the device in the step of FIG. 7, (b) is a cross-sectional view of the device taken along the line AA in the plan view of (a), and (c) is (a). FIG. 4B is a cross-sectional view of the device taken along the line BB in the plan view of FIG.

18A is a plan view of the device in the step of FIG. 13, FIG. 18B is a sectional view of the device taken along the line AA in the plan view of FIG. 13A, and FIG. FIG. 4B is a cross-sectional view of the device taken along the line BB in the plan view of FIG.

FIG. 19 is a cross-sectional view of a main part of a vertical MOSFET manufactured through the steps of FIGS.

FIG. 20 is a diagram showing an equivalent circuit of the device of FIG.

FIG. 21 shows a result of actual measurement of a change in contact resistance in the N-type region when P-type impurity (BF ₂ ) is ion-implanted into the surface of a silicon substrate having an N-type impurity concentration of 1 × 10 ²⁰ / cm ^3. FIG.

FIG. 22 is a diagram showing a process flow of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

23A is a cross-sectional view of a device for explaining a device destruction mechanism in a power MOSFET (UMOS), and FIG. 23B is a diagram showing an equivalent circuit of the device shown in FIG.

[Explanation of symbols]

10 drain layer 20 body P layer 30 trench mask (Si ₃ N ₄ ) 40a, 40b sidewalls 50a, 50b trenches 60a, 60b first portions 70a, 70b forming a ladder-like source region (N ⁺ ) gate oxide film 80a , 80b Gate electrode material layer (polysilicon) 90a, 90b Cap oxide films 100a, 100b, 100c Resist masks 110a, 110B Second portions 120a, 120b constituting a ladder source region (N ⁺ ) Side wall 200 Source electrode 220 Drain electrode

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toshio Murata, Nagachite-cho, Aichi-gun, Aichi 1-41 Yokomichi, Nagakage, Toyota Central Research Institute Co., Ltd. (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 29/78 H01L 21/336

Claims (3)

(57) [Claims] 1. A semiconductor device having a trench gate structure.
And forming a trench processing mask on the second conductive type semiconductor layer.
And introducing a first conductivity type impurity into the semiconductor layer.
And a first side wall on the side wall of the trench processing mask.
Forming a trench , the trench processing mask, and the first sidewall
And a mask to form a trench in the semiconductor layer.
Through a degree, the gate oxide film formed on an inner wall of the trench
A step of forming a gate electrode in the trench, and a step between the gate electrode and the surface of the semiconductor layer.
A step of forming a cap insulating film having a difference portion, and a step of forming a small amount of the semiconductor layer in which the impurity of the first conductivity type is introduced.
Side wall of the stepped portion of the cap insulating film on at least a part
Forming a second sidewall on the semiconductor layer , and using the second sidewall as a mask
And a step of introducing an impurity of the second conductivity type into
And a method for manufacturing a semiconductor device. 2. The cap insulating film according to claim 1, wherein the surface of the gate electrode is oxidized.
Of a semiconductor device characterized by being formed by
Production method. 3. The semiconductor layer according to claim 1 , wherein a region of the semiconductor layer in which an impurity of a first conductivity type is introduced is used.
The position of the end of the second sidewall with respect to
Based on the position of the cap insulation film formed on the gate electrode
Manufacturing of semiconductor devices characterized by being determined as quasi
Method.