JPH10150171A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the life of a memory from being reduced due to an excess of the number of times of the refreshment of data on storage in storage transistors. SOLUTION: This device is provided with a transistor 111 for test use, which has the same fundamental structure as that of storage transistors 110 and is constituted into such a structure that data on storage in the transistor 111 is disappeared easier than data on storage in the transistors 110, and a means, which detects the disappearance the data on storage in this transistor 111 and refreshes the data on storage in the transistors 110 and the data on storage in the transistor 111. By providing such the transistor 111, as the data on storage in the transistor 111 is disappeared without fail before the data on storage in the transistors 110 is disappeared, the data on storage in the transistors 110 is never disappeared if the refreshment of the data on storage in the transistors 110 is conducted at the time of the disappearance of the data on storage in the transistor 111 and as the number of times of the refreshment is decreased, a break in the device due to an excess of the number of times of the refreshment can be prevented from being generated and the life of the device can be prolonged.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device, and more particularly to a technique for refreshing (rewriting) data stored in a nonvolatile memory or the like.

[0002]

2. Description of the Related Art As a conventional semiconductor device, there is, for example, one described in Japanese Patent Application Laid-Open No. 3-23897. Hereinafter, the structure and operation of the above conventional example will be described with reference to FIG. The device shown in FIG. 8 includes a CPU 1, a memory matrix 2, a timer 3, and a writing circuit 4 including a control circuit. The CPU 1 is connected to the memory matrix 2, the timer 3, and the writing circuit 4, and the writing circuit 4 is further connected to the memory matrix 2 and the timer 3. A nonvolatile memory transistor forming each bit of the memory matrix 2 is a PROM such as a flash memory, an EEPROM or an EPROM.
Consists of

Here, a non-volatile memory transistor generally used for a PROM has a floating gate surrounded by an insulating film. In the PROM, as shown in FIG. 9, data is written in a high threshold voltage state by injecting electron charges into the floating gate, and data is erased in a low threshold voltage state by extracting electron charges. And

However, it is known that such PROMs have difficulty in guaranteeing that stored data is maintained stably due to the following three problems. First, when the use environment temperature is high, for example, in the case of an automobile, the charge in the floating gate is easily lost, that is, the so-called retention characteristic is deteriorated. Second, there is a disturbance caused by applying a voltage to a bit line or a word line when writing or erasing data in another bit. Third,
There is a soft write in which electrons are injected into the floating gate when reading the bit data.

In order to deal with the above problem, in the above-mentioned conventional example, refresh (rewrite) is performed to prevent data loss. Hereinafter, the refresh operation will be described. In FIG. 8, a program stored in the memory matrix 2
1 sends a data rewrite signal to the timer 3 and the write circuit 4. Then, the timer 3 sends the time necessary for rewriting the data of each bit to the writing circuit 4, and the writing circuit 4 rewrites, ie, refreshes, the data of each bit of the memory matrix 2 in order. As described above, by performing data refresh before data of each bit of the memory matrix is lost, data loss can be prevented.

[0006]

However, such a conventional semiconductor device has the following problems. In the above conventional example, the CPU 1 refreshes data of all bits at regular intervals. Here, in general, there is a relationship shown in FIG. 10 between the average failure rate relating to data retention of each bit and the usage environment temperature, and the average failure rate may rapidly increase when the temperature becomes about 110 to 120 ° C. or more. Are known. Therefore, in order to prevent the retention characteristics from deteriorating in a high temperature environment, it is necessary to refresh at shorter time intervals as the use environment temperature increases. In order to prevent data loss due to disturb or soft write, it is necessary to refresh at a time interval corresponding to a bias condition in which disturb or soft write is most likely to occur.

[0007] For the above reasons, as a first problem, if the time interval of refresh is shortened to prevent data loss, the number of times of refresh increases. Generally, the number of times data is written to a nonvolatile memory transistor is 1
It has been limited to about 0 ⁴ -10 ⁵ times. Therefore, in the conventional example, the number of times of refreshing becomes too large, and the nonvolatile memory transistor itself may be destroyed. That is, since the refresh interval according to the actual use state of the semiconductor device, that is, the refresh frequency is not set, the refresh becomes excessively frequent and the life of the semiconductor device is shortened.

Further, when the continuous application time of the power supply voltage to the semiconductor device is not permanent, as in the case of automobile use, and is generally assumed to be about several hours, the continuous application time of the power supply voltage must be within the continuous application time of the power supply voltage. The refresh must be performed at least once. As a result, the number of times of refresh is further increased, and the possibility of destruction of the semiconductor device is further increased.

As a second problem, there is an effect on the read operation of the CPU. In this conventional example, all bits are refreshed. Generally, however, the data write time of the nonvolatile memory transistor is long, and it takes several minutes for all bits. During the refresh, the CPU cannot read the data and perform the operation. Therefore, CPU
This has the significant adverse effect of suspending normal operation of for several minutes.

A third problem is that data loss cannot be completely prevented. In other words, when temperature or voltage stress is applied to the semiconductor device more suddenly than originally expected, or when a bit whose data retention characteristics are inferior to other bits due to a process defect or the like occurs, refresh is not performed. Data loss may occur before

The present invention has been made to solve the problems of the prior art as described above.
The first is to provide a semiconductor device capable of preventing a reduction in the life of a memory due to an excessive number of refreshes.
Third, to provide a semiconductor device capable of preventing data loss even when a more severe temperature and voltage stress than expected is applied. That is.

[0012]

Means for Solving the Problems In order to achieve the above object, the present invention is configured as described in the claims. That is, in the invention according to claim 1, in a semiconductor device having a plurality of memory transistors, the semiconductor device has the same basic structure as that of the memory transistor, and is configured so that stored data is more easily lost than the memory transistor. At least one test transistor is provided, and means for detecting that data stored in the test transistor has been lost and refreshing the memory data of the memory transistor and the test transistor is configured. . The above-described inspection transistor is formed so that stored data is easily lost structurally (for example, claim 2,
3, 10, 11) and the case of controlling the storage data to be easily lost (for example, claims 7 to 9 described later).

As described above, by providing the inspection transistor having the same structure as that of the memory transistor and configured so that the stored data is easily lost, the inspection transistor must be provided before the stored data of the memory transistor is lost. Will be lost. Therefore, if refreshing is performed at that time, the data stored in the memory transistor will not be lost, and the number of refreshes will be smaller than in the conventional example. Therefore, destruction of the semiconductor memory device due to an excessive number of refreshes can be prevented, and the life can be extended.

Further, since it is not necessary to check the data stored in each memory transistor, even if the memory capacity is large, the data check time does not adversely affect the CPU operation. Furthermore, since the basic structure of the test transistor and the memory transistor is the same, the mechanism of deterioration and loss of stored data is essentially the same. Then, when the storage data of the inspection transistor configured so that the storage data is easily deteriorated and lost is lost, that is, when the storage data of the memory transistor is still normal, the semiconductor storage device is more than expected. Even when severe and various temperature and voltage stresses are applied and the period of data deterioration and loss becomes shorter than expected, data loss of the memory transistor can be reliably prevented.

Next, the invention according to claim 2 shows a specific configuration example of a memory transistor and a test transistor, wherein the memory transistor is a non-volatile memory transistor and the test transistor is a non-volatile memory transistor. The insulating film is formed thinner than that.
With such a configuration, the retention characteristic can be reduced as described in detail in the embodiment below.
Stored data is easily lost. This configuration is
For example, it corresponds to the embodiment shown in FIG.

Next, the invention according to claim 3 shows another specific configuration example, and the inspection transistor comprises:
A portion having the same structure as the nonvolatile memory transistor, a portion having a first conductor layer corresponding to the control gate and a second conductor layer corresponding to the floating gate (acting as a simple capacitor),
The portion having the first and second conductor layers has a structure in which the insulating film is thinner than the portion of the insulating film having the same structure as the non-volatile memory transistor, or the first and second conductor layers have the control structure. The control gate and the first conductor layer, and the floating gate and the second conductor layer each have at least one of a gate and a structure having an area larger than the floating gate. It is configured to be connected to each other.

With this configuration, since the retention characteristic of the inspection transistor is determined by the first and second conductive layer portions, it is possible to provide a configuration in which stored data is easily lost. In addition, since the threshold voltage and gm of the inspection transistor have the same values as those of the non-volatile memory transistor, there is no need to take special measures for a read circuit such as a sense amplifier for reading stored data. Become. In addition, since many parts have the same structure, the manufacturing process may be easier. In addition, since the size of the conductor layer can be set without changing the transistor characteristics such as gm of the inspection transistor, the retention characteristics of the inspection transistor are surely shorter than the retention characteristics of the nonvolatile memory transistor. In addition, it becomes easy to control the time until the data of the inspection transistor disappears. Therefore, the design of the refresh period becomes easy, and data loss of the nonvolatile memory transistor can be reliably prevented. The above configuration corresponds to, for example, an embodiment shown in FIG. 5 described later.

Next, in the invention according to claim 4,
At least two test transistors are provided for each memory block or memory matrix, and a means is provided for controlling one of the transistors to be in a high threshold voltage state and the other to be in a low threshold state. With this configuration, the refresh operation can be reliably performed before the stored data is lost regardless of whether the stored data in the nonvolatile memory transistor is in the written state or the erased state.

Next, in the invention according to claim 5,
The configuration is such that the number of refreshes of the inspection transistor is detected, and when the number of refreshes reaches a predetermined value, the address of the memory block to which the inspection transistor belongs is assigned to an unused memory block. With this configuration, the destruction of the nonvolatile memory transistor itself due to an excessive number of refreshes can be further prevented.

Next, in the invention according to claim 6,
When it is detected that the storage data of the inspection transistor has been lost, after the arithmetic unit using the storage data of the memory transistor stops the normal operation, or before the normal operation is restarted after the operation is stopped once. , So that a refresh operation is performed. With this configuration, the original operation of the CPU (normal operation operation) is hardly obstructed.

Next, the inventions according to the seventh to eleventh aspects show configurations for accelerating the loss of data stored in the inspection transistor. The seventh aspect of the present invention relates to a floating gate of the inspection transistor. Controlling the amount of electron charge injected into the memory transistor to be smaller than that of the memory transistor, wherein a voltage of Vcc or more or a voltage of Vss or less is applied to the control gate of the inspection transistor in a steady or intermittent manner. Claim 9 applies the above voltage even when the operation of the semiconductor device is stopped or the power supply voltage is stopped. Claim 10 applies a high voltage pulse or a voltage higher than the Vcc voltage before use to insulate the semiconductor device. A device which causes a minute defect inside the film, wherein a step or irregularities are formed on the front surface or the back surface of the insulating film of the inspection transistor. That.

Each of the configurations of claims 7 to 9 shows a configuration in which the stored data of the inspection transistor is controlled so as to be easily lost, and the configurations of claims 10 and 11 are arranged so that the stored data is lost. This shows a configuration in which a test transistor is formed so as to be easy.

[0023]

According to the present invention, the following effects can be obtained. First, refresh is performed after data loss actually occurs in the test transistor, so that the number of refreshes is smaller than in the conventional example. Therefore, the semiconductor memory device itself can be prevented from being destroyed due to an excessive number of refreshes, and the life can be extended.

Second, since it is not necessary to check the storage data of the individual memory transistors in the memory matrix or the memory block, even if the memory capacity is large, the data check time may adversely affect the CPU operation. Disappears.

Third, the deterioration and erasure mechanisms of the storage data of the inspection transistor and the nonvolatile memory transistor are essentially the same, and the inspection transistor is formed so as to be easily deteriorated and lost. Since refresh is performed when the storage data loss of the inspection transistor is detected, that is, before the storage data of the non-volatile memory transistor is still lost, the semiconductor memory device is subjected to more severe and various temperature and voltage stresses than expected. Is applied, and even if the period of data deterioration and loss becomes shorter than expected, data loss of the nonvolatile memory transistor can be reliably prevented.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. 1 and 2 are views showing a first embodiment, FIG. 1 is a block diagram showing an overall configuration, and FIG. 2 is a cross-sectional view showing the structure of a nonvolatile memory transistor 110 and a test transistor 111. . First, the overall configuration will be described. In FIG. 1, a memory matrix 107 includes a plurality of memory blocks 100. Each memory block 100 has a plurality of nonvolatile memory transistors 110 for storing data as bits, and at least one or more test transistors 1
11 is provided. The above nonvolatile memory transistor 1
Numeral 10 has a floating gate surrounded by an insulating film as shown in FIG. 2, for example, and a high threshold voltage state and a low threshold voltage corresponding to the amount of electron charge in the floating gate. The data is stored depending on the voltage state.

The bit lines in the memory block 100 are connected to the write circuit 103 and the read circuit 104 via the column decoder 102, and the word lines in the memory block 100 are connected to the voltage generation circuit 108 via the row decoder 101. Connecting. Write circuit 1
03, the read circuit 104, the column decoder 102, the row decoder 101, and the voltage generation circuit 108
It is controlled by the control circuit 106. Also, the second storage device 10 provided separately from the memory matrix 107
5 is connected to the readout circuit 104 and the control circuit 106.

The bit line of the inspection transistor 111 is also connected to the write circuit 1 via the column decoder 102.
03 and the readout circuit 104, and the word line of the inspection transistor 111 is connected to the voltage generation circuit 108 via the row decoder 101.

Next, the structure of the nonvolatile memory transistor 110 and the inspection transistor 111 will be described with reference to FIG. FIG. 2A is a sectional view of a nonvolatile memory transistor 110, and FIG.
1 is a sectional view of FIG. First, the nonvolatile memory transistor shown in FIG. 2A has a first gate oxide film 113, a first floating gate 114, a first interlayer film 115, and a first control film formed on a semiconductor substrate 112. The gate 116 has a stacked structure. The first control gate 116 is connected to the voltage generation circuit 108 via the word line and the row decoder 101.

The test transistor shown in FIG. 2B has a second gate oxide film 117, a second floating gate 118, a second interlayer film 119, and a second gate oxide film 117 formed on a semiconductor substrate 112. Control gate 10
Nine laminated structures. The second control gate 109 is connected to the voltage generation circuit 108 via the word line and the row decoder 101. Note that the floating gate and the control gate are formed of a conductive material such as polycrystalline silicon.

As described above, the structure of the nonvolatile memory transistor 110 and the structure of the inspection transistor 111 are basically the same, but differ in the following points. In other words, the inspection transistor 111 has the second gate oxide film 117 thinner than the first gate oxide film 113 or the second interlayer film so that stored data is lost earlier than the nonvolatile memory transistor. 119 is made thinner than the first interlayer film 115, or a structure satisfying both of the above two conditions is adopted. For example, in FIG.
Thickness of first gate oxide film 117 <first gate oxide film 11
3 <thickness of second interlayer film 119 <first interlayer film 1
The thickness is set to 15.

Next, the operation will be described. Memory block 10
The function of newly writing or erasing data in each bit of 0 or the function of reading data of each bit is performed by the control circuit 106, the write circuit 103, and the read circuit 104. Since this part is a general operation, detailed description is omitted.

Here, the relationship between the data state of the nonvolatile memory transistors constituting the memory block 100 and the threshold voltage distribution is assumed to be the same as the relationship shown in FIG. That is, a state in which electrons are injected into the floating gate in the nonvolatile memory transistor to increase the threshold voltage is referred to as a write state, and a state in which electrons are removed from the floating gate and the threshold voltage is lowered is referred to as a state. Set to the erased state.

As described in the section of the conventional example, in the non-volatile memory transistor, the data stored in the non-volatile memory transistor is lost due to deterioration of the retention characteristic under a high temperature environment, disturb, soft write, and the like. It is easy to be. That is, the electrons injected into the floating gate escape to the surroundings, and the threshold voltage of the nonvolatile memory transistor in the high threshold voltage state decreases. Alternatively, electrons are injected into the floating gate, and the threshold voltage of the nonvolatile memory transistor that has been in the low threshold voltage state increases.

In this embodiment, focusing on the above points,
At least one or more test transistors are provided in a memory block, and data stored in the test transistors is erased earlier than data stored in non-volatile memory transistors constituting a proper memory block. Thus, before the data of the normal nonvolatile memory transistor is lost, the precursor of the loss is surely detected. By performing a refresh operation when data loss in the inspection transistor is detected, it is possible to reliably retain data stored in the normal nonvolatile memory transistor and prevent a reduction in life due to an excessive number of refreshes. I can do it. Also, by reducing the number of refreshes, while minimizing the effect on the normal operation of the CPU,
Data loss can be prevented.

Here, the cause of the data degradation is as follows:
It is generally known that, among the deterioration of retention characteristics, disturb, and soft write under a high temperature environment, the most problematic in data retention is the deterioration of the retention characteristics under a high temperature environment. In particular, when the maximum use environment temperature reaches 80 to 150 ° C. as in the case of automobiles, a significant problem occurs. What matters in retention is a memory transistor in a written state rather than an erased state.

Hereinafter, the above reason will be described with reference to FIG. FIG. 3 is a cross-sectional view for explaining an erased state (a) and a written state (b) in the nonvolatile memory transistor. In FIG. 3, when the power supply voltage is not applied, the semiconductor substrate 112 and the control gate 116
Are both at the GND potential. In the memory transistor in the erased state, since no electrons are injected into the floating gate 114, there is no excess charge. Accordingly, since there is no electric field from the floating gate 114 to the semiconductor substrate 112 or the control gate 114, the charge does not easily increase or decrease. On the other hand, in the memory transistor in the written state, since the floating gate 114 has the excess charge 120, the semiconductor substrate 112 and the control gate 116
, An electric field 121 is generated. Therefore, electrons in the control gate 114 may flow out.

Therefore, in this embodiment, data is written in advance to the inspection transistor 111, and the transistor 111 is set to the high threshold voltage state. Then, one of the test transistors 111 is selected by the row decoder 101 and the column decoder 102, and the voltage is applied to the word line of the test transistor from the voltage generating circuit 108 to a voltage lower than the high threshold voltage. The data stored in the transistor for use is read by the read circuit 104 constantly or intermittently. If the stored data is lost and the inspection transistor changes from the off state to the on state, it is determined that the storage data of other nonvolatile memory transistors in this memory block may be degraded. ,
The stored data is refreshed by the write circuit 103 and the read circuit 104. At this time, the storage data of the inspection transistor is also refreshed (rewritten to a predetermined state, for example, a high threshold voltage state). The above operation is performed on all the memory blocks 100 constituting the memory matrix 107.

Here, the reason why the present embodiment can reliably detect a precursor of data loss will be described. The retention characteristics of the individual nonvolatile memory transistors 110 are determined by the electron tunneling of the gate oxide film 113 and the interlayer film 115 and the Fren
It largely depends on the leakage current due to kel-Poole conduction and the degree of leakage current passing through defects or pinholes in the gate oxide film 113 or the interlayer film 115 (for example, “DATA
RETENTION IN EPROMS ”IRPS, pp238-243, 1980).
In the normal memory matrix 107, since the number of the nonvolatile memory transistors 110 is as large as several kbits to several Mbits, the leakage current caused by defects in the gate oxide film 113 and the interlayer film 115, pinholes and the like is reduced. It is extremely difficult to get rid of or to adjust to a certain level.

As a result, the retention characteristics of individual nonvolatile memory transistors vary greatly. However, a semiconductor memory device having a non-volatile memory transistor having extremely poor retention characteristics can be removed by screening and not practically used. Therefore, as shown in the range of FIG. 4A, it is possible to make the retention characteristics of the nonvolatile memory transistor more than a certain level.

It is generally known that the thinner the gate oxide film or interlayer film, the more noticeable the leak current due to the electron tunneling or Frenkel-Poole conduction described above. The reason will be described below. First, the magnitude of the electric field applied to the gate oxide film and the interlayer film will be described with reference to the equivalent circuit shown in FIG. 3A, the floating gate 114 and the semiconductor substrate 112 form a capacitor 150 using the gate oxide film 113 provided therebetween as a dielectric, and the control gate 116 and the floating gate 114 are provided therebetween. A capacitor 151 is formed using the interlayer film 115 as a dielectric, and both are connected in series. And C ₁ is the capacitance of the capacitor 0.99, C ₂ is the capacitance of the capacitor 151.

In the above structure, the potential of the control gate 116 is represented by V _CG , the potential of the floating gate 114 is represented by V _FG, and the capacitance coupling ratio r is defined by the following equation (1). r = C ₁ / (C ₁ + C ₂ ) (Equation 1) Further, the electronic charge Q (<
Assuming that a change in the threshold voltage caused by the accumulation of 0) is ΔV _th , the following equation (2) is established by the charge neutral condition regarding the floating gate 114.

V _FG = r [V _CG + (Q / C ₂ )] (Equation 2) From the above (Equation 2), the following (Equation 3) is obtained. Q = -C ₂ · ΔV _th ( _Equation 3) Accordingly, the thickness of the gate oxide film 113 is applied to t _ox , the magnitude of the applied electric field is E _ox , and the thickness of the interlayer film 115 is applied to t _pp . Assuming that the magnitude of the electric field is E _pp , when V _CG = 0, the following equation (Equation 4) is satisfied, so that E _pp and E _ox
Is represented by the following (Equation 5) and (Equation 6).

V _FG = r (Q / C ₂ ) <0 (Equation 4) E _pp = r┃Q / C ₂ ┃ / t _pp = r (ΔV _th / t _pp ) (Equation 5) E _ox = r┃Q / C ₂ ┃ / t _ox = r (ΔV _th / t _ox ) (Formula 6) From the above formulas (5) and (6), if the value of t _ox or t _pp becomes smaller, E _pp and E _ox increase. It is known that the electron current J due to electron tunneling or Frenkel-Poole conduction has a strong electric field dependence (for example, SMSze
"Physics of Semiconductor Devices", published by Wiley P4
03, see).

The above-described electric field dependence is expressed by the following equation (Formula 7). J = f (E) (Expression 7) where f (E) indicates an increasing function of the electric field E.

As described above, when the value of t _ox or t _pp decreases, the strength of the electric field E _pp or E _ox increases.
From the equation, the electron current J increases. For this reason, the value of the electron charge Q stored in the floating gate 114 decreases, and ΔV _th decreases according to the equation (3), and the data stored in the memory transistor is lost. Further, the time until the stored data is lost can be designed by analyzing the contents of Expression (7). Although the above description has been made with respect to the nonvolatile memory transistor 110, the same holds true for the inspection transistor 111 having the same structure.

The test transistors 111 occupy a small area in the memory matrix 107 and have a small number.
In many cases, there is no leak due to defects or pinholes in the gate oxide film 117 or the interlayer film 119, or even if there is a leak, the inspection transistor 1 having the leak
By removing the memory having 11 by screening, it is possible to eliminate only the memory having no leak and to deteriorate the retention characteristic of the inspection transistor 111 with good controllability as described above. Therefore, as shown in the range of FIG.
11 is lower than the retention characteristic (a) of the nonvolatile memory transistor 110, and
It is possible to align within a certain width. That is,
The design can be made such that the data stored in the test transistor 111 is lost before the nonvolatile memory transistor 110.

As described above, in the present embodiment, (1) the storage data of the inspection transistor 111 actually disappears, and thus the nonvolatile memory transistor 110
When the data stored in the nonvolatile memory transistor 110 is in a state where it is highly likely that the stored data has also deteriorated (has not yet been lost), the data in the nonvolatile memory transistor 110 is refreshed. Can be done. Therefore, it is possible to prevent the semiconductor memory device itself from being destroyed (reduced in life) due to an excessive number of refreshes.

(2) Since it is not necessary to inspect the storage data of the individual nonvolatile memory transistors in the memory matrix or the memory block, even if the memory capacity is large, the data inspection time adversely affects the CPU operation. There is no.

(3) The deterioration and erasure mechanisms of the storage data of the inspection transistor 111 and the nonvolatile memory transistor 110 are essentially the same, and the inspection transistor 111 is formed so as to be more easily deteriorated and lost. When the loss of the stored data in the inspection transistor 111 is detected, the stored data in the nonvolatile memory transistor 110 is refreshed. Therefore, severer than expected and various temperature and voltage stresses are applied to the semiconductor memory device, Even when the cycle of deterioration and loss of the nonvolatile memory transistor becomes shorter than expected, data loss of the nonvolatile memory transistor 110 can be reliably prevented.

Next, a second embodiment of the present invention will be described. FIG. 5 is a cross-sectional view illustrating the structure of the inspection transistor according to the second embodiment.

In FIG. 5, on a semiconductor substrate 112,
A portion of a nonvolatile memory transistor in which a first gate oxide film 113, a third floating gate 201, a first interlayer film 115, and a third control gate 200 are stacked; a second insulating film 205; Conductor layer 20
4, a portion where the first insulating film 203 and the first conductor layer 202 are laminated is formed, and the third control gate 200, the first conductor layer 202, and the third floating gate 201 are formed. And the second conductor layer 204 are electrically connected. Note that the above conductor layer 20
2, 204 can be formed of, for example, the same polycrystalline silicon or aluminum layer as the floating gate and control gate. Then, the second insulating film 205 is thinner than the first gate oxide film 113 and the first insulating film 203 is formed.
Is formed thinner than the first interlayer film 115, or the area of the first and second conductor layers 202 and 204 is reduced to the third control gate 200 and the third floating gate 2
01 is formed to be larger than the area. Or do both of the above. In FIG. 5, the thickness of the second insulating film 205 is smaller than the thickness of the first gate oxide film 113, and the thickness of the first insulating film 203 is smaller than the thickness of the first interlayer film 115. It shows the case where it is done. The whole of FIG. 5 constitutes the inspection transistor 206.

In the above configuration, the first and second insulating films are thin or the first and second conductor layers are formed to have a large area. For that reason, the retention characteristics of that part are shortened,
In addition, since the third control gate 200 and the first conductive layer 202 and the third floating gate 201 and the second conductive layer 204 are electrically connected, the entire inspection transistor 206 is eventually formed. Is determined by the portions of the first and second insulating films and the first and second conductor layers. Therefore, with the configuration described above, the same operation and effect as those described in the first embodiment can be obtained.

This embodiment has the following features. (1) The gate oxide film 113 and the interlayer film 115 of the inspection transistor 206 shown in FIG. 5 are the same as the gate oxide film 11 of the nonvolatile memory transistor 110 shown in FIG.
3 and the interlayer film 115, and can be formed in the same step. Therefore, the threshold voltage and gm of the nonvolatile memory transistor in the inspection transistor 206
Are respectively the nonvolatile memory transistors 110 of FIG.
And the same value as gm. Therefore, there is no need to take special measures for a read circuit such as a sense amplifier for reading stored data, and the read circuit 104 of the nonvolatile memory transistor 110 may have the same circuit configuration. Therefore, the circuit configuration becomes easy.

(2) The insulating films 203 and 205 have the same film quality or ONO as the gate oxide film 113 and the interlayer film 115.
A film or the like may be used, and no special process is required. Therefore, the manufacturing process may be easier than in the first embodiment.

(3) Nonvolatile memory transistor 110
Irrespective of the structure of the conductive layers 202, 205 without changing the transistor characteristics such as gm of the inspection transistor 206, the thickness of the insulating films 203, 205 can be set.
04 size can be set. For this reason, the retention characteristics of the test transistor described in the first embodiment are reliably made shorter than the retention characteristics of the nonvolatile memory transistor 110, and the test transistor 2
It becomes easy to control the time until the 06 data is lost. Therefore, the design of the refresh period is facilitated, and data loss of the nonvolatile memory transistor 110 can be reliably prevented.

Next, a third embodiment of the present invention will be described. FIG. 6 is a block diagram showing a third embodiment of the present invention. The configuration shown in FIG. 6 is different from the configuration shown in FIG.
0, and the other parts are the same. In FIG. 1, the structure of the nonvolatile memory transistor 110 and the structure of the inspection transistor 111 are different, but in FIG.
The structure of the test transistor 300 is basically the same as that of the test transistor 10 except that the retention characteristic of the test transistor 300 is shortened in terms of a circuit. As will be described later, the retention characteristics can be changed by slightly changing the structure.

The operation of the third embodiment will be described below.

FIG. 7 shows a nonvolatile memory transistor 11
0 is a diagram showing the structure of the test transistor 300 and 0,
(A) is a cross-sectional view of the nonvolatile memory transistor 110,
(B) is a sectional view of the inspection transistor 300. In FIG. 7, the first gate oxide film 113 and the gate oxide film 301 are formed simultaneously in one manufacturing process and have the same thickness. Similarly, the first interlayer film 115 and the interlayer film 303
Are also formed at the same time and have the same thickness. Also, 30
2 is a floating gate and 304 is a control gate. The control gate 304 is connected to the voltage generation circuit 108 via the word line and the row decoder 101.

As described above, since the structure of the nonvolatile memory transistor 110 and the structure of the inspection transistor 300 are the same, the retention characteristics are the same as they are, and
The data stored in the test transistor 300 cannot be lost quickly. Therefore, in the present embodiment, control such as one of the following (1) to (3) or a combination thereof is performed.

(1) In the write state, the amount of electron charges injected into the floating gate 302 of the test transistor 300 is
Is smaller than the amount of electron charges injected into the floating gate 114, and the width of change in the threshold voltage during data writing is reduced.

(2) A voltage is applied between the control gate 304 and the semiconductor substrate 112 constantly or intermittently.

(3) In the above (2), the voltage applied to the control gate 304 is equal to or higher than the Vcc potential, or
Make it less than ss potential. This voltage application is performed only during normal operation or when no voltage is applied to the semiconductor memory device. Vcc is the power supply voltage on the high voltage side, Vss
Is the power supply voltage on the low voltage side.

The operation when the above control is performed will be described. First, in the case of (1), the threshold voltage in the written state is lower in the inspection transistor 300 than in the nonvolatile memory transistor 110. Therefore, the data stored in the inspection transistor 300 is inverted with less outflow of electrons from the floating gate 302. Therefore, the retention characteristic of the inspection transistor can be shortened, and the same effect as in the first embodiment can be obtained.

Next, the cases (2) and (3) will be described. As shown in the equation (7) in the first embodiment, the magnitude J of the electron current inside the gate oxide film 301 and the interlayer film 303 is a function of increasing the electric field E.

Here, the value of V _FG at the time of V _CG = 0 [V] is represented as V _FG0, and is defined as the following equation (8) by the above equations (2) and (3). .

V _FG0 = r · Q / C ₂ = −r · ΔV _th ( _Equation 8) Accordingly, the magnitude of the electric field when V _CG ≠ 0 [V] is equal to The following expression (Expression 9) is obtained from the expression, and the following expression (Expression 10) is obtained for the floating gate 302.

(V _CG −V _FG ) / t _pp = [(1−r) V _CG −V _FG0 ] / t _pp ( _Equation 9) where t _{pp is} the thickness of the interlayer film 303 V _FG / t _ox = ( _{RV CG} + V _FG0 ) / t _ox ( _Equation 10) where t _{ox is} the thickness of the gate oxide film 301. From the above (Equation 9), if a voltage of about V _CG = Vcc is obtained,
The electric field applied to the gate oxide film 301 and the interlayer film 303 is larger than the electric field when V _CG = 0 [V]. Therefore, the electrons in the floating gate 302 disappear faster, and the retention is shortened. When a voltage equal to or higher than Vcc is applied, the retention is further shortened. Also,
The same effect can be obtained by applying a voltage equal to or lower than Vss.

Further, when the power supply voltage is not applied to the semiconductor memory device, for example, in the case of an automobile, the voltage is continuously applied to the control gate 304 even when the ignition switch is turned off. Then, the loss of electrons in the floating gate 302 can be always accelerated. Therefore, even when the retention of the non-volatile memory transistor is short, such as when parking in the hot sun, the retention of the inspection transistor 300 can be always shorter than the retention of the non-volatile memory transistor 110.

The above-described voltage application and the like are performed by the control circuit 106 and the voltage generation circuit 108. Further, the above-described effect is obtained even when the voltage is not applied constantly but intermittently.

As described above, even if the structure of the non-volatile memory transistor 110 and the structure of the test transistor 300 are the same, the retention characteristics of the test transistor 300 can be configured to be shortened in terms of a circuit.

Further, as described in the following (4) and (5), the retention can be shortened by partially changing the structure of the inspection transistor 300. (4) By applying a high voltage pulse or a voltage higher than the Vcc potential in advance between the control gate 304 and the semiconductor substrate 112, the gate oxide film 301, the interlayer film 30
A microdefect is generated inside 3 or electrons are injected, and then the inspection transistor 300 is set to a written state or an erased state. With this configuration, a leak path of electrons accumulated in the floating gate 302 is formed inside the gate oxide film 301 and the interlayer film 303, so that the speed at which the electron charges in the floating gate 302 disappear is increased. Therefore, the retention characteristic of the inspection transistor can be shortened, and the same effect as in the first embodiment can be obtained.

(5) Gate oxide film 301 or interlayer film 3
Steps or irregularities are formed on the front surface or the back surface of at least one of the films 03. It is generally known that with the above-described configuration, stress concentrates on the formed step or uneven portion, so that a minute defect is likely to occur in that portion. Then, the minute defect becomes a leak path of the electrons in the floating gate 302, so that the elimination speed of the electron charges in the floating gate 302 is increased. Therefore, the retention characteristics of the inspection transistor 300 can be shortened, and the same effect as described above can be obtained.

In the above (1) to (5), by adjusting the amount of electron charge, the amount of minute defects or injected electrons, the applied voltage, or the level of the step, the inspection transistor 30 is adjusted.
The time until the stored data of 0 disappears can be controlled.

As described above, the same effects as those of the first embodiment can be obtained in the third embodiment, but the basic structure of the inspection transistor 300 is the same as that of the nonvolatile memory transistor 110. It can be manufactured in the same semiconductor manufacturing process. Therefore, there is an advantage that the manufacturing process is not complicated, and an increase in manufacturing cost can be suppressed.

The structure of the inspection transistors 111 and 206 in the first and second embodiments is the same as the structure in which at least one or some of (1) to (5) in the third embodiment is combined. In this case, since the operation described in the third embodiment is added, the design of the refresh period is further facilitated, and the nonvolatile memory transistor 1
10 can be reliably prevented from being lost, and the life of the semiconductor memory device can be extended.

Further, in the first to third embodiments, the following configuration can be adopted. (1) Inspection transistor 111, 206 or 300
Are provided in the memory block 100 or the memory matrix 107, and when one is in the writing state, the other is in the erasing state. According to this configuration, refreshing can be reliably performed before the stored data is lost regardless of whether the stored data in the nonvolatile memory transistor 110 is in the written state or the erased state.

(2) Inspection transistors 111 and 206
Alternatively, when the number of refreshes of 300 reaches the first predetermined value, the inspection transistors 111, 206, or 3
The address of the memory block 100 to which 00 belongs is assigned to an unused memory block. According to this configuration, destruction of the nonvolatile memory transistor 110 itself due to an excessive number of refreshes can be further prevented.

(3) The refresh operation is performed after the original operation of the CPU is stopped, or the refresh operation is performed when a power supply voltage is applied to the semiconductor memory device, and then the original operation of the CPU is started. With such a configuration, the original operation of the CPU is hardly obstructed.

When the above-described configurations (1) to (3) are combined, the same effects can be obtained.

In the above description, the high threshold voltage state of the nonvolatile memory transistor is the write state,
Although the low threshold state has been described as the erased state, the same applies to the case where the opposite state is set.

Similar effects can be obtained even when the nonvolatile memory transistor is a flash memory, an EEPROM, or an EPROM.

If the function of control circuit 106 is configured to be performed by a CPU that reads data from the semiconductor storage device, the configuration of the semiconductor storage device can be simplified.

If the semiconductor memory device and the CPU are formed on the same semiconductor substrate, the number of wires between the semiconductor memory device and the CPU can be increased without being restricted by a package or the like, and the degree of freedom of the circuit configuration can be increased. Can be improved.

Further, in the embodiment of the present invention described above, the conventional ECC circuit (Error Checking a
nd Correcting circuit) has the following effects. First, the ECC circuit can correct only one bit error in one word or one byte, but in the case of the present embodiment, there is no such restriction, and failure can be reliably prevented.

Second, the ECC circuit requires a memory matrix having parity bits composed of a plurality of bits in addition to the original memory matrix. Therefore, the size of the storage device is increased by 30 to 50%, and the integration degree of the storage device is significantly impaired. On the other hand, in the embodiment of the present invention, the area of the additional circuit is much smaller than the area of the memory matrix itself, and the integration degree of the semiconductor memory device is hardly impaired.

Third, since the ECC circuit has a bit error correction circuit, the access time increases when reading data. In the embodiment of the present invention, there is no increase in the access time at the time of reading data, and the normal operation of the CPU is not adversely affected.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a structure of a nonvolatile memory transistor 110 and a test transistor 111.

FIG. 3 is a cross-sectional view illustrating a state in which data stored in a nonvolatile memory transistor is in a write state (high threshold voltage state) and an erase state (low threshold voltage state).

FIG. 4 is a diagram showing distribution of retention characteristics of a nonvolatile memory transistor and a test transistor.

FIG. 5 is a cross-sectional view illustrating a structure of a test transistor 206 used in a second embodiment of the present invention.

FIG. 6 is a block diagram showing a third embodiment of the present invention.

FIG. 7 is a cross-sectional view illustrating the structures of a nonvolatile memory transistor 110 and an inspection transistor 300.

FIG. 8 is a block diagram of an example of a conventional device.

FIG. 9 is a diagram showing threshold voltages of memory transistors in a write state and an erase state of a flash memory.

FIG. 10 is a characteristic diagram showing a relationship between a temperature and an average failure rate in a semiconductor memory device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... CPU 2 ... Memory matrix 3 ... Timer 4 ... Write circuit including a control circuit 100 ... Memory block 101 ... Row decoder 102 ... Column decoder 103 ... Write circuit 104 ... Read circuit 105 ... Second storage device 106 ... Control circuit 107 ··· Memory matrix 108 ··· Voltage generating circuit 109 ··· Second control gate 110 ··· Nonvolatile memory transistor 111 ··· Test transistor 112 ··· Semiconductor substrate 113 ··· First gate oxide film 114 ··· First floating gate 115 ··· First Interlayer film 116 First control gate 117 Second gate oxide film 118 Second floating gate 119 Second interlayer film 120 Surplus charge 121 Electric fields 150 and 151 Capacitor 200 Third control gate 201: third floating gate 202: first conductive layer 203: first insulating film 204: second conductive layer 205: second insulating film 206: test transistor 300: test transistor

Claims (11)

[Claims] 1. A semiconductor device having a plurality of memory transistors, wherein at least one test transistor has the same basic structure as the memory transistor and is configured so that stored data is more easily lost than the memory transistor. And a means for detecting that the storage data of the inspection transistor has been lost and refreshing the storage data of the memory transistor and the inspection transistor. 2. The memory transistor according to claim 1, wherein said memory transistor is a nonvolatile memory transistor having a floating gate surrounded by an insulating film, wherein said memory transistor has a high threshold voltage state corresponding to the amount of electronic charge in said floating gate. And a low threshold voltage state for storing data, and forming a semiconductor memory device by a memory block having a plurality of the nonvolatile memory transistors as respective bits or a memory matrix including a plurality of memory blocks. The inspection transistor has the same basic structure as the non-volatile memory transistor, and the insulating film is formed thinner than the non-volatile memory transistor. , At least one of which is provided. 2. The semiconductor device according to claim 1, wherein: 3. The non-volatile memory transistor according to claim 1, wherein said memory transistor is a nonvolatile memory transistor having a floating gate and a control gate surrounded by an insulating film. A semiconductor memory device for storing data according to a threshold voltage state and a low threshold voltage state, and comprising a memory block having a plurality of nonvolatile memory transistors for each bit or a memory matrix including a plurality of memory blocks. Wherein the inspection transistor has a portion having the same structure as the nonvolatile memory transistor, a first conductor layer corresponding to the control gate, and a second conductor layer corresponding to the floating gate. And a portion having
The portion having the first and second conductor layers has a structure in which the insulating film is thinner than the portion of the insulating film having the same structure as the nonvolatile memory transistor, or the first and second conductor layers have the control structure. The control gate and the first conductor layer, and the floating gate and the second conductor layer each have at least one of a gate and a structure having an area larger than the floating gate. The semiconductor device according to claim 1, wherein the semiconductor device is electrically connected. 4. A means for providing at least two test transistors for each memory block or memory matrix, wherein one of the transistors is in a high threshold voltage state and the other is in a low threshold state. 4. The semiconductor device according to claim 1, wherein: 5. A means for detecting the number of refreshes of the test transistor, wherein when the number of refreshes reaches a predetermined value, an address of a memory block to which the test transistor belongs is assigned to an unused memory block. The semiconductor device according to claim 1, further comprising: allocating means. 6. When an operation device using the storage data of the memory transistor stops normal operation or once stops operation after detecting that the storage data of the inspection transistor has been lost, the operation device may be restarted. 6. The semiconductor device according to claim 1, further comprising means for performing said refresh operation before starting a normal operation. 7. A means for controlling the amount of electron charge injected into the floating gate of the inspection transistor in the high threshold voltage state to be smaller than the amount of electron charge injected into the floating gate of the nonvolatile memory transistor. The semiconductor device according to claim 1, further comprising: 8. The method according to claim 1, further comprising means for applying a voltage of Vcc or more or a voltage of Vss or less to the control gate of the inspection transistor, either constantly or intermittently. The semiconductor device according to any one of the above. 9. The semiconductor device according to claim 8, wherein the voltage is applied even when the operation of the semiconductor device is stopped or when the supply of the power supply voltage to the semiconductor device is stopped. . 10. A high-voltage pulse or a voltage not lower than Vcc voltage is applied between the control gate of the inspection transistor and the substrate before the semiconductor device is put into practical use so as to generate minute defects inside the insulating film. 10. The semiconductor device according to claim 1, wherein the semiconductor device is configured as follows. 11. The semiconductor device according to claim 1, wherein a step or unevenness is formed on a front surface or a back surface of the insulating film of the inspection transistor.