JPH10145670A - Electronic image pickup device with flicker correction function - Google Patents

Abstract

PROBLEM TO BE SOLVED: To conduct flicker correction properly corresponding to even an image pickup signal that is obtained under the occurrence of a large change in a storage time for each field. SOLUTION: An integration device 102 integrates an image pickup signal at an input terminal in the unit of one image to obtain a mean luminance signal in the unit of patterns. Delay devices 103-107 delay sequentially the image mean luminance signal in the unit of one pattern to obtain a pattern mean luminance signal from a plurality of image patterns. A computing element 108 adds three pattern mean luminance signals corresponding to a time apart by two image patterns to obtain a numerator signal. A computing element 109 obtains a denominator signal that is thrice of one pattern mean luminance signal. A divider 110 divides the denominator signal by the numerator signal to obtain a correction signal. The correction signal is given to a delay device 111, in which the time is adjusted and the result is multiplied with an image pickup signal received at the input terminal to correct flickers.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic image pickup apparatus having a flicker correction function, and more particularly, to an improved flicker correction function.

[0002]

2. Description of the Related Art A solid-state imaging device used as a video camera or an electronic still camera can be roughly divided into an optical system for introducing an optical image from a subject, a solid-state imaging device for forming a subject image from the optical system, It comprises a drive circuit for driving the solid-state image sensor, and a signal processor for converting an image signal read from the solid-state image sensor into a video signal of a desired broadcast system.

In general, the broadcasting system is often set in accordance with the frame frequency or the field frequency with the commercial power frequency. For example, in the NTSC system adopted in a region where the commercial power frequency is 60 Hz, the field frequency is 60 Hz, and the commercial power frequency is 50 Hz.
In many cases, the PAL system adopted in the region has a field frequency of 50 Hz.

However, the frequency of the commercial power supply (50 Hz) and the field frequency (60 Hz) may be different in some areas, such as the eastern Japan area. In such an area, flickering occurs when an image is taken by a video camera under blinking illumination such as a fluorescent light.

FIG. 7 shows the cause of flicker. Now, there is a lighting that periodically emits light from commercial power,
It is assumed that the light emission cycle is 1/100 (second) (FIG. 7 (7A)). On the other hand, if the field frequency is 1
Assume that charge accumulation (imaging) is performed by a video camera using a solid-state imaging device of / 60 (seconds). In such a case, due to the difference between the light emission cycle and the accumulation cycle, the charge accumulation amount changes between fields, and the brightness of the screen varies (flicker) (FIG. 7 (7B)). (1/100) × 5 = between the above light emission cycle and field cycle
There is a relationship of (1/60) × 3 = 1/20, and the change of flicker is called 20 Hz flicker which makes one cycle in three fields. At this frequency, the blinking speed is slow, so that it is sufficiently visible.

[0006] Recent solid-state imaging devices have a charge accumulation time variable function called an electronic shutter. In this function, first, a charge sweep pulse is given to the solid-state imaging device, the charge accumulated so far is once discarded, charge accumulation (exposure) for a set shutter time is performed, and the charge accumulated during this shutter time. This is to extract electric charge.
Therefore, this accumulation time is set to the previous light emission cycle (1/100 second)
By adjusting to, flicker can be suppressed.

On the other hand, a camera utilizing the electronic shutter function as a lens aperture function has been developed. That is, the accumulation time varies depending on the subject (1/60 to 1 / tens of thousands of seconds). In the case of a camera having such a function, flicker occurs due to the accumulation time that changes due to the aperture.

Further, as an electronic camera, a camera that obtains a video signal having a large dynamic range from a video of two fields by greatly changing an accumulation time for each field has been developed. Assuming that the low shutter speed is 1/100 second, flicker is generated for an image signal by the high shutter.

That is, as shown in FIGS. 8 (A) and 8 (B), flicker does not occur for imaging signals B, D and F by a 1/100 second low-speed shutter, but a high-speed shutter does. Flicker has occurred for the imaging signals A, C, and E.

FIG. 9 shows a conventional flicker correction circuit.
An imaging signal from a solid-state imaging device is supplied to the input terminal 11. The imaging signal (digitized) at the input terminal 11 is supplied to the one vertical period integrator 12 and the multiplier 21. The average luminance signal obtained from one vertical period integrator 12 is sequentially input to delay units (shift registers) 13, 14, and 15. The outputs of the delay units 13 and 14 are added by an adder 16, and the added output is input to an adder 17 and added to the output of the register 15. Thus, an average luminance signal for three fields is obtained and input to the divider 19. The output of the adder 18 for adding the output of the delay unit 14 for three fields is input to the divider 19.

Assuming that the outputs of the delay units 13, 14, and 15 are C, B, and A, the divider 19 calculates (A + B + C) /
The operation of 3B is performed. The output kB of the divider 19 is
It is input to the delay unit 20 for timing adjustment. The output of the delay unit 20 is input to the multiplier 21 and is multiplied by the input signal as a flicker correction value.

The input imaging signal described above has a frequency of 20 Hz.
Assuming that flicker has occurred, this 20 Hz flicker makes one cycle in three fields. Therefore, if the average luminance signal of one field is added for three fields, it should be constant. This sum is the numerator. And
By multiplying the average luminance signal in each field by 3, multiplying the average luminance signal by the denominator and performing division, it is possible to sequentially obtain correction values for each field.

[0013]

As described above, as a method for eliminating flicker, there are a method of adjusting the charge accumulation time of the solid-state imaging device to a light emission cycle (1/100 second) of illumination, and a method of eliminating the above-mentioned flicker correction circuit. There is a method of providing.

However, the method of adjusting the charge accumulation time to the light emission cycle of the illumination in any case has the problem that the sensitivity is reduced and the shutter speed is fixed because the light emission cycle is adjusted in any case. There is also a problem that the aperture function using an electronic shutter cannot be used.

Next, the method of providing the flicker correction circuit has a problem that it cannot cope with a case where the charge accumulation time greatly changes for each field. That is, 1
Since there is a large difference in the level of the average luminance signal for the field, the correction signal resulting from the division may not be appropriate. Further, a divider is required, and the circuit scale becomes large.

It is therefore an object of the present invention to provide an electronic image pickup apparatus having a flicker correction circuit capable of appropriately coping with an image pickup signal obtained by greatly changing an accumulation time for each field.

Another object of the present invention is to provide an electronic image pickup apparatus having a flicker correction circuit having a small circuit scale. It is another object of the present invention to provide an electronic imaging apparatus having a flicker correction circuit which can appropriately cope with an imaging signal obtained by greatly changing an accumulation time for each field and has a small circuit scale. It is in.

[0018]

According to the present invention, an input terminal to which an imaging signal obtained from a solid-state imaging device is input, and an imaging signal of the input terminal are integrated for each screen, and an average luminance signal for each screen is obtained. An integrating means for obtaining, a delay means for sequentially delaying the screen average luminance signal by one screen unit to obtain a screen average luminance signal for a plurality of M (≧ 5) screens, and a plurality of screens obtained from the delay means A first calculating means for deriving and adding N (3 ≦ N <M) screen average luminance signals corresponding to a time separated by two screens out of the screen average luminance signals for two minutes to obtain a numerator signal; Second calculating means for obtaining a denominator signal obtained by multiplying one of the screen average luminance signals by N.

Then, the denominator signal is divided by the numerator signal,
A division unit that uses the result as a correction signal; and a multiplication unit that multiplies the imaging signal input to the input terminal by the correction signal obtained by the division unit.

By the above means, an appropriate flicker correction can be performed even for an image pickup signal obtained by, for example, a 20 Hz flicker and having an accumulation time greatly changed for each field. This is because calculation processing of a correction signal for a signal corresponding to the accumulation time is performed.

According to the present invention, there is provided an input terminal to which an image pickup signal obtained from a solid-state image pickup device is inputted, and an integrating means for integrating the image pickup signal of the input terminal for each screen to obtain an average luminance signal for each screen. Delay means for sequentially delaying the screen average luminance signal by one screen unit to obtain a screen average luminance signal for three screens, and a screen average luminance signal for three screens obtained from the delay means; The image processing apparatus includes a first arithmetic unit for obtaining a first comparison signal and a second arithmetic unit for obtaining a triple signal obtained by triple one of the three screen average luminance signals.

A high-speed counter that counts one or more rounds during one screen period; first multiplication means for multiplying the output of the high-speed counter by the triple signal to obtain a second comparison signal; Comparison and latch means for comparing the value of the comparison signal with the value of the second comparison signal, and latching the output of the high-speed counter when the value of the second comparison signal exceeds the value of the first comparison signal And second multiplying means for time-adjusting the latch output obtained from the comparing and latching means and multiplying the image signal of the input terminal. By the above means, a divider is not required and can be realized with a small-scale circuit configuration.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows an embodiment of the present invention. To the input terminal 101, an imaging signal which is captured by a solid-state imaging device and includes flicker is input. This imaging signal is assumed to be digitized.

This image signal is supplied to one vertical period integrator 10.
2. It is supplied to the multiplier 112. 1 vertical period integrator 10
The average luminance signal for one screen obtained from the second unit is a delay unit (shift register) 103, 104, 105, 106, 10
7 are sequentially input. Each delay device 103, 104, 10
5, 106 and 107 delay the input signal by one field period.

The output of the delay units 103, 105, and 107, that is, the time corresponding to one screen-separated time among the screen average luminance signals for a plurality of screens obtained from the delay units 103, 104, 105, 106, and 107 N (3 in this case) of the screen average luminance signals to be obtained are derived and input to the first computing unit 108. The first arithmetic unit 108 adds and outputs the input screen average luminance signal. This first computing unit 108
Is a molecular signal.

The screen average luminance signal output from the delay unit 105, that is, one of the plurality of average luminance signals
One is input to the arithmetic unit 109 and tripled. This 3
The doubled signal is used as a denominator signal.

The numerator signal and the denominator signal are divided by a divider 1
At 10 the numerator signal is divided by the denominator signal. Then, the result of division obtained by the divider 110 is input to the delay unit 111 for timing adjustment as a correction signal. The output of the delay unit 111 is input to the multiplier 21 and is multiplied by the input signal. An image signal from which flicker has been removed can be obtained from the output terminal 113.

FIG. 2 shows an example of signal waveforms for explaining the operation of the above circuit. FIG. 2 (2A) shows the amount of illumination light with a light emission cycle of 1/100 second, and FIG. 2 (2B) shows an image signal captured under this illumination environment.
This imaging signal has a charge accumulation time of 1/100 second and 1/4
This is an image pickup signal obtained by switching and imaging every field at 00 seconds and expanding the dynamic range.

As can be seen from the image pickup signal shown in FIG. 2B, the signal to be obtained by the correction circuit for obtaining a correction signal is a screen average luminance signal for three screens corresponding to the charge accumulation time. That is, correction signals are separately created for the group of signals A, C, E, G,... And the group of signals B, D, F, H,. In other words, a flicker correction signal is obtained for each group of screen average luminance signals having the same charge accumulation time. As a result, an appropriate flicker correction signal can be obtained for the signal for each screen.

If it is assumed that a 20 Hz flicker has occurred in the input image signal, the 20 Hz flicker has made one cycle in three fields, so that it can be regarded as having made one cycle in six fields. Therefore, the first computing unit 10
The addition output (A + C + E) of 8 can be regarded as a constant value at which flicker does not appear. On the other hand, 3C is obtained from the second computing unit 109. In the divider 110, (A + C + E) /
The operation of 3C is performed to obtain a correction signal.

Now, it is assumed that the imaging signal input to the input terminal 101 is a signal of the cycle of the signal F, and the correction signal output from the delay unit 111 is nF. This correction signal is obtained from the calculation of nF = (B + D + F) / 3F. Here, the result calculated by the multiplier 112 is F × nF = F × (B + D + F) / 3F = (B + D +
F) / 3 = constant value, and the flicker component has been removed.

FIG. 3 shows another embodiment of the present invention.
To the input terminal 201, an imaging signal which is captured by the solid-state imaging device and includes flicker is input. This imaging signal is assumed to be digitized.

This image signal is supplied to one vertical period integrator 20.
2, is supplied to the multiplier 213. 1 vertical period integrator 20
2 are sequentially input to delay units (shift registers) 203, 204, and 205. Each of the delay units 203, 204, and 205 delays the input signal by one field period. The output of the delay unit 203 and the output of the delay unit 204 are added by an adder 206, and the output of the adder 206 is added by an adder 207 to the output of the delay unit 205.

The output of the adder 207 is input to one of the comparators 210. The output of the delay unit 203 is
At 8, it is tripled. The output of the adder 208 is multiplied by a count value, which will be described later, in a multiplier 209 and output, and is supplied to the other side of the comparator 210.

The comparator 210 compares the two inputs, and outputs a low level “L” or a high level “H” according to the result of the comparison.
Is obtained. For example, the output of the adder 207 (A + B +
C) is compared with the output of the multiplier 290 (n × 3B).
When (n × 3B) <(A + B + C), the comparator output P = “L”, and when (n × 3B) ≧ (A + B + C), the comparator output P = “H”. Then, when P = “H”, the value of the counter 221 is latched by the latch circuit 211. The counter 221 is a counter that is reset, for example, in a horizontal cycle. The output of the counter 221 is input to the decoder 222 and used to generate various drive pulses for the solid-state imaging device.

The output of the latch circuit 211 is
Is supplied to the multiplier 213 via the. In this embodiment, the output of the latch circuit 211 has the same role as the result of the division in the previous embodiment.

The operation of the above embodiment will be described with reference to FIG. FIG. 4A shows an image pickup signal having flicker. FIG. 4 (4B) shows the output of the counter 211 and the output of the comparator 210. Two examples of the output of the counter 221 are shown. One example is the next horizontal period after the addition of the screen average luminance signals (A, B, C) is completed. In the case of the flicker shown in FIG.
Is small, so that n × 3B is (n × 3B) ≧ (A
+ B + C) takes time (n2
Count is required).

Another example is a screen average luminance signal (B,
9 shows an example of the next horizontal period after the addition of C and D) is completed. In the case of the flicker shown in this figure, the level of the screen average luminance signal C is large, so that n × 3C is (n × 3C) ≧ (B +
It does not take much time until the relationship of (C + D) is reached (the count of n1 is sufficient).

As described above, the count value is obtained as a correction value according to the level of flicker. According to this embodiment, it is not necessary to use a divider which tends to be large, and a small-scale and low-cost can be realized.

FIG. 5 shows still another embodiment of the present invention. This embodiment is a combination of the circuit shown in FIG. 3 and the circuit shown in FIG. Therefore, portions corresponding to the respective drawings are denoted by the same reference numerals. That is, the first
Is output as the first comparison signal by the comparator 2
10 is input. The output (triple signal) of the second arithmetic unit 208 is input to the multiplier 209 and
Multiplied by the output of 1. Then, the output of the multiplier 209 is input to the comparator 210 as a second comparison signal.

FIG. 6 shows still another embodiment of the present invention. In this embodiment, the operation of the circuit shown in FIG. 5 and the operation of the circuit shown in FIG. 3 can be selectively obtained. Therefore, portions corresponding to the respective drawings are denoted by the same reference numerals. In the case of this embodiment, a switch 300 is provided. The output of the register 107 is supplied to one of the switches 300, and the output of the register 104 is supplied to the other of the switches 300. The switch 300 derives one of them according to the switching signal supplied to the terminal 301, and
And the second arithmetic unit 208.

Therefore, when the screen average luminance signal B shown in the figure is selected, the same circuit operation as that of the circuit shown in FIG. 3 can be obtained. When the screen average luminance signal E is selected, the circuit operation shown in FIG. The same circuit operation as that of the circuit can be obtained.

[0043]

As described above, according to the present invention,
It is possible to appropriately cope with an imaging signal obtained by greatly changing the accumulation time for each field. Further, according to the present invention, a flicker correction circuit having a small circuit scale can be obtained. Further, according to the present invention, it is possible to appropriately cope with an image pickup signal obtained by greatly changing the accumulation time for each field, and to obtain a flicker correction circuit having a small circuit scale.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of the present invention.

FIG. 2 is a waveform chart shown for explaining the operation of the circuit of FIG. 1;

FIG. 3 is a diagram showing another embodiment of the present invention.

FIG. 4 is a waveform chart shown for explaining the operation of the circuit of FIG. 3;

FIG. 5 is a diagram showing still another embodiment of the present invention.

FIG. 6 is a diagram showing still another embodiment of the present invention.

FIG. 7 is a diagram for explaining the cause of flicker generation.

FIG. 8 is a diagram for explaining another cause of occurrence of flicker.

FIG. 9 is a diagram showing a flicker correction circuit considered conventionally.

[Explanation of symbols]

 102, 202 ... 1 vertical period integrators 103-107, 203-205 ... delay unit 108 ... first computing unit 109 ... second computing unit 110 ... dividers 111, 212 ... delay units 112, 209, 213 ... Multipliers 206, 207 Adder 210 Comparator 211 Latch circuit 221 Counter 222 Decoder 300 Switch.

Claims (5)

[Claims] An input terminal to which an imaging signal obtained from a solid-state imaging device is input; an integration means for integrating the imaging signal of the input terminal for each screen to obtain an average luminance signal for each screen; Delay means for sequentially delaying the luminance signal by one screen unit to obtain a screen average luminance signal for a plurality of M (≧ 5) screens, and among the screen average luminance signals for the plurality of screens obtained from the delay means First calculating means for deriving and adding N (3 ≦ N <M) screen average luminance signals corresponding to a time separated by two screens to obtain a numerator signal, among the N screen average luminance signals Second computing means for obtaining a denominator signal obtained by multiplying one by N, dividing means for dividing the denominator signal by a numerator signal, and using the result as a correction signal, and a correction signal obtained by the division means Multiplying means for multiplying the imaging signal input to the input terminal by An electronic imaging apparatus having a flicker correction function, comprising: 2. An input terminal to which an imaging signal obtained from a solid-state imaging device is input; an integration unit that integrates the imaging signal of the input terminal in units of one screen to obtain an average luminance signal in units of a screen; The luminance signal is sequentially delayed by one screen unit, and 3
Delay means for obtaining a screen average luminance signal for three screens; first calculating means for adding the screen average luminance signals for three screens obtained from the delay means to obtain a first comparison signal; A second calculating means for obtaining a triple signal obtained by tripled one of the three screen average luminance signals; a high-speed counter for counting one or more times in one screen period; an output of the high-speed counter and the triple signal Multiply by the second
A first multiplying means for obtaining a comparison signal of the following formulas: a value of the first comparison signal is compared with a value of the second comparison signal, and the value of the first comparison signal is Comparing and latching means for latching the high-speed counter output when exceeding, and second multiplying means for adjusting the time of the latched output obtained from the comparing and latching means and multiplying the imaged signal of the input terminal by the time. An electronic imaging apparatus having a flicker correction function, comprising: 3. An input terminal to which an image signal obtained from a solid-state image sensor is input; an integrating means for integrating the image signal of the input terminal for each screen to obtain an average luminance signal for each screen; Delay means for sequentially delaying the luminance signal by one screen unit to obtain a screen average luminance signal for a plurality of M (≧ 5) screens, and among the screen average luminance signals for the plurality of screens obtained from the delay means Derive and add N (3 ≦ N <M) screen average luminance signals corresponding to the time separated by two screens,
A first calculating means for obtaining a comparison signal of the following; a second calculating means for obtaining an N-fold signal obtained by multiplying one of the N screen average luminance signals by N; a high-speed counting means for counting one or more times in one screen period Multiplying the output of the high-speed counter by the N-times signal;
A first multiplying means for obtaining a comparison signal of the following formulas: a value of the first comparison signal is compared with a value of the second comparison signal, and the value of the first comparison signal is Comparing and latching means for latching the high-speed counter output when exceeding, and second multiplying means for adjusting the time of the latched output obtained from the comparing and latching means and multiplying the imaged signal of the input terminal by the time. An electronic imaging apparatus having a flicker correction function, comprising: 4. An input terminal to which an imaging signal obtained from a solid-state imaging device is input; an integration means for integrating the imaging signal of the input terminal for each screen to obtain an average luminance signal for each screen; Delay means for sequentially delaying the luminance signal by one screen unit to obtain a screen average luminance signal for a plurality of M (≧ 5) screens, and among the screen average luminance signals for the plurality of screens obtained from the delay means Deriving and adding N (3 ≦ N <M) screen average luminance signals corresponding to the time separated by two screens,
Alternatively, N (3 ≦ N <M) screen average luminance signals corresponding to the time separated by one screen may be derived and added, or either of them may be selected, and the result of the addition may be selected as a first comparison signal. A first calculating means for obtaining an N-fold signal obtained by multiplying one of the N screen average luminance signals by N; a high-speed counter for counting one or more times in one screen period; Multiplying the output of the high-speed counter by the N-times signal,
A first multiplying means for obtaining a comparison signal of the following formulas: a value of the first comparison signal is compared with a value of the second comparison signal, and the value of the first comparison signal is Comparing and latching means for latching the high-speed counter output when exceeding, and second multiplying means for adjusting the time of the latched output obtained from the comparing and latching means and multiplying the imaged signal of the input terminal by the time. An electronic imaging apparatus having a flicker correction function, comprising: 5. The electronic image pickup apparatus having a flicker correction function according to claim 1, wherein the image pickup signal of the input terminal is digitized.