JPH10145162A - Amplifeir, transmission circuit and reception circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce power consumption and gain fluctuation, when input/output are low by connecting the multiple stages of active elements in parallel, switching bias voltage/current given to them and sequentially switching the desired number of elements from those of low gains to non-active ones. SOLUTION: An amplifier 22 is constituted by connecting the multiple stages of FET groups 27 and 28 in parallel. The gate length or the gate finger width of the group 27 is set to be small and that of the group 28 to be large. When high output is transmitted and when a received signal intensity is in a low level, the groups 27 and 28 are set in an operational state. When low output is transmitted and when received signal intensity is in the low level, a switch 37 is changed over, and the group 28 whose gain is low compared to that of the group 27 is set to an off-state. When low output is transmitted and when received signal intensity is in the low level, power consumption can be reduced, and the range of gain fluctuation is set to be small so as to reduce the discontinuity of the gain. Thus, the stability precision of output power and the gain can be improved by a simple constitution and control.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

【table of contents】

 The present invention will be described in the following order. Technical field to which the invention pertains Conventional technology (FIG. 7) Problems to be solved by the invention (FIGS. 8 and 9) Means for solving the problems Embodiments of the invention (FIGS. 1 to 6) Effects of the invention

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an amplifier, a transmission circuit, and a reception circuit, and is suitably applied to, for example, an amplifier, a transmission circuit, and a reception circuit used in a wireless communication terminal device for controlling transmission power.

[0003]

2. Description of the Related Art Conventionally, in a wireless communication terminal device such as a portable telephone, transmission power control is performed to reduce power consumption and interference with other stations. FIG. 7 shows a wireless communication terminal device that performs transmission power control. In FIG. 7, reference numeral 1 denotes a wireless communication terminal device as a whole, which receives a signal transmitted from a communication partner station by an antenna 2 and supplies it as a reception signal S1 to a reception circuit unit 4 via a transmission / reception splitter 3. I do.

The receiving circuit section 4 inputs the received signal S1 to the receiving amplifier 5. The receiving amplifier 5 amplifies the received signal S1 and converts it into a high-frequency signal S2. The receiving amplifier 5 sends out the obtained high-frequency signal S2 to the mixer 6. Here, the local frequency signal S3 is supplied to the mixer 6 from the local oscillator 7. The mixer 6 converts the high frequency signal S2 into an intermediate frequency signal S4 by mixing the local frequency signal S3 supplied from the local oscillator 7 with the high frequency signal S2, and sends it to the intermediate frequency variable gain amplifier 8.

[0005] Here, a reception power measuring circuit 10 is connected to the intermediate frequency gain variable amplifier 8, and the output level of the intermediate frequency signal S 4 transmitted from the intermediate frequency gain variable amplifier 8 by the reception power measuring circuit 10 is measured. Detection has been made.
The reception power measurement circuit 10 is an automatic gain controller (AGC).
ol) The control unit variably controls the gain of the intermediate frequency gain variable amplifier 8 according to the detected output level of the intermediate frequency signal S4. The intermediate frequency gain variable amplifier 8 supplies the intermediate frequency signal S4 obtained by performing the gain control to the demodulator 9. The demodulator 9 demodulates the intermediate frequency signal S4 into a baseband signal S5, and converts this into a baseband signal processing circuit 11
To supply.

On the other hand, a signal transmitted from the wireless communication terminal device 1 to the communication partner station (hereinafter, referred to as a transmission baseband signal S6) is transmitted from the baseband signal processing circuit 11 to the transmission circuit unit 12. The transmission circuit section 12 inputs the transmission baseband signal S6 to the modulator 13. The modulator 13 performs a predetermined modulation process on the transmission baseband signal S6 to convert it into an intermediate frequency signal S7,
Give to. Here, the intermediate frequency variable gain amplifier 14 is provided with a control signal S8 from the transmission power control circuit 15.
The transmission power control circuit 15 is provided with reception signal strength level information S9 corresponding to the output level of the intermediate frequency gain variable amplifier 8 from the reception power measurement circuit 10. The transmission power control circuit 15 generates a control signal S8 based on the received signal strength level information S9 and supplies the control signal S8 to the intermediate frequency gain variable amplifier. The intermediate frequency gain variable amplifier 14 controls the gain of the intermediate frequency signal S7 based on the control signal S8 thus supplied, and supplies the same to the mixer 16.

[0007] The mixer 16 mixes the local frequency signal S3 supplied from the local oscillator 7 with the intermediate frequency signal S7, converts it into a high frequency signal S10 as a radio frequency signal, and sends it to the radio frequency variable amplifier 17. Like the intermediate frequency gain variable amplifier 14, the control signal S12 based on the received signal strength level information S9 is given from the transmission power control circuit 15 to the radio frequency gain variable amplifier 17 like the intermediate frequency gain variable amplifier 14. The variable radio frequency gain amplifier 17 controls the gain of the high frequency signal S10 based on the control signal S12,
8 The transmission power amplifier 18 outputs the high-frequency signal S10
Is amplified and given to the transmission / reception splitter 3, which transmits and outputs the high-frequency signal S10 via the antenna 2.

As described above, in the radio communication terminal device 1, the received signal strength level information S9 corresponding to the level of the received signal is obtained.
The control signals S8 and S12 are generated on the basis of the above, and the transmission power control is performed by variably controlling the gains of the intermediate frequency gain variable amplifier 14 and the radio frequency gain variable amplifier 17 based on the control signals S8 and S12. Incidentally, there is a method of performing gain control based on an instruction signal included in the received signal S1 from the partner station. In this case, the wireless communication terminal device 1 extracts the instruction signal S11 from the partner station included in the received signal S1 by the baseband signal processing circuit 11. The instruction signal S11 is transmission power control information obtained by measuring the transmission signal level of the own station by the partner station.
The wireless communication terminal device 1 supplies the instruction signal S11 to the transmission power control circuit 15 via the microcomputer 19,
Thereby, control signals S8 and S12 are generated.

[0009]

By the way, in the wireless communication terminal device 1 having such a configuration, the input / output of the transmission power amplifier 18 disposed after the radio frequency gain variable amplifier 17 when performing the transmission power control is considered. In this case, there is a problem that wasteful power consumption is performed. Similarly, the efficiency of the amplification process by the receiving amplifier 5 is reduced according to the fluctuation of the received signal strength level. When the input power increases in the transmission power amplifier 18, the output power increases accordingly.
Further, as the input power increases, the power added efficiency also increases.
Here, when the input power to the transmission power amplifier 18 decreases due to the transmission power control at the time of low output, the power added efficiency decreases, and the power added efficiency is consumed for actually outputting the transmission signal with respect to the overall power consumption. Power is small. That is, at the time of low output, most of the power is wasted.

In order to avoid such a problem, the receiving amplifier 5 and the transmitting power amplifier 18 are connected to a plurality of FETs (Field
Effect Transistor) is connected in multiple stages in parallel,
A control signal is supplied from the transmission power control circuit 15 to
By switching the ET to the off state, a method of making the amplifier suitable for a low-level output in the low transmission output state can be considered.

As shown in FIG. 8, the reception amplifier 5 and the transmission power amplifier 18 (FIG. 7) having such a configuration are used in a low transmission output state or when the received signal strength is at a high level. The drain current can be reduced by limiting the number of FETs. In FIG. 8, the desired FET is turned off in the low transmission output state where the output power is 15 [dBm] or less, so that the drain current Id [mA] is 以下 or less as compared with the case where all the FETs are in the on state. It has become.

However, as shown in FIG. 9, in the receiving amplifier 5 and the transmitting power amplifier 18 using such a technique, the FET is turned off when the transmission output state is low or the received signal strength is at a high level. Gain fluctuation occurs at the time of switching. In FIG. 9, a gain fluctuation of about 1.3 [dB] occurs when switching to the off state. Such discontinuity of the power gain affects the stability of the wireless communication device, and becomes a problem particularly when power control needs to be performed with high accuracy.

The following method can be considered to compensate for such a gain fluctuation. For example, a compensation control circuit is connected and provided to the radio frequency variable gain amplifier 17 preceding the transmission power amplifier 18. The compensation control circuit has, for example, table data of a predetermined switching level of the transmission power and a gain variation amount of the radio frequency variable gain amplifier 17 corresponding to each switching level. Thus, power consumption control is performed in the low transmission output state, and compensation control is performed by the compensation control circuit so as to increase or decrease the gain that fluctuates at this time.

However, when such a compensation control circuit is provided, the configuration becomes complicated, which hinders the miniaturization of the wireless communication terminal device 1. Further, when such a compensation control circuit is shared with the radio frequency gain variable amplifier 17, the control becomes complicated.

The present invention has been made in view of the above points, and proposes an amplifier, a transmission circuit, and a reception circuit that can improve the accuracy of output power and gain stability with a simple configuration and control. Things.

[0016]

According to the present invention, a first active element and second to Nth active elements having a lower gain than the first active element are connected in parallel. Amplifying means connected in multiple stages, when the input power to the amplifying means is equal to or less than a predetermined threshold, by switching the bias voltage or bias current supplied to each active element,
Bias control means for controlling the gain of the amplification means as a whole by sequentially switching a desired number of active elements from a low gain element to an inactive state.

At the time of high output or high input, all the active elements are set to the active state. At the time of low output or low input, the low-gain second to Nth active elements are sequentially set to the inactive state from the one with the lowest gain. By doing so, it is possible to reduce the power consumption at the time of low output and low input, and to reduce the fluctuation of the gain.

In the present invention, the first active element and the second to Nth active elements having a lower gain than the first active element are connected in multiple stages in parallel, and the input transmission signal Amplifying means for performing the amplifying process, and when the input power to the amplifying means is equal to or less than a predetermined threshold, a bias voltage or a bias current to be supplied to each active element is switched so that a desired number of active elements are switched from those having a low gain. Bias control means for controlling the gain of the whole amplification means by sequentially switching to the inactive state, detection means for detecting the signal level of the transmission signal inputted to the amplification means, and according to the detection result of the detection means, And control means for determining the number of active elements to be switched to the inactive state and supplying the same to the bias control means.

At the time of high-power transmission, all the active elements are set to the active state, and at the time of low-output transmission, the low-gain second to N-th active elements are sequentially set to the inactive state from the one having the lowest gain. It is possible to reduce the power consumption of the amplifying unit at the time of low-power transmission, reduce the fluctuation of gain, and improve the accuracy of transmission control.

In the present invention, a first active element and second to Nth active elements having a lower gain than the first active element are connected in multiple stages in parallel. Amplifying means for performing the amplifying process, and when the input power to the amplifying means is equal to or more than a predetermined threshold, the bias voltage or the bias current to be supplied to each active element is switched so that a desired number of active elements are switched from those having a low gain. Bias control means for controlling the gain of the whole amplification means by sequentially switching to the inactive state, detection means for detecting the signal level of the received signal inputted to the amplification means, and according to the detection result of the detection means, And control means for determining the number of active elements to be switched to the inactive state and supplying the same to the bias control means.

When the received signal strength is at a high level, all the active elements are activated, and when the received signal strength is at a low level, the low-gain second to N-th active elements are sequentially set in order from the one with the lowest gain. By setting it to the inactive state, when the received signal strength is at a low level, the power consumption of the amplifying means can be reduced, the fluctuation of the gain can be reduced, and the accuracy of the reception control can be improved.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings.

In FIG. 1 in which parts corresponding to those in FIG. 7 are assigned the same reference numerals, reference numeral 20 denotes a wireless communication terminal device as a whole, and an amplifier 21 and an amplifier 21 instead of the reception amplifier 5 and the transmission power amplifier 18 (FIG. 7). 22 and a receiving power control circuit 23 for controlling the power consumption and gain of the amplifier 21 on the receiving circuit 4 side. Receive power control circuit 2
3 and the transmission power control circuit 15
It is connected to the. The reception power measurement circuit 10 detects the output level of the intermediate frequency signal S4 output from the intermediate frequency gain variable device 8, and outputs the reception signal strength level information S9 corresponding to the output level to the reception power control circuit 23 and the transmission power control. Supply to circuit 15.

Based on the received signal strength level information S9 thus provided, the reception power control circuit 23
By supplying the control signal S13 to the power supply, the power consumption of the amplifier 21 is reduced and the reduction of the gain is reduced when the received signal strength is low. Further, the transmission power control circuit 15 supplies the control signal S14 to the amplifier 22 based on the received signal strength level information S9 thus provided, thereby reducing the power consumption of the amplifier 22 when the transmission power is low. Control is performed so as to reduce the gain and the decrease in gain. The control for reducing the power consumption and the reduction in the gain will be described later.

FIG. 2 shows the internal configuration of the amplifier 22, which is composed of a transmission power amplifier 24 and a gate bias controller 25. Note that the amplifier 21 has the same configuration as the amplifier 22, and a description thereof will be omitted. The amplifier 22 has an input power P
1 is input to the transmission power amplifier 24. Transmission power amplifier 2
4 inputs the input power P1 to the FET (Fiel
d Effect Transistor) groups 27 and 28 and output as output power P2 via the matching circuit 29.

Each of the FET groups 27 and 28 is constituted by a plurality of unit FETs. The gate and drain of each unit FET are electrically connected, and the source is grounded. In the FET group 27 and the FET group 28, unit FETs having different gate lengths or gate finger widths are arranged. For example, the gate length or the gate finger width of the unit FET in the FET group 27 is equal to the unit FET in the FET group 28.
Is smaller than the gate length or gate finger width. Thus, the gain of the FET group 27 is higher than the gain of the FET group 28. The relationship between the structure (gate length, gate finger width) and gain of each unit FET will be described later.

The matching circuit 26 and the FET groups 27 and 28
And DC cut capacitors 30 and 31 are connected to each other, so that the FET groups 27 and 28 are connected.
Are separated in a DC manner and connected in a high-frequency manner. Further, gate resistors 32 and 33 are connected to the gate electrodes of the FET groups 27 and 28, respectively, so that the gate electrodes of the FET groups 27 and 28 are isolated from the gate bias control unit 25 by high-frequency isolation. I'm getting Chillon.

On the other hand, the drain electrodes of the FET groups 27 and 28 are connected, and the drain electrodes and the matching circuit 29 are connected.
And the drain voltage Vd is applied from the high-frequency chopper coil 34 connected between the drain current Id _max
Have gained. Note that the drain current Id _max is set to the FET group 27.
And 28 are current amounts obtained when the operating gate voltage is applied.

The gate bias control unit 25 includes an FET group 27
And 28 are provided. The gate bias control unit 25 obtains the operating gate voltage V _on and the off-gate voltage V _off which is equal to or lower than the pinch-off voltage Vp by, for example, resistance division by the resistors 35 and 36. The gate bias control unit 25 supplies an operation gate voltage V _on as a gate voltage for the FET group 27 via a gate resistor 32. On the other hand, the operation gate voltage V _on and the off-gate voltage V _off are supplied to each terminal of the switch 37, and the switch 37 is connected to the gate resistor 33. The gate bias control unit 25 determines the operating gate voltage V _on and the off-gate voltage V
Either "_off" or "_off" is supplied by switching the switch 37.

The switch 37 is switched by a control signal S14 supplied from the transmission power control circuit 15. That is, when transmission power is high transmission output state, switch 37 is connected to the terminal side of the operating gate voltage V _on is supplied, supplies the operating gate voltage V _on the gate voltage for FET group 28. When the transmission power is in the low transmission output state, the switch 37 is connected to the terminal to which the _off- gate voltage V _off is supplied,
An _off- gate voltage _Voff is supplied as a gate voltage to the FET group 28.

In this way, when the amplifier 22 is in the high transmission output state, the switching of the switch 37 supplies the operating gate voltage V _on to both of the FET groups 27 and 28 so that the amplifier 22 is suitable for high-level output. . In the case of the low transmission output state, the switching of the switch 37 causes the FET group 2 to change.
By supplying the operation gate voltage V _on only to the FET 7 and turning off the FET group 28, an amplifier suitable for low-level output is obtained.

As shown in FIG. 3, the FET groups 27 and 28
Each of the unit FETs includes a source, a gate, and a drain electrode, and the current value flowing from the drain electrode to the source electrode changes according to the voltage applied to the gate electrode. Here the gate length L _G shown in FIG. Generally, the maximum oscillation frequency f _max is used as the performance value of the amplification element. Where f
_max indicates the frequency at which the power gain becomes 1, and when Rg is the gate resistance value of the FET, Gd is the drain conductance of the FET, and ν _sat is the electron saturation speed, the gain of the FET is

(Equation 1) Can be approximately expressed by As can be seen from the equation (1), in the FET, f _max , that is, the gain at a predetermined frequency point can be increased by reducing the gate length L.

As for the gate finger width Z _G , as shown in FIG. 4, it can be seen from the simulation value of the gain characteristic with respect to the gate finger width Z _G that the gain can be increased by reducing Z _G.

Therefore, in the FET groups 27 and 28,
As described above, the power gain is increased by reducing the gate length or the gate finger width of the FET group 27, and
The power gain is reduced by increasing the gate length or the gate finger width of the ET group 28. FIG.
As shown in the figure, the amplifier 22 is a FET group 27 having a high gain.
And a low-gain FET group 28 are connected in parallel, and at the time of low-output transmission (15 [dBm] in FIG.
8 is switched to the OFF state, so that the fluctuation width of the gain with respect to the input power, that is, the fluctuation width from the gain at the time of high output transmission to the gain at the time of low output transmission is made smaller than the conventional fluctuation width. Have gained.

In the above configuration, the amplifier 22 is a FET
The configuration is such that the groups 27 and 28 are connected in multiple stages in parallel.
At the time of high output transmission, the gate voltages supplied to the FET groups 27 and 28 are both V _on , and both the FET groups 27 and 28 are in operation. In this case, the drain current Id is F
The current value flows through the ET groups 27 and 28. At the time of low output transmission, the gate voltage supplied to the FET group 28 is switched to V _off , and only the FET group 27 is in the operating state. In this case, the drain current Id is
7 (FIG. 8). As described above, the amplifier 22 switches the operation state of the FET group 28 to the off state at the time of low-output transmission, and sets only the FET group 27 to the operation state, thereby reducing the power consumption required for the operation of the FET group 28. , Power consumption can be reduced.

In the amplifier 22, the gate length or the gate finger width of the FET group 27 is reduced, and the gate length or the gate finger width of the FET group 28 is increased. At the time of high-output transmission, that is, when both the FET groups 27 and 28 are in the operating state, since the FET group 28 having a lower gain than that of the FET group 27 is included, the same gain is used as in the related art. Amplifier 2 compared to the case where
2 The overall gain is reduced. However, at the time of low output, that is, when only the FET group 27 is in operation,
Since the ET group 27 has a higher gain than the FET group 28,
The gain of the amplifier 22 as a whole is equal to that of the conventional amplifier (FIG. 5).

As described above, the amplifier 22 is provided with the FET groups 27 and 28 having different gate lengths or gate finger widths.
FE with low gain compared to FET group 27 during low output transmission
By turning off the T group 28, the fluctuation range of the gain with respect to the input power can be made smaller than that of the conventional amplifier when compared with the high power transmission, thereby reducing the discontinuity of the gain. be able to.

According to the above configuration, the FET groups 27 and 28 having different gate lengths or gate finger widths are provided, and the FET groups 27 and 28 are connected in parallel in multiple stages.
FET at high output transmission and low reception signal strength
When both the groups 27 and 28 are in the operating state, the switch 37 is switched when the output is low and the received signal strength is low, so that the gain is lower than that of the FET group 27 by switching the switch 37.
By turning off the ET group 28, it is possible to reduce power consumption at the time of low output transmission and at the time of a low level of the received signal strength, and to reduce the gain fluctuation width to reduce the gain discontinuity. . Thus, the accuracy of output power and gain stability can be improved with a simple configuration and control.

In the above embodiment, the FET groups 27 having different gate lengths or gate finger widths are used.
And 28 have been described, but the present invention is not limited to this. For example, three or more FET groups each having a different gate length or gate finger width may be provided.

In the above embodiment, the FET group 2
Although the case of the amplifiers 21 and 22 provided with 7 and 28 has been described, the present invention is not limited to this, and for example, a bipolar transistor may be provided. As shown in FIG. 6, the bipolar transistor includes an emitter, a base, and a collector electrode, and the amount of current flowing from the collector electrode to the emitter electrode changes according to the current value applied to the base electrode (in the case of an npn type). In the bipolar transistor, the emitter width We corresponds to the gate length L, and the emitter length Le corresponds to the gate finger width Z. Therefore, in an amplifier provided with a bipolar transistor, different emitter widths We and different emitter lengths Le are used.
May be provided.

Further, in the above-described embodiment, FET groups 27 and 28 each composed of a plurality of unit FETs are provided.
FET group 2 at the time of high output transmission and reception signal strength high level, or at the time of low output transmission and reception signal strength low level
Although the description has been given of the case of the amplifiers 21 and 22 which switch the operation state of the switching device 8 on or off, the present invention is not limited to this, and the switching operation of each of the unit FETs may be performed.

In the above embodiment, the case where the output level of the intermediate frequency gain variable amplifier 8 is detected by the reception power measuring circuit 10 has been described. However, the present invention is not limited to this. May be arranged downstream of the amplifier 21.

Further, in the above-described embodiment, the case of the wireless communication terminal device 20 in which the transmission power control circuit 15 and the reception power control circuit 23 are configured separately has been described. However, the present invention is not limited to this. The power control circuit and the reception power control circuit may have the same configuration. Accordingly, the wireless communication terminal device can control the power consumption and the gain in the transmission circuit and the reception circuit collectively.

[0044]

As described above, according to the present invention, the first active element and the second to second elements having a lower gain than the first active element.
Amplifying means comprising a plurality of N-th active elements connected in parallel,
When the input power to the amplifying means is equal to or less than a predetermined threshold value, the bias voltage or the bias current supplied to each active element is switched, and the desired number of active elements are sequentially switched to the inactive state from the one with the lowest gain. Bias control means for controlling the gain of the amplification means as a whole, to activate all the active elements at the time of high output or high input, and the second to second low gain at the time of low output or low input. By inactivating the N active elements sequentially from the one with the lowest gain, the power consumption at the time of low output and low input can be reduced, and the fluctuation of the gain can be reduced. With a simple configuration and control, the accuracy of output power and gain stability can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a wireless communication terminal device according to one embodiment of the present invention.

FIG. 2 is a circuit diagram illustrating a circuit configuration of an amplifier according to an embodiment.

FIG. 3 is a perspective view for explaining the internal configuration of the FET.

FIG. 4 is a table for explaining a relationship between a gate finger width and a gain characteristic;

FIG. 5 is a chart for explaining reduction of gain discontinuity according to an embodiment;

FIG. 6 is a perspective view for describing the internal configuration of the bipolar transistor.

FIG. 7 is a block diagram showing a configuration of a conventional wireless communication terminal device.

FIG. 8 is a chart for explaining a reduction in power consumption in a low transmission output state.

FIG. 9 is a table for explaining a discontinuity of a gain accompanying a reduction in power consumption.

[Explanation of symbols]

1, 20 wireless communication terminal device, 2 antenna, 3 ...
… Transmitter / demultiplexer, 4… Reception circuit unit, 5… Reception amplifier,
6, 16: Mixer, 7: Local oscillator, 8, 14
…… Intermediate frequency gain variable amplifier, 9 …… Demodulator, 10 ……
Reception power measurement circuit, 11 baseband signal processing circuit, 12 transmission circuit section, 13 modulator, 15 transmission power control circuit, 17 radio frequency gain variable amplifier, 1
8 ... transmission power amplifier, 19 ... microcomputer, 21, 22 ... amplifier, 24 ... transmission power amplifier,
25 gate bias control section, 26, 29 matching circuit, 27, 28 FET group, 30, 31 DC cut capacitor, 32, 33 gate resistance, 34 high frequency chiyo coil, 35, 36 ... resistance, 37 ... switch.

Claims (15)

[Claims] Amplifying means comprising a first active element and second to Nth active elements having a lower gain than the first active element connected in parallel in multiple stages; and input power to the amplifying means. When is equal to or less than a predetermined threshold value, the bias voltage or bias current supplied to each of the active elements is switched, and the desired number of the active elements are sequentially switched from the one having a low gain to the inactive state by switching to the inactive state. An amplifier, comprising: bias control means for controlling a gain of the amplification means as a whole. 2. The active device according to claim 1, wherein a single or a plurality of FETs are connected in parallel, and a gate length of a gate electrode of the FET is equal to the first active device and the second to Nth active devices. The amplifier according to claim 1, wherein 3. Each of the active elements comprises a single or a plurality of FETs connected in parallel, wherein the gate width of the gate electrode of the FET is equal to the first active element and the second to Nth active elements. The amplifier according to claim 1, wherein 4. Each of the active elements includes one or more bipolar transistors connected in parallel, and the emitter width of an emitter electrode of the bipolar transistor is different from the first active element and the second to Nth active elements. The amplifier according to claim 1, wherein the amplifier differs from the element. 5. Each of the active elements comprises a single or a plurality of bipolar transistors connected in parallel, and the emitter length of an emitter electrode of the bipolar transistor is equal to the first active element and the second to Nth active elements. The amplifier according to claim 1, wherein the amplifier differs from the element. 6. A first active element and second to Nth active elements having a lower gain than the first active element are connected in multiple stages in parallel, and amplifying an input transmission signal. Amplifying means for performing, when the input power to the amplifying means is equal to or less than a predetermined threshold, a bias voltage or a bias current to be supplied to each of the active elements is switched, and a desired number of the active elements are sequentially switched from a low gain element Bias control means for controlling the gain of the entire amplification means by switching to an inactive state, detection means for detecting the signal level of the transmission signal inputted to the amplification means, and detection results of the detection means. Control means for determining the number of the active elements to be switched to the non-active state and supplying the determined number to the bias control means. 7. Each of said active elements comprises a single or a plurality of FETs connected in parallel, wherein the gate length of a gate electrode of said FET is equal to said first active element and said second to Nth active elements. 7. The transmission circuit according to claim 6, wherein 8. Each of the active elements includes a single or a plurality of FETs connected in parallel, and the gate width of the gate electrode of the FET is set to the first active element and the second to Nth active elements. 7. The transmission circuit according to claim 6, wherein 9. Each of the active elements includes one or more bipolar transistors connected in parallel, and the emitter width of an emitter electrode of the bipolar transistor is different from the first active element and the second to Nth active elements. 7. The transmission circuit according to claim 6, wherein the transmission circuit differs from the element. 10. Each of the active elements includes one or more bipolar transistors connected in parallel, and the emitter length of an emitter electrode of the bipolar transistor is equal to the first active element and the second to Nth active elements. 7. The transmission circuit according to claim 6, wherein the transmission circuit differs from the element. 11. A multi-stage connection of a first active element and second to N-th active elements having a lower gain than that of the first active element is performed in parallel to perform amplification of an input received signal. Amplifying means for performing, when the input power to the amplifying means is equal to or more than a predetermined threshold, a bias voltage or a bias current to be supplied to each of the active elements is switched, and a desired number of the active elements are sequentially switched from one having a low gain. Bias control means for controlling the gain of the entire amplification means by switching to an inactive state, detection means for detecting a signal level of the reception signal input to the amplification means, and a detection result of the detection means. Control means for deciding the number of the active elements to be switched to an inactive state in accordance with the control means and supplying the determined number to the bias control means. 12. Each of the active elements includes a single or a plurality of FETs connected in parallel, and the gate length of the gate electrode of the FET is set to the first active element and the second to Nth active elements. The receiving circuit according to claim 11, wherein 13. Each of the active elements comprises a single or a plurality of FETs connected in parallel, wherein the gate width of the gate electrode of the FET is equal to the first active element and the second to Nth active elements. The receiving circuit according to claim 11, wherein 14. Each of the active elements comprises a single or a plurality of bipolar transistors connected in parallel, and the emitter width of an emitter electrode of the bipolar transistor is equal to the first active element and the second to Nth active elements. The receiving circuit according to claim 11, wherein the receiving circuit differs from the element. 15. Each of the active elements comprises a single or a plurality of bipolar transistors connected in parallel, and the emitter length of an emitter electrode of the bipolar transistor is equal to the first active element and the second to Nth active elements. The receiving circuit according to claim 11, wherein the receiving circuit differs from the element.