JPH10144077A - Static semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a circuit scale. SOLUTION: A pair of bit lines BL, /BL corresponding to a non-selected column is pre-charged to a 'L' level. Therefore, a connection/disconnection circuit 11 corresponding to non-selected column is not activated. Either of NMOS transistor 41 or 43 of the connection/disconnection circuit 11 corresponding to a selected column is turned on conforming to the information in a selected memory cell. Ground voltage is supplied to a data line D or/D from a NMOS transistor 13 through turned on NMOS transistor 41 or 43. A potential difference conformed to the information in the memory cell is generated in the pair of data lines D, /D. This potential difference is amplified by a sense amplifier 15.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a static semiconductor memory device, and more particularly to a static semiconductor memory device having a memory cell including two bipolar transistors, two access transistors, and two driver transistors.

[0002]

2. Description of the Related Art A static random access memory (hereinafter, referred to as "SRAM") as a conventional static semiconductor memory device is disclosed in Japanese Patent Laid-Open No. 7-226083.
No. 6,086,045.

FIG. 8 is a circuit diagram showing details of a peripheral portion of a conventional SRAM. Referring to FIG. 8, this SRAM
Have memory cells M1 to Mn at the intersections of word lines WL and bit line pairs BL and / BL. Further, a connection / disconnection circuit 9 corresponding to each bit line pair BL, / BL.
7 are provided. N corresponding to each connection / disconnection circuit 97
A MOS transistor 99 is provided. One equalize / precharge circuit 101 and one sense amplifier 103 are provided for all bit line pairs BL and / BL. Each of the memory cells M1 to Mn.
It comprises S transistors 105 and 107 and two inverters 119 and 121.

FIG. 9 is a circuit diagram showing details of the memory cells M1 to Mn of FIG. Referring to FIG. 9, this memory cell includes driver transistors Q1, Q2, access transistors Q3, Q4, and high resistance elements R1, R2.

Referring to FIG. 8 again, the read operation will be described. Consider a case where the memory cell M1 is selected. The potential of bit line pair BL, / BL is precharged to “H (high)” level. Further, the data line pair D,
The potential of / D is precharged to the “H” level by the equalize / precharge circuit 101. When the word line WL is activated, the potential of the bit line pair BL, / BL changes according to the information stored in the memory cell M1. When the word line WL is activated, the NMOS transistor 99 corresponding to the selected memory cell M1 is turned on. That is, only the column selection signal Y1 is “H”.
Be leveled. On the other hand, the column selection signals Y2 to Yn are at "L" level. Then, the bit line pair BL, / BL
, A potential difference occurs between the data line pair D and / D. Next, the sense amplifier 103 sets the data line pair D, / D
To amplify the potential difference.

[0006]

In the conventional SRAM configured as described above, the potential of the bit line pair BL, / BL is precharged to the "H" level, so that the selected bit line pair Not only NMOS transistors 109 and 111 corresponding to BL and / BL, but also NMOS transistors 10 corresponding to unselected bit line pairs BL and / BL.
9,111 can also be on. Therefore, the bit line pair B
An NMOS transistor 99 is provided for each of L and / BL, and the NMOS transistor 99 corresponding to the unselected bit line pair BL and / BL is turned off. Thus, the conventional S
In the RAM, since a plurality of NMOS transistors 99 are provided corresponding to a plurality of bit line pairs BL and / BL, there is a problem that the circuit scale becomes large.

The present invention has been made to solve the above problems, and has as its object to provide a static semiconductor memory device capable of reducing the circuit scale.

[0008]

According to a first aspect of the present invention, there is provided a static semiconductor memory device comprising a plurality of memory cells, a plurality of bit line pairs, a pair of data lines, a voltage supply line,
A connection / disconnection unit and a voltage supply unit are provided. The plurality of memory cells are arranged in a matrix of rows and columns. Bit line pairs are arranged corresponding to each column. A memory cell in a corresponding column is connected to the bit line pair. A first voltage is applied to the pair of data lines. A second voltage supplied to one of the pair of data lines is applied to the voltage supply line. The connection / disconnection means is provided corresponding to each row. The connection / disconnection means connects or disconnects a pair of data lines and a voltage supply line. The voltage supply means supplies a second voltage to the voltage supply line. Each memory cell includes two bipolar transistors, two access transistors, and two driver transistors. The connection / disconnection means corresponding to the selected column connects one of the pair of data lines to the voltage supply line according to the information stored in the selected memory cell. A third voltage is applied to a bit line pair corresponding to a non-selected column. The connection / disconnection means corresponding to the unselected column disconnects the pair of data lines and the voltage supply line according to the third voltage.

According to a second aspect of the present invention, there is provided a static semiconductor memory device according to the first aspect, wherein
The disconnecting means includes two NMOS transistors. NM
One of the OS transistors is connected to one of a pair of data lines,
A control electrode is provided between the power supply line and a voltage supply line, and its control electrode is connected to one bit line of a corresponding bit line pair. The other of the NMOS transistors is provided between the other of the pair of data lines and the voltage supply line, and its control electrode is connected to the other bit line of the corresponding bit line pair. The third voltage level applied to the bit line pair corresponding to the unselected column is N
This is a level at which the MOS transistor can be deactivated.

According to a third aspect of the present invention, there is provided a static semiconductor memory device according to the first or second aspect, wherein a plurality of equalizing means, a plurality of precharge means, and a plurality of current supply means are provided. , A sense amplifier, and an equalizing / precharging means. The equalizing means is provided corresponding to each column. The equalizing means equalizes the potential of one bit line of the corresponding bit line pair and the potential of the other bit line. The precharge means is provided corresponding to each column. The precharge means
A third voltage is applied to a corresponding bit line pair. The current supply means is provided corresponding to each column. The current supply means is
A current is supplied to the corresponding bit line pair. The sense amplifier is provided corresponding to the pair of data lines and amplifies a potential difference between the pair of data lines. The equalizing / precharging means is provided corresponding to the pair of data lines, and equalizes one potential of the data line and the other potential of the data line. The equalizing / precharging means applies a first voltage to the pair of data lines.

According to a fourth aspect of the present invention, there is provided a static semiconductor memory device according to the third aspect, wherein the sense amplifier is a latch type.

According to a fifth aspect of the present invention, there is provided the static semiconductor memory device according to the third aspect, wherein the equalizing means and the precharging means corresponding to the selected column are inactivated. The current supply means corresponding to the selected column is activated. After the start of the read operation, the voltage supply means is activated. After the start of the read operation, the equalizing / precharging means is deactivated. The sense amplifier is activated after a predetermined time elapses after the voltage supply means is activated.

According to a sixth aspect of the present invention, there is provided the static semiconductor memory device according to the third aspect, wherein the precharge means corresponding to a non-selected column is activated. The current supply means corresponding to a non-selected column is inactivated.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG.
In order to increase the static noise margin and secure the data retention, the following design is required for the memory cell. The channel width of driver transistors Q1 and Q2 is Wd, the channel length is Ld, the channel width of access transistors Q3 and Q4 is Wa, and the channel length is La. In such a case, in order to increase the static noise margin, generally, (Wd
/ Ld) needs to be about three times or more of (Wa / La). For this reason, there is a problem that the area of the driver transistors Q1 and Q2 becomes large, which prevents the area of the memory cell from being reduced. Furthermore, an SRAM using a low power supply potential
In this case, when the memory cell shown in FIG. 8 is used, there is a problem that a static noise margin becomes small and data retention becomes difficult. In the SRAM as the static semiconductor memory device according to the embodiment of the present invention, in order to solve the above-described problem, that is, to increase the static noise margin, two bipolar transistors and two drives are used. Transistors and
A memory cell including two access transistors is used.

FIG. 1 shows an SRA according to an embodiment of the present invention.
FIG. 4 is a circuit diagram showing details of M memory cells. Referring to FIG. 1, this memory cell is a bipolar transistor BP
1, BP2, driver transistors Q1 and Q2, and access transistors Q3 and Q4. The bipolar transistors BP1 and BP2 are of the PNP type. Driver transistors Q1, Q2 and access transistors Q3, Q4 are NMOS transistors.

The high resistance element R1 is connected to a power supply voltage V
It is provided between a node to which cc is applied and storage node SN1. The high resistance element R2 is connected to the power supply voltage V
It is provided between a node to which cc is applied and storage node SN2. Driver transistor Q1 includes a node supplied with ground voltage GND from ground 3 and a storage node SN
1, the gate of which is connected to storage node SN2
Connected to. Driver transistor Q2 is provided between storage node SN2 and a node supplied with ground voltage GND from ground 3, and has a gate connected to storage node SN.
Connected to 1. Access transistor Q3 includes base B of bipolar transistor BP1 and storage node SN
1, the gate of which is connected to the word line WL. Access transistor Q4 is connected to storage node S
N2 and a base B of bipolar transistor BP2 are provided, and the gate is connected to word line WL.
Bipolar transistor BP1 is provided between bit line BL and a node supplied with ground voltage GND from ground 3. Bipolar transistor BP2 is provided between bit line / BL and a node supplied with ground voltage GND from ground 3.

The write operation will be described with reference to FIG. In the following, a case is considered where "H" level is written to storage node SN1 and "L" level is written to storage node SN2.
The SRAM according to the present embodiment has a plurality of rows and columns. A plurality of word lines are arranged corresponding to a plurality of rows,
A plurality of bit line pairs are arranged corresponding to a plurality of columns. The plurality of memory cells are provided at intersections of the plurality of bit line pairs and the plurality of word lines. Row selection is performed by the word line WL. At the time of selection, the potential of the word line WL is set to “H (h
i) level, and the potential of the word line WL is at the “L (low)” level when not selected.

In a non-selected column, the potential of the bit line pair BL, / BL is set to a low level. For example, it is set to 0V. The potential of bit line BL of the selected column to be written is set to "H" level. The potential of bit line / BL of the selected column to be written is
It is set to the “L” level. In the selected memory cell, access transistors Q3 and Q4 are turned on. Further, since the potential of the bit line BL connected to the selected memory cell is high, the PN diode between the emitter and the base causes the bipolar transistor BP1
Has a value lower than the potential of the bit line BL by the voltage Vbe between the emitter and the base. Therefore, current flows from the emitter E toward the collector C and the base B. At this time, the current ratio between the base current and the collector current is given from the current amplification factor of the bipolar transistor BP1, and the collector current generally accounts for a large proportion.

Such a base current flows into storage node SN1 of the memory cell, and raises the potential of storage node SN1. When the potential of storage node SN1 exceeds the threshold voltage of driver transistor Q2, storage node SN1
And driver transistor Q2 to which the gate is connected
Turns on. Therefore, the potential of the storage node SN2, that is, the drain potential of the driver transistor Q2 decreases, and the driver transistor Q1 whose storage node SN2 is connected to its gate is turned off. When the driver transistor Q1 is turned off, the bipolar transistor BP1
Is cut off, and the collector current is also cut off.
Therefore, a large current temporarily flows from the emitter E to the collector C of the bipolar transistor BP1 during writing, but this current is cut off immediately after writing. On the other hand, the potential of bit line / BL is at a low level, and bipolar transistor BP2 does not turn on. Note that the storage node SN1
To the storage node SN2.
The operation for writing "H" level is performed in the same manner.

The read operation will be described. Here, a case is considered where "H" level is written to storage node SN1 and "L" level is written to storage node SN2. When the read operation is started, the word line WL is activated. Then, access transistors Q3 and Q4 are turned on. On the other hand, before the start of the read operation, bit line pair BL, / BL is precharged to the "L" level, and bit line pair B is started with the start of the read operation.
The potentials of L and / BL are pulled up to “H” level by a current supply circuit (not shown). That is, an appropriate amount of current flows from the current supply circuit to the bit line pair BL, / BL. Of this current, bipolar transistor B
The current determined by the current amplification factor of P2 flows into the memory cell via the base B of the bipolar transistor BP2. Therefore, the current supply circuit needs to be set to a current value that does not destroy data in the memory cell. In FIG. 1, the current supply circuit includes a bit line pair B
A current of 200 μA is supplied to L and / BL. It is assumed that 20% of 10% of this current (emitter current) flows into the memory cell.

Here, the driver transistor Q2 is on and the driver transistor Q1 is off.
Therefore, a base current flows through the bipolar transistor BP2 connected to the driver transistor Q2 which is turned on. Therefore, the bipolar transistor BP2
Turns on, and the current from the current supply circuit flows into the memory cell. Therefore, the potential of bit line / BL falls. On the other hand, since the bipolar transistor BP1 does not turn on,
The potential of the bit line BL increases. Therefore, a potential difference occurs between bit line pair BL and / BL. By sensing and amplifying the potential difference with a sense amplifier (not shown), data in the memory cell can be read.

FIG. 2 shows an SRAM according to an embodiment of the present invention.
FIG. 3 is a circuit diagram showing details of a peripheral portion of FIG. The same parts as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted as appropriate. Referring to FIG. 2, this SRAM includes a plurality of memory cells MC1 to MCn..., A plurality of equalizing circuits 5, a plurality of current supply circuits 7, a plurality of precharge circuits 9, a plurality of connection / disconnection circuits 11, an NMOS. It includes a transistor 13, a sense amplifier 15, an equalize / precharge circuit 17, a first control signal generation circuit 4, and a second control signal generation circuit 6. Each of the memory cells MC1 to MCn ...
Is the same as the configuration of the memory cell of FIG. Each equalizing circuit 5 includes a PMOS transistor 19 and N
It comprises a MOS transistor 35. Each current supply circuit 7
Comprises PMOS transistors 21 and 23. Each precharge circuit 9 includes NMOS transistors 37 and 39. Each connection / disconnection circuit 11 includes NMOS transistors 41 and 43. The sense amplifier 15 is a PMOS
Transistors 25 and 27 and NMOS transistor 4
5, 47, 49. The equalize / precharge circuit 17 includes PMOS transistors 31, 29, 33 and an NMOS transistor 51. Note that the sense amplifier 15 is a latch type.

In the equalizing circuit 5, the PMOS transistor 19 is provided between the bit line BL and the bit line / BL, and its gate is connected to the equalizing signal supply line EQ2.
Connected to. The NMOS transistor 35 is provided between the bit line BL and the bit line / BL, and has its gate connected to the equalizing signal supply line EQ1. In current supply circuit 7, PMOS transistor 23 is provided between a node to which power supply voltage Vcc is applied from power supply 1 and bit line BL, and has a gate connected to pull-up signal supply line P.
A1,... Or PAn. PMOS transistor 21 is provided between a node to which power supply voltage Vcc is applied from power supply 1 and bit line BL, and has a gate connected to pull-up signal supply lines PA1,.

In the precharge circuit 9, the NMOS transistor 37 is provided between the bit line BL and the precharge voltage supply line PV, and its gate is connected to the precharge signal supply lines PC1,. .
NMOS transistor 39 is provided between bit line / BL and precharge voltage supply line PV, and its gate is connected to precharge signal supply lines PC1,..., Or PCn. In the connection / disconnection circuit 11, the NMOS transistor 41 is provided between the data line D and the ground voltage supply line GV, and has a gate connected to the bit line BL. NMOS transistor 43 is provided between data line / D and ground voltage supply line GV, and has its gate connected to bit line / BL. NMOS transistor 13
Is the ground voltage supply line GV and the ground 3 to the ground voltage GND
Is provided between the node and the gate of which
Connected to transistor activation signal supply line TR.

In the sense amplifier 15, the PMOS transistor 25 and the NMOS transistor 45 are connected to a node supplied with the power supply voltage Vcc from the power supply 1,
The transistor 49 is connected in series with the drain. PMOS transistor 27 and NMOS transistor 47 are connected in series between a node supplied with power supply voltage Vcc from power supply 1 and the drain of NMOS transistor 49. PMOS transistor 25 and N
MOS transistor 45 has its gate connected to data line / D. The gates of the PMOS transistor 27 and the NMOS transistor 47 are connected to the data line D.
The source of the NMOS transistor 49 is connected to a node supplied with the ground voltage GND from the ground 3, and the gate thereof is connected to the sense amplifier activation signal supply line SA.

In the equalize / precharge circuit 17, the PMOS transistor 31 is provided between a node supplied with the power supply voltage Vcc from the power supply 1 and the data line D. PMOS transistor 29 is provided between a node supplied with power supply voltage Vcc from power supply 1 and data line / D. PMOS transistor 33 is provided between data line D and data line / D. The NMOS transistor 51 is provided between the data line D and the data line / D, and has its gate connected to the equalize / precharge signal supply line EP2. PMOS transistors 31 and 3
Gates 3 and 29 are connected to an equalize / precharge signal supply line EP1.

The first control signal generation circuit 4 includes column selection signals Y1 to Yn and an internal write enable signal intWE.
And internal output enable signal intOE. Then, the first control signal generation circuit 4 includes equalizing signals EQ1 and EQ2, precharge signals PC1 to PC
n and pull-up signals PA1 to PAn. Here, each signal generated by the first control signal generation circuit 4 is:
It is given to the wires with the same reference numerals. Further, the internal write enable signal intWE controls the write / read operation. The internal output enable signal intOE controls data output. The second control signal generation circuit 6
It receives an ATD (Address Transition Detection) signal and an internal output enable signal intOE. Then, transistor activation signal TR, sense amplifier activation signal SA, and equalize / precharge signal EP
1 and EP2 are generated. Here, each signal generated from the second control signal generation circuit 6 is given to a wiring denoted by the same reference numeral. The ATD signal is a one-shot high-level pulse generated when the address changes.

A pair of bit lines B corresponding to one column
L, / BL, one equalizing circuit 5, one current supply circuit 7, one precharge circuit 9, and one connection /
A disconnection circuit 11 is provided. One NMOS transistor 13 and one sense amplifier 15 for all columns
And one equalize / precharge circuit 17, one first control signal generation circuit 4, and one second control generation circuit 6.

FIG. 3 shows an SRA according to an embodiment of the present invention.
FIG. 5 is a timing chart for explaining a read operation of M. The state of the SRAM before the start of the read operation in the read mode (time t0 to t1) will be described with reference to FIGS. Attention is focused on the memory cell MC1 and various circuits corresponding to the column where the memory cell MC1 exists. When the internal output enable signal intOE transitions to the “H” level (time t0), the operation enters the read mode. Then, the read operation is started when the word line WL transitions to the “H” level.

The potential of word line WL is at "L" level. That is, the word line WL is inactivated.
Further, since the precharge signal PC1 is at the “H” level, the NMOS transistors 37 and 39 are on. That is, the precharge circuit 9 is activated. Here, “L” is applied to the precharge voltage supply line PV.
A level potential (0 V to 0.8 V) is supplied. Therefore, the potential of bit line pair BL, / BL is at "L" level. Therefore, the NMOS transistor 4
1, 43 are off. That is, the connection / disconnection circuit 11
Has been deactivated.

Before time t0, the equalizing signal EQ1
Is at the “H” level, and the equalizing signal EQ2
Is set to the “L” level, the NMOS transistor 35 and the PMOS transistor 19 are on. That is, the equalizing circuit 5 is activated. At time t0, the internal output enable signal intOE
In response to the “H” level, the equalizing signal E
Q1 goes to “L” level, and the equalize signal EQ2 goes to “H” level, so that the NMOS transistor 35 and the PMOS transistor 19 are turned off. That is, the equalizing circuit 5 is deactivated. Pull-up signal PA
Since 1 is at the “H” level, the PMOS transistors 23 and 21 are off. That is, the current supply circuit 7 is inactivated. The above is the description of the memory cell MC1
Pays attention to the equalizer circuit 5, the current supply circuit 7, the precharge circuit 9, and the connection / disconnection circuit 11 corresponding to the column in which is present, but the equalize circuit 5, the current supply circuit 7, the precharge circuit corresponding to other memory cells. Circuit 9 and connection /
The disconnection circuit 11 is also in the same state.

Next, the sense amplifier 15 before the start of the read operation
The state of the equalize / precharge circuit 17 will be described. Since the sense amplifier activation signal SA is at the “L” level, the NMOS transistor 49 is off and the sense amplifier 15 is inactive. The equalize / precharge signal EP1 is at “L” level, and the equalize / precharge signal EP2 is
Since it is at the “H” level, the PMOS transistors 29, 31, 33 and the NMOS transistor 51 are on, and the equalize / precharge circuit 17 is activated. Therefore, the potential of the data line pair D, / D is at the “H” level. Since the transistor activation signal TR is at the “L” level, the NMOS transistor 13 is off.

The state of the SRAM after the start of the read operation (after time t1) will be described with reference to FIGS.
Here, the memory cell MC1 is selected and the memory cell MC1 is selected.
Consider reading the information stored in 1. It is assumed that storage node SN1 is set at the “L” level and storage node SN2 is set at the “H” level. Time t
At 1, the potential of the word line WL is set to "H" level, and the access transistors Q3 and Q4 are turned on. At time t1, the column selection signal Y1 is set to “H” level,
Other column selection signals Y2 to Yn remain at the “L” level. Note that each of the column selection signals Y1 to Yn corresponds to each column. Then, only the column selection signal corresponding to the column to be selected becomes "H" level. Further, at time t1, the precharge signal PC1 is set to “L” level, so that the NMOS transistors 37 and 39 are turned off, and the precharge circuit 9 is deactivated.

At time t1, the pull-up signal PA1 is
Since it is set to “L” level, the PMOS transistor 2
3 and 21 are turned on, and the current supply circuit 7 is activated. Therefore, the bit line pair BL, / BL that has been precharged to the “L” level gradually becomes higher in potential. For this reason, the potential of the bit line BL is set to 0.6 V to 0.
When the voltage becomes about 8 V (voltage at which bipolar transistors BP1 and BP2 are turned on), a forward voltage is applied between emitter E and base B of bipolar transistor BP1 connected to storage node SN1 storing the "L" level of memory cell MC1. Is applied. Thereby, bipolar transistor BP1 is activated, and an emitter current flows.
Note that the potential of the bit line pair BL, / BL before the start of the read operation is set lower than the voltage level at which the bipolar transistors BP1, BP2 are turned on.

Here, the amount of current flowing from the bipolar transistor BP1 to the ground 3 and the current supply circuit 7
Depending on the relationship with the amount of current supplied to L, the bit line BL
Is determined. Bipolar transistor BP is connected to storage node SN1 set to the “L” level potential.
The potential of the bit line BL connected via 1 is pulled down to the “L” level by the bipolar transistor BP1. On the other hand, bipolar transistor BP1 is connected to storage node SN2 set to the “H” level potential.
The potential of the bit line / BL connected through is pulled up to the “H” level side by the current supply circuit 7.

At time t1, transistor activation signal TR is set to "H" level. Therefore, the NMOS transistor 13 turns on. On the other hand, at time t1,
The equalize / precharge signal EP1 is set to “H” level, and the equalize / precharge signal EP2 is
It is set to the “L” level. Therefore, the PMOS transistors 29, 31, 33 and the NMOS transistor 51 are turned off, and the equalize / precharge circuit 17 is deactivated. Here, after time t1, bit line B
The bit line which is at a higher level than the potential of L /
The NMOS transistor 43 whose gate is connected to BL is activated. Therefore, the potential of the data line / D set to the “H” level potential is pulled down to the “L” level side. On the other hand, the NMOS transistor 41 whose gate is connected to the bit line BL whose level is lower than the potential of the bit line / BL is inactive. Therefore, the potential of the data line D is maintained at the “H” level (precharge level).

A half latch circuit is formed by the NMOS transistors 41 and 43 and the PMOS transistors 25 and 27 corresponding to the column where the memory cell MC1 exists. Until time t2, the half latch circuit amplifies the potential difference between the data line pair D and / D. At time t2,
In other words, after the NMOS transistor 13 is turned on (after the transistor activation signal TR goes to “H” level), after a predetermined time has elapsed (so that the sense amplifier 15 does not perform erroneous reading, the data line pair D, After the potential difference of / D becomes sufficiently large), the sense amplifier activation signal SA is set to the “H” level. And the NMOS transistor 4
9 is turned on, and the sense amplifier 15 is activated.

The activated sense amplifier 15 has a data line D and a data line / D which are spread by a half latch circuit.
Is further amplified. Finally, the potential of the data line D is set to the level of the power supply voltage Vcc, and the data line /
The potential of D is set to the level of the ground voltage GND. Thus, the sense amplifier 15 generates a data line amplitude larger than the bit line amplitude. At time t3, word line WL, transistor activation signal TR, sense amplifier activation signal SA, and equalize / precharge signal E
P1 is set to “L” level, pull-up signal PA1, precharge signal PC1 and equalize / precharge signal EP2 are set to “H” level, and the read operation from memory cell MC1 is completed. Note that information from other memory cells than the memory cell MC1 is read out in the same manner as described above.

FIG. 4 shows an SRA according to an embodiment of the present invention.
FIG. 9 is a diagram for explaining a state of a non-selected column in an M read mode. Here, attention is paid to the column where the memory cell MC1 exists in FIG. 2, and the case where this column and the memory cell MC1 are not selected will be described. Word line WL connected to memory cell MC1 is at "L" level. The column selection signal Y1 corresponding to the selected column is at the “L” level. The potential of precharge voltage supply line PV is at "L" level. Internal output enable signal in
tOE is at “H” level, and internal write enable signal intWE is at “L” level. Since the equalizing signal EQ1 is at "L" level and the equalizing signal EQ2 is at "H" level, the NMOS transistor 35 and the PMOS transistor 19 are off. That is, the equalizing circuit 5 is inactivated. The pull-up signal PA1 is "H"
Level, the PMOS transistor 21,
23 is off. That is, the current supply circuit 7 is inactivated. Since the precharger signal PC1 is at “H” level, the NMOS transistors 37 and 3
9 is on. That is, the precharge circuit 9 is activated. Therefore, the potential of bit line pair BL, / BL is at "L" level. Here, the same applies to the case where other columns are not selected.

As described above, in the SRAM according to the embodiment of the present invention, the connection / disconnection connected to the bit line pair corresponding to the selected column (the bit line pair connected to the selected memory cell). Either the NMOS transistor 41 or 43 of the circuit 11 turns on. On the other hand, the bit line pair corresponding to the unselected column (the bit line pair connected to the unselected memory cells) is at the “L” level, and is connected to the bit line pair corresponding to the unselected column. Connection / disconnection circuit 11
Has been deactivated. Therefore, the data line D or /
D to supply the ground voltage GND to the transistor (N
It is only necessary to provide one MOS transistor 13) for all columns (all bit line pairs). Therefore, the circuit size of the SRAM according to the embodiment of the present invention can be smaller than that of the conventional SRAM of FIG.

The SRAM according to the embodiment of the present invention
In the example, one sense amplifier 15 is provided for a plurality of bit line pairs. That is, a plurality of data in a plurality of columns are received by one sense amplifier 15 at different times. Therefore, in the SRAM according to the embodiment of the present invention, the circuit configuration for reading is simplified.

In the SRAM according to the embodiment of the present invention,
The sense amplifier 15 is a latch type. Therefore, in the SRAM according to the embodiment of the present invention, a direct current does not flow and power consumption can be reduced.

In the SRAM according to the embodiment of the present invention,
NMOS transistors 41 and 4 corresponding to the selected column
3 and a half-latch circuit comprising PMOS transistors 25 and 27, the sense amplifier 15 is activated after the potential difference between the data line pair D and / D is increased. For this reason, in the SRAM according to the embodiment of the present invention, the influence of the offset of the driving force of the transistor on the sense amplifier is reduced.

FIG. 5 shows the first control signal generating circuit 4 of FIG.
FIG. 3 is a circuit diagram showing details of the embodiment. The same parts as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted as appropriate. With reference to FIG. 5, the first control signal generation circuit
R circuit 53, inverter 55, NAND circuits ND1 to ND
Dn, pull-up signal generation circuits CK1 to CKn, and a constant voltage generation circuit 49. Pull-up signal generation circuit C
K1 is an inverter 57, a PMOS transistor 61,
It consists of 63. Pull-up signal generation circuits CK2 to CKn
Has the same configuration. The constant voltage generation circuit 59
It includes a resistance element 73, PMOS transistors 65 and 67, and NMOS transistors 69 and 71.

The internal write enable signal intWE is input to one input node of the NOR circuit 53, and the internal output enable signal intO is input to the other input node.
E is input. An output node of the NOR circuit 53 is connected to the equalize signal supply line EQ1. Inverter 55
Is provided between the equalize signal supply line EQ1 and the equalize signal supply line EQ2. An internal output enable signal i is applied to one input node of the NAND circuit ND1.
ntOE is input, and the column selection signal Y1 is input to the other input node. The output node of NAND circuit ND1 is connected to precharge signal supply line PC1. N
The internal output enable signal intOE is input to one input node of the AND circuit NDn, and the column selection signal Yn is input to the other input node. NAND
The output node of the circuit NDn is connected to the precharge signal supply line P
Cn. Note that the other NAND circuits ND2 to ND
The same applies to Dn-1.

The connection of the elements constituting the pull-up signal generation circuit CK1 will be described. The inverter 57 includes a precharge signal supply line PC1 and a PMOS transistor 61.
Between the gates. PMOS transistor 6
1 is provided between a node to which power supply voltage Vcc is applied from power supply 1 and pull-up signal supply line PA1. PM
The OS transistor 63 includes a PMOS transistor 65,
67 and a pull-up signal supply line PA1, and the gate thereof is connected to a precharge signal supply line PC1.
1 is connected. Next, the pull-up signal generation circuit CKn
Will be described. Inverter 5
7 is provided between the precharge signal supply line PCn and the gate of the PMOS transistor 61. PMOS transistor 61 is provided between a node supplied with power supply voltage Vcc from power supply 1 and pull-up signal supply line PAn. The PMOS transistor 63 is connected to the gates of the PMOS transistors 65 and 67 and the pull-up signal supply line PA.
n, and the gate thereof is connected to the precharge signal supply line PCn. The same applies to the connection of the elements constituting the other pull-up signal generation circuits CK2 to CKn-1.

The connection of the elements forming the constant voltage generating circuit 59 will be described. Resistance element 73, PMOS transistor 65 and NMOS transistor 69 are connected in series between a node supplied with power supply voltage Vcc from power supply 1 and a node supplied with ground voltage GND from ground 3. PMOS transistor 67 and NMOS transistor 71 are connected in series between a node supplied with power supply voltage Vcc from power supply 1 and a node supplied with ground voltage GND from ground 3. PMOS transistor 65,
The gate of 67 is connected to the drain of NMOS transistor 71. The gates of the NMOS transistors 69 and 71 are connected to the drain of the NMOS transistor 69. The operation of the first control signal generation circuit in FIG. 5 will be described with reference to FIG. At time t0, when internal output enable signal intOE transitions to “H” level, internal write enable signal intWE
Is at the "L" level, the equalizing signal EQ1 output from the NOR circuit 53 transitions to the "L" level. The equalizing signal EQ2 is equal to the equalizing signal EQ1.
Is inverted by the inverter 55. Therefore, after time t1, equalize signal EQ2 output from inverter 55 attains "H" level.

A description will be given of a case before the read operation is started (time t0 to t1) in the read mode. Here, attention is paid to the column where the memory cell MC1 exists. Since the column selection signal Y1 is at "L" level and the internal output enable signal intOE is at "H" level, the precharge signal PC1 output from the NAND circuit ND1 is at "H" level. For this reason,
The PMOS transistor 63 is off. Meanwhile, PM
Since a signal obtained by inverting the precharge signal PC1 by the inverter 57 is supplied to the gate of the OS transistor 61, the PMOS transistor 61 is turned on. Thereby, the power supply 1 is connected to the pull-up signal supply line PA1.
Supplies the power supply voltage Vcc. That is, the pull-up signal PA1 is at the “H” level.

The case where memory cell MC1 is selected in the read mode (after time t1) will be described. At time t1, word line WL connected to memory cell MC1 is set to "H" level. At time t1, when the column selection signal Y1 transitions to the “H” level (when the column where the memory cell MC1 exists is selected),
Precharge signal PC1 output from ND circuit ND1
Transitions to the “L” level. Therefore, the inverter 5
The output of 7 becomes "H" level, and the PMOS transistor 61 is turned off. On the other hand, when the precharge signal PC1 goes to "L" level, the PMOS transistor 63 turns on. Thereby, constant voltage CV generated by constant voltage generation circuit 59 is applied to pull-up signal supply line PA1.
Since constant voltage CV is lower than power supply voltage Vcc, the potential of pull-up signal supply line PA1 is lower than before time t1. That is, at time t1, the pull-up signal generation circuit CK1 changes the pull-up signal PA1 to the “L” level.

Although the case where memory cell MC1 is selected has been described above, the other memory cells MC2 to MCn are selected.
Is selected, the first control signal generation circuit operates similarly.

FIG. 6 shows the second control signal generating circuit 6 of FIG.
FIG. 3 is a circuit diagram showing details of the embodiment. The same parts as those in FIG. 2 are denoted by the same reference numerals, and description thereof will be omitted as appropriate. Referring to FIG. 6, the second control signal generation circuit includes inverters 75, 77, 79, 81, 83, delay circuit 85,
87, 89, NAND circuits 91, 93 and a NOR circuit 95.

The input node of inverter 75 has ATD
A signal is input. The output node of the inverter is node N
Connected to 1. Delay circuit 85 is provided between nodes N1 and N2. The delay circuit 87 is connected to the node N2
And a node N3. Inverter 77 is provided between nodes N3 and N4. The first input node of the NAND circuit 91 is connected to the node N4,
The second input node is connected to the node N2, and the third input node has an internal output enable signal in.
tOE is input. The output node of NAND circuit 91 is connected to node N6. Inverter 79 is connected to node N
1 and a node N5.

One input node of NOR circuit 95 is connected to node N6, and the other input node is connected to node N5. The output node of the NOR circuit 95 is the inverter 81
Connected to the input node. The output node of inverter 81 is connected to equalize / precharge signal supply line EP2. Delay circuit 89 is provided between equalize / precharge signal supply line EP1 and node N7. Note that the equalize / precharge signal supply line EP1 is connected to the transistor activation signal supply line TR. N
The first input node of AND circuit 93 is connected to node N4, the second input node is connected to equalize / precharge signal supply line EP1, and the third input node is connected to node N7. The output node of NAND circuit 93 is connected to node N8. Inverter 83 is provided between node N8 and sense amplifier activation signal supply line SA.

FIG. 7 is a timing chart for explaining the operation of the second control signal generation circuit of FIG. Referring to FIGS. 6 and 7, delay circuits 85 to 89 are circuits for delaying the transition time to "H" level. In accordance with the rising edge of the ATD signal at time T1, the potential of node N1 transitions to "L" level. The potential of the node N2 transitions to the “H” level later than the potential of the node N1 by the delay circuit 85 (time T2). The potential of the node N3 changes to “H” level later than the potential of the node N2 by the delay circuit 87 (time T4). Node N4
At "L" in accordance with the rising edge of node N3.
Transition to a level. Here, in accordance with the rising edge of the potential of node N2 at time T2, the potential of node N6 transitions to "L" level. In accordance with the falling edge of the potential of node N6, the potential of transistor activation signal supply line TR and equalize / precharge signal supply line EP1
Transitions to the “H” level. In accordance with the rising edge of the potential of transistor activation signal supply line TR and the potential of equalization / precharge supply line EP1, transition of equalize / precharge signal supply line EP2 to "L" level.

The potential of node N7 is delayed by delay circuit 89 from the potentials of transistor activation signal supply line TR and equalize / precharge signal supply line EP1.
The state transits to the “H” level (time T3). In accordance with the rising edge of the potential of node N7 at time T3, node N8
Becomes "H" level. Then, in accordance with the falling edge of the potential of node N8, the potential of sense amplifier activation signal supply line SA attains "H" level. Therefore,
When the delay time of the delay circuit 89 elapses after the NMOS transistor 13 of FIG. 2 is turned on, the sense amplifier 15 of FIG.
Is activated.

In accordance with the rising edge of the potential of node N3 at time T4, the potential of node N4 transitions to "L" level. According to the falling edge of the potential of node N4,
The potential of node N6 transitions to "H" level. Node N
In accordance with the rising edge of the potential of No. 6, the potential of transistor activation signal supply line TR and the potential of equalize / precharge signal supply line EP1 transition to "L" level.
In accordance with the falling edge of the potential of the transistor activation signal supply line TR and the potential of the equalize / precharge signal supply line EP1, the potential of the equalize / precharge signal supply line EP2 transitions to the “H” level. Equalize /
In accordance with the falling edge of precharge signal supply line EP1, the potential of node N8 transitions to "H" level. In accordance with the rising edge of the potential of node N8, the potential of sense amplifier activation signal supply line SA transitions to "H" level.

As described above, in the SRAM according to the embodiment of the present invention, the connection / disconnection circuit 1 corresponding to the non-selected column
1 are all inactivated. Therefore, there is no need to provide a plurality of transistors (NMOS transistors 13) for supplying the ground voltage GND to the data lines D and / D corresponding to the plurality of connection / disconnection circuits 11. Therefore, in the SRAM according to the embodiment of the present invention, the circuit scale can be reduced.

[0058]

In the static semiconductor memory device according to the present invention, the connecting / disconnecting means corresponding to the non-selected column includes:
The pair of data lines and the voltage supply line are separated. For this reason, the voltage supply unit that supplies the second voltage to the voltage supply line can be shared by the plurality of connection / disconnection units. Therefore, the circuit scale can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing details of a memory cell of an SRAM according to an embodiment of the present invention;

FIG. 2 is a circuit diagram showing details of a peripheral portion of the SRAM according to the embodiment of the present invention;

FIG. 3 is a timing chart for explaining a read operation of the SRAM according to the embodiment of the present invention;

FIG. 4 is a diagram illustrating a state of a non-selected column in a read mode of the SRAM according to the embodiment of the present invention;

FIG. 5 is a circuit diagram showing details of a first control signal generation circuit of FIG. 2;

FIG. 6 is a circuit diagram showing details of a second control signal generation circuit of FIG. 2;

FIG. 7 is a timing chart for explaining the operation of the second control signal generation circuit of FIG. 6;

FIG. 8 is a circuit diagram showing details of a peripheral portion of a conventional SRAM.

FIG. 9 is a circuit diagram showing details of a conventional SRAM memory cell.

[Explanation of symbols]

1 power supply, 3 ground, 4 first control signal generation circuit, 5
Equalization circuit, 6 second control signal generation circuit, 7 current supply circuit, 9 precharge circuit, 11,98 connection / disconnection circuit, 13, 35 to 51, 69, 71, 99, 1
05 to 117 NMOS transistors, 15, 103 sense amplifiers, 17, 101 equalizing / precharge circuits, 19 to 33, 61 to 67, 123 to 129 PM
OS transistor, 53, 95 NOR circuit, 55, 5
7,75-83,119,121 Inverter, 59
Constant voltage generation circuit, 73 resistance element, 85-89 delay circuit, 91, 93 NAND circuit, SN1, SN2 storage node, BP1, BP2 bipolar transistor, Q
1, Q2 driver transistor, Q3, Q4 access transistor, R1, R2 high resistance element, MC1-MC
n, M1 to Mn memory cells, BL, / BL bit lines, D, / D data lines, EQ1, EQ2 Equalize signal supply lines (equalize signals), PV precharge voltage supply lines, GV ground voltage supply lines, PC1 to PCn Precharge signal supply line (precharge signal), SA sense amplifier activation signal supply line (sense amplifier activation signal), EP1, EP2 Equalize / precharge signal supply line (equalize / precharge signal), TR transistor activation signal Supply line (transistor activation signal), PA1 to PAn pull-up signal supply line (pull-up signal), CK1 to CKn pull-up signal generation circuit, ND1 to NDn NAND circuit, N1 to N8 nodes.

Claims (6)

[Claims] A plurality of memory cells arranged in a matrix of rows and columns; and a plurality of bit line pairs arranged corresponding to the respective columns and connected to the memory cells of the corresponding columns respectively. A pair of data lines to which a first voltage is applied; a voltage supply line to which a second voltage to be supplied to one of the pair of data lines is provided; A pair of data lines,
A plurality of connection / disconnection means for connecting or disconnecting the voltage supply line; and a voltage supply means for applying the second voltage to the voltage supply line, wherein each of the memory cells has two bipolar transistors. And two access transistors and two driver transistors, wherein the connection / disconnection means corresponding to the selected column is operated in accordance with information stored in the selected memory cell. A third voltage is connected to one of the pair of data lines and the voltage supply line, and a third voltage is applied to the bit line pair corresponding to the unselected column. The static semiconductor memory device, wherein the connection / disconnection means corresponding to a column disconnects the pair of data lines and the voltage supply line according to the third voltage. 2. Each of the connection / disconnection means includes two NMOs.
One of the NMOS transistors is provided between one of the pair of data lines and the voltage supply line, and has a control electrode connected to one of the bit lines of the corresponding bit line pair. The other of the NMOS transistors is provided between the other of the pair of data lines and the voltage supply line, and its control electrode is connected to the other bit line of the corresponding bit line pair. 2. The static semiconductor memory device according to claim 1, wherein a level of said third voltage applied to said bit line pair corresponding to said selected column is a level that can deactivate said NMOS transistor. 3. A plurality of equalizing means provided corresponding to each column, for equalizing the potential of one bit line and the potential of the other bit line of the corresponding bit line pair, A plurality of precharge means provided to apply the third voltage to the corresponding bit line pair, and a plurality of precharge means provided corresponding to each column and supplying current to the corresponding bit line pair Current supply means, a sense amplifier provided corresponding to the pair of data lines, amplifying a potential difference between the pair of data lines, and a data amplifier provided corresponding to the pair of data lines. And equalizing / precharging means for equalizing one potential of the data line and the other potential of the data line, and applying the first voltage to the pair of data lines. Item 2 Static semiconductor memory device of the mounting. 4. The sense amplifier is of a latch type.
The static semiconductor memory device according to claim 3. 5. The equalizing means and the precharging means corresponding to the selected column are inactivated, the current supply means corresponding to the selected column is activated, and after a read operation is started. The voltage supply means is activated, the read / write operation is started, the equalization / precharge means is deactivated, and the sense amplifier is activated after a lapse of a predetermined time after the voltage supply means is activated. The static semiconductor memory device according to claim 3, wherein: 6. The static circuit according to claim 3, wherein said precharge means corresponding to said unselected column is activated, and said current supply means corresponding to said unselected column is deactivated. Type semiconductor storage device.