JPH10143296A - Operation detecting method for arithmetic processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable the detection of an idle state in the case of performing arithmetic operation for a long time by detecting whether an arithmetic processor is in the idle state or not while detecting whether an access signal is a code signal or a data signal and utilizing whether the access signal hits a cache memory or not. SOLUTION: When the access operation by an arithmetic processing circuit 1 is a code signal, the signal level of a signal kind-classified signal output terminal 1A is turned to L level, and when the access operation of that is a data signal, that signal level is turned to H level. Besides, when access to the cache memory hits, a signal at the H level is outputted to a hit signal output terminal 2A provided at a cache memory control circuit 2. Namely, while detecting whether the access signal is the code signal or the data signal and utilizing a signal showing whether the access signal hits the cache memory or not, detecting operation is performed to show whether the arithmetic processor is in the idle state or not.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic processing device such as a personal computer, and more particularly to an operation detecting method for detecting whether the arithmetic processing device is in an operating state.

[0002]

2. Description of the Related Art Recently, an arithmetic processing unit called a personal computer, in particular, a notebook type personal computer which can be carried and used has become widespread. In such an arithmetic processing device, power consumption is a major problem because a battery is used as an operating power source. In a conventional device, when a signal from a keyboard or a mouse is not input for a predetermined time, a personal computer is in an inactive state. ,
That is, it is configured to determine that it is in the idle state and stop the operation of supplying power to unnecessary circuits or stop the operation itself.

[0003]

A method of detecting an idle state by using a signal from a keyboard or a mouse is described in I.
It is configured to monitor access to I / O, but it is also possible to use HD (hard disk) or FDD
(A floppy disk) by detecting an access operation for performing a signal recording / reproducing operation. However, when a long operation is continued, or when a large amount of data is transferred from memory to memory, the time without I / O access becomes longer, and is detected as a long idle state.
There has been a problem that the processing time is long or the processing is not performed.

An object of the present invention is to provide a method for detecting the operation of an arithmetic processing unit which solves the above problem.

[0005]

According to the present invention, an arithmetic processing unit having a cache memory and a power saving function detects whether an access signal is a code signal or a data signal and transmits the access signal to the cache memory. This is to detect whether or not the arithmetic processing unit is in an idle state by using whether or not a hit has occurred.

[0006]

FIG. 1 is a block circuit diagram showing an embodiment for explaining an operation detecting method according to the present invention. FIG. 2 is a block circuit showing a main part of an arithmetic processing unit incorporating the operation detecting method according to the present invention. FIG.

In FIG. 2, reference numeral 1 denotes an arithmetic processing circuit constituting a computer, which controls operations of a memory circuit, a hard disk device, a floppy disk device, and the like based on signals input from a keyboard, a mouse, and the like. A power saving function for stopping power supply to unnecessary circuits or stopping the operation itself when in a non-operation state is incorporated.

[0008] Reference numeral 2 denotes a cache memory control circuit whose operation is controlled by the arithmetic processing circuit 1 and in which a cache memory and a control circuit for controlling the memory are incorporated. 4 denotes an HD address for decoding an address of a hard disk drive; Reference numeral 4 denotes an FDD address for decoding the address of the floppy disk device.

An operation detecting circuit 5 according to the present invention is provided in the arithmetic processing circuit 1 and outputs a signal indicating whether a signal being accessed is a code (program) signal or a data signal. A signal type signal input terminal 5A connected to the signal type signal output terminal 1A and a signal provided in the cache memory control circuit 2 and indicating whether an access to the cache memory is hit is output. A hit signal input terminal 5B is connected to the hit signal output terminal 2A, and is configured to output a detection signal to an output terminal 5C when it is detected that the arithmetic processing device is in an operating state.

Reference numeral 6 denotes an OR circuit to which address signals from the HD address 3 and the FDD address 4 and a detection signal from the operation detection circuit 5 are input. Reference numeral 7 denotes an output signal of the OR circuit 6 to a reset terminal 7R. A timer circuit that is reset every time an H (high) level signal is applied, and is configured to output an H level signal to the output terminal 7P when the signal is not reset for a predetermined time. When an H-level detection signal is output to the output terminal 7P of the timer circuit 7, a control operation for power saving is performed by a control operation of the arithmetic processing circuit 1.

In the above-described circuit, when an operation of accessing a hard disk device or a floppy disk device is performed by operating a keyboard or a mouse, H
Since the H level signal from the D address 3 or the FDD address 4 is input to the reset terminal 7R of the timer circuit 7 via the OR circuit 6, the output terminal 7 of the timer circuit 7
The detection signal at the H level is not output to P, and the arithmetic processing operation by the arithmetic processing circuit 1 is performed.

Next, the operation detecting method of the present invention will be described with reference to the block circuit diagram shown in FIG. FIG. 1 shows the operation detection circuit 5 in FIG. 2, which is provided in the signal type signal input terminal 5A connected to the signal type signal output terminal 1A of the arithmetic processing circuit 1 and the cache memory control circuit 2. A hit signal input terminal 5B connected to the hit signal output terminal 2A is provided. In such a circuit, when the access operation by the arithmetic processing circuit 1 is a code (program) signal, the signal level of the signal type signal output terminal 1A becomes L (low) level, and when the access operation is a data signal, the signal level becomes H (low). It is configured to be a level. When an access to the cache memory is hit, a hit signal output terminal 2 provided in the cache memory control circuit 2
A high level signal is output to A.

In FIG. 1, reference numeral 8 denotes an oscillator for generating a reference signal, and reference numeral 9 denotes a time base signal generation circuit for generating a base time signal at predetermined time intervals based on the signal obtained from the oscillator 8. Reference numeral 10 denotes a gate control circuit that performs an opening / closing operation based on a signal output from the time base signal generation circuit 9;
When an L-level signal is input to A, that is, when an H-level signal is applied to the hit signal input terminal 5B when the access operation is a code signal, an H-level pulse signal is output to the output terminal. It is configured to be.

A counter circuit 11 counts the number of pulse signals output from the gate control circuit 10, and is configured to be reset by a signal from the time base signal generation circuit 9. Reference numeral 12 denotes a first latch circuit that latches a count value counted by the counter circuit 11 when a reset operation of the counter circuit 11 is performed by a signal from the time base signal generation circuit 9. Reference numeral 13 denotes a second latch circuit that latches the count value latched by the first latch circuit 12 when a reset operation of the counter circuit 11 is performed by a signal from the time base signal generation circuit 9. In such a circuit configuration,
The gate control circuit 10, the counter circuit 11, the first latch circuit 12, and the second latch circuit 13 constitute a code cache hit rate detection circuit 14.

Reference numeral 15 denotes a gate control circuit that performs an opening / closing operation based on a signal output from the time base signal generation circuit 9, and when a high level signal is input to the signal type signal input terminal 5A. That is, when an H-level signal is applied to the hit signal input terminal 5B when the access operation is a data signal, an H-level pulse signal is output to the output terminal.

Reference numeral 16 denotes a counter circuit for counting the number of pulse signals output from the gate control circuit 15, which is configured to be reset by a signal from the time base signal generation circuit 9. Reference numeral 17 denotes a first latch circuit that latches the count value counted by the counter circuit 16 when a reset operation of the counter circuit 16 is performed by a signal from the time base signal generation circuit 9. Reference numeral 18 denotes a second latch circuit that latches the count value latched by the first latch circuit 17 when the reset operation of the counter circuit 16 is performed by a signal from the time base signal generation circuit 9. In such a circuit configuration,
The gate control circuit 15, counter circuit 16, first latch circuit 17, and second latch circuit 19 constitute a data cache hit rate detection circuit 19.

Reference numeral 20 denotes the count values C0 and C1 which have been latched by the first latch circuit 12 and the second latch circuit 13 constituting the code cache hit rate detection circuit 15 and the first value constituting the data cache hit rate detection circuit 19. This is an arithmetic circuit that receives count values D0 and D1 latched by the latch circuit 17 and the second latch circuit 18 and performs an arithmetic operation based on an input signal. It is configured to output a signal to the output terminal 5C.

In the above-mentioned circuit, when the access operation of the arithmetic processing circuit 1 is an operation based on a code signal, an L-level signal is applied to the signal type signal input terminal 5A, which is in such a state. When an H-level signal output from the hit signal output terminal 2A of the cache memory control circuit 2 is applied to the hit signal input terminal 5B, a pulse signal is output from the gate control circuit 10 to the counter circuit 11. . Therefore, the number of pulses counted by the counter circuit 11 is the number of hits of the code signal to the cache memory.

When the access operation of the arithmetic processing circuit 1 is an operation based on a data signal, an H-level signal is applied to the signal type signal input terminal 5A. When an H-level signal output from the hit signal output terminal 2A of the memory control circuit 2 is applied to the hit signal input terminal 5B, a pulse signal is output from the gate control circuit 15 to the counter circuit 16. Therefore, the number of pulses counted by the counter circuit 16 is the number of hits of the data signal to the cache memory.

The hit number of the code signal counted by the counter circuit 11 is reset and latched by the first latch circuit 12 every time the signal from the time base signal generation circuit 9 is applied. Then, a counting operation in the next period is performed, and the number of hits during that period is counted by the counter circuit 11. The number of hits counted by the counter circuit 11 is latched by the first latch circuit 12 when a time base signal is output from the next time base signal generation circuit 9, and the hit number is stored in the first latch circuit 12 until then. The latched hit count is latched by the second latch circuit 13.

Similarly, the number of hits of the data signal counted by the counter circuit 16 is reset and latched by the first latch circuit 17 every time the signal from the time base signal generation circuit 9 is applied. Then, the counting operation in the next period is performed, and the number of hits during that period is counted by the counter circuit 16. The number of hits counted by the counter circuit 16 is latched by the first latch circuit 17 when the next time base signal is output from the time base signal generation circuit 9, and the hit number is stored in the first latch circuit 17 until then. The latched hit count is latched by the second latch circuit 18.

The code cache hit rate detection circuit 1
Latch Circuit 12 and Second Latch Circuit 1 Constituting 4
3 and the count values D0 and D1 latched by the first latch circuit 17 and the second latch circuit 18 constituting the data cache hit rate detection circuit 19 are input. The arithmetic processing operation for the operation detection by the circuit 20 is performed as follows.

In the circuit described above, the condition that the arithmetic processing circuit is in the idle state is that the absolute value (C1-C0) <CC and D1> D and D0> D and the absolute value (D1-D0) <CD
It is expressed as That is, the absolute value of C1-C0 indicates a change in the hit rate of the code signal, and the condition that the change in the hit rate is smaller than the predetermined value CC is that when many tasks are executed. The reason is that the hit rate may decrease because the cache memory capacity is limited, and even if the hit rate is low, the hit rate of the cache memory is not expected to change so much in a steady state. It is in.

If the access operation is data, it can be inferred that the hit rate for the cache memory is reduced.
The condition is that 1 and D0 are higher than a predetermined hit rate D. Further, the absolute value of D1-D0 indicates a change in the hit rate of the data signal (CD), and a small change in the hit rate is expressed as a condition that the arithmetic processing operation is not performed.

[0025]

The operation detecting method according to the present invention detects whether an access signal in an arithmetic processing unit is a code signal or a data signal and indicates whether or not the access signal hits a cache memory. Is used to detect whether or not the arithmetic processing device is in an idle state. Therefore, when an arithmetic operation for a long time is performed, that is, an operation without I / O access is performed. In this case, the idle state detection operation can be performed.

Further, according to the present invention, since the idle state detection operation is performed by measuring the hit rate of the access signal to the cache memory, the idle state detection operation can be accurately performed.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram showing an embodiment for explaining an operation detection method of the present invention.

FIG. 2 is a block circuit diagram showing a main part of an arithmetic processing device in which the operation detection method of the present invention is incorporated.

[Explanation of symbols]

 Reference Signs List 1 arithmetic processing circuit 2 cache memory control circuit 5 operation detection circuit 9 time base signal generation circuit 14 code cache hit rate detection circuit 19 data cache hit rate detection circuit 20 operation circuit

Claims (5)

[Claims] An arithmetic processing unit having a cache memory and a power saving function detects whether an access signal is a code (program) signal or a data signal and sends the access signal to the cache memory. And detecting whether the arithmetic processing unit is in an idle state using a signal indicating whether or not a hit has occurred. 2. The system according to claim 1, wherein a hit ratio for the cache memory is measured to detect whether or not the arithmetic processing unit is in an idle state.
3. The motion detection method according to 1. 3. The operation detecting method according to claim 1, wherein whether the arithmetic processing unit is in an idle state is detected by measuring a change in a hit ratio. 4. The operation detecting method according to claim 3, wherein whether the arithmetic processing unit is in an idle state is detected by measuring a change in a hit ratio of the code signal. 5. The operation detecting method according to claim 3, wherein whether the arithmetic processing device is in an idle state is detected by measuring a change in a hit ratio of the data signal.