JPH10136056A - Unit fault monitoring method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To monitor the unit fault of facing units in a device, without abnormality by means of the signal fault of the different unit in the fault monitoring system of the transmission device. SOLUTION: When a monitoring device 6 collects fault information from a device to be monitored, on which the plural units are mounted, a collection destination address table is provided and whether or not the units are in yet to be loaded state or the loading state prior to the fault information being collected. When they are not loaded, a processing for passing through a corresponding area in the collection destination address table is executed, and fault information is collected by using the collection destination address table when they are loaded.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fault monitoring method for a transmission device. In recent years, transmission devices have become complicated and large in capacity. Along with this, the internal configuration of the device is also divided into functions, and it has become common sense to provide a service as a transmission device by combining the packages divided into a plurality of units.

For this reason, fault monitoring of an apparatus is not simply considered for each unit, and accurate monitoring cannot be performed unless the situation of a plurality of units is handled in combination.

[0003]

2. Description of the Related Art FIG. 18 is an explanatory diagram of a conventional fault monitoring method, FIG. 19 is an example of a unit mounting explanatory diagram in a shelf, and FIG.
Is a flowchart of a collection process in a conventional example.

Hereinafter, FIGS. 18 to 20 will be described. First,
The fault monitoring in the transmission device checks the status of the transmission unit collected via the data bus as shown in FIG.
Determines whether there is an obstacle.

That is, the operating state of each transmission unit is sent to an area corresponding to a predetermined address of the input / output circuit. Therefore, the CPU accesses the specified area using the address determined for each transmission unit,
The on / off state and the value of the bit for the state of the target transmission unit, such as a failure, are detected to determine whether there is a failure.

Here, the monitoring items for the failure of the transmission device can be roughly classified into three. Transmission unit failure Line failure Transmission unit not mounted failure The transmission unit failure in the item is a failure of the unit itself. An example is an internal clock error or LSI failure. This fault can be detected by turning on / off a specific bit.

[0007] The line fault in the item is an abnormality of a main signal processed by the transmission device or an external clock signal, and can be detected by turning on / off a specific bit. The failure to mount the transmission unit in the item is determined by looking at the transmission unit specific code.

That is, when the transmission unit is not mounted,
The area indicating the status of the corresponding unit is set to 0 value and CP
Since it looks like U, it can be detected that the value that should be visible is 0.

In the case where the unit is not mounted, the state of the unit including the code unique to the transmission unit is all 0, so that the unit failure and the line failure are naturally cleared at the same time.

Incidentally, the above-mentioned line failure may repeatedly occur and recover in a short cycle depending on the quality of the line. A setting function is provided so that a specific bit is turned off by continuous recovery.

By setting this duration in the target unit, detection of occurrence and recovery of unnecessary trouble is guarded. The continuous monitoring time of the occurrence is called an activate time, and the continuous monitoring time of the recovery is called a deactivate time.

Further, as shown in FIG. 19, the transmission device is configured by mounting a number of units in a box called a shelf. These units include, for example, an interface processing unit for interfacing between units and a program, and include a main signal unit control unit and a main signal unit for monitoring the operation state of each main signal unit.

Here, the transmission device functions to take in a transmission signal and a clock signal from the outside into the unit, perform processing such as multiplexing and synchronization, and, in some cases, transmit the signal to the outside. At this time, a series of flow from input to processing to output is performed by many units.

Further, since the signal interface must be matched between the units, it is natural that the signal from the input unit to the processing unit may be interrupted due to the occurrence of a device failure.

[0015] The interruption of the signal can usually be detected on the receiving side, so that a fault occurs on the processing unit. By the way, such a problem or failure in the apparatus is treated as a unit failure because it is an abnormality inside the apparatus, and is naturally considered to be a unit that sends out a signal to the processing unit, that is, a unit failure of the input unit. It is.

Therefore, in the case described above, if a signal interruption in the apparatus is detected on the processing unit side, it must be treated as a unit failure of the input unit. Next, the procedure of the conventional fault information collection processing will be described with reference to FIG. 20, but the operation register of the CPU mounted on the main signal unit control unit in the unit shown in FIG.
A, register B.

First, register B is set to 0 in step S1. Then, in step S2, a counter J indicating the number of units
Is set to 0 and set to the beginning. Subsequently, in step S3, a counter I indicating the number of items collected in the unit is set to 0.

Subsequently, in step S4, the contents stored in the area indicated by the value of IO + counter I are stored in the register A. IO indicates the head address of each input / output circuit, and the contents of the area of the input / output circuit can be sequentially read out by increasing the value of the counter I and adding it to IO.

After accessing the input / output circuit with the value of the IO + counter I and storing the content in the register A, the stored content is stored in the area indicated by the CR + counter I in step S5. Since CR is a pointer of the status buffer and indicates the leading value, information of the input / output circuit is stored in the area indicated by the value of CR + counter I.

Subsequently, in step S6, the registers A and PR +
An exclusive OR XOR of the contents stored in the area indicated by the value of the counter I is obtained to obtain a difference value, and the obtained difference value is stored in the register A.

Incidentally, PR indicates a buffer for storing the contents of the previous IO. Then, in step S7, the content of register A is
XOR + Store in the area indicated by the value of the counter I.
That is, the presence or absence of a change is held.

Subsequently, in step S8, the result obtained by ORing the register A and the register B is stored in the register B. Subsequently, in step S9, the value of the counter I is obtained by adding 1 to the value of the counter I. That is, the value of the counter I is increased by 1 in order to collect the contents of the next item.

Subsequently, in step S10, the number of items I to be collected in the unit is compared with the value of NJ. If I is smaller than the value of NJ, the process returns to step S4 and the above process is repeated again. . However, if the number I of collected items in the unit is larger than the value of NJ, the process proceeds to step S11.

Subsequently, at step S11, the value of the counter J is incremented by one for the purpose of collecting the next unit, and is set as the value of the counter J. That is, the value of the counter J is increased for the collection of the next unit.

Subsequently, in step S12, the value of J is compared with the value of M. If the value of J is smaller than the value of M, the process returns to step S3 to repeat the above processing. However, if it is large, the process proceeds to step S13. That is, it is determined whether collection of all units is completed.

In step S13, it is determined whether or not the value of the register B is 0 (whether or not at least one has changed from the previous value). When it is determined that the value is not 0, the occurrence of a fault or This indicates recovery from a failure, and such a determination result is
S14 Send. Therefore, in step S14, a secondary mask process is performed as described later.

However, if it is 0, a determination that there is no change is sent to step S15. Therefore, in step S15, for example, about 10
After waiting for 0 ms, the collected value of the internal buffer is moved to the buffer (PR) storing the previous collected value, and the process returns to step S1.

Then, the above processing is repeated.

[0029]

FIG. 21 is an explanatory diagram of a problem. The conventional technology has the following problems. (1) When the input unit (UNIT) is disconnected, the signal is cut off in the processing unit as described above. Therefore, two failures, ie, a failure in mounting the input unit and a failure in the input unit, occur.

Normally, a unit failure occurs in a closed state inside the unit. Therefore, when the corresponding unit is removed, the IO value becomes 0 and no failure occurs. It is a problem that a unit failure that does not exist and does not exist occurs.

Hereinafter, description will be made with reference to FIG. In case (1),
There are two possible causes, (1) a and (1) b in FIG. (1) In the case of a, when the processing unit detects that a failure has occurred in the input unit, the processing unit must detect the failure. However, when the input unit is removed, monitoring should not be performed, but monitoring will cause a failure.
In other words, when the input unit is disconnected, the processing unit detects the input unit signal disconnection at the timing indicated by the dotted line immediately thereafter. However, even if a predetermined time has elapsed, the signal disconnection continues, so that a failure of the input unit is transmitted. (1) In the case of (b), the processing unit detects that a failure has occurred in the input unit and sends out a signal disconnection occurrence. Thereafter, even if the failed input unit is removed, the signal interruption is continuously transmitted. In the case of item (2), when a normal input unit is mounted and the state changes from the unmounted state to the mounted state, if the deactivate (DACT) time is set, the processing unit Bit is on. For this reason, a failure that may be unnecessary is detected. There is a problem called.

An object of the present invention is to enable a unit failure monitoring of a processing unit to be performed without error even when an input unit is disconnected.

[0033]

According to a first aspect of the present invention, a collection destination address table is provided when a monitoring device collects fault information from a monitored device in which a plurality of units are mounted.

Before collecting the failure information, it is checked whether the unit is in the unmounted state or the mounted state, and when the unit is not mounted, the unit passes through the corresponding area in the collection destination address table. No fault information is collected.

However, in the mounted state, the failure information is collected using the collection destination address table. According to a second aspect of the present invention, when a failure occurs in the own unit due to an address of an area where predetermined failure information is stored for each unit and a failure occurring in another unit in the above-mentioned collection destination address table, The address of the area of the other unit in which the failure information generated in the own unit is stored.

According to a third aspect of the present invention, there is provided mounting state change detecting means for detecting a change in the mounting state of the unit. And
Before collecting failure information, the mounting state change detection means
When detecting that the unit has changed from the unmounted state to the mounted state, the deactivate time and the activate time are once set to 0, and immediately returned to the set values.

That is, regarding the problem (1), since the unmounted device has a higher priority than the unit failure, the unit failure is not observed when the device is not mounted, or by providing a masking means, the unmounted device and the unit failure can be simultaneously performed. It was made to prevent occurrence. (1-1) When collecting faults from a unit, a collection destination address table is provided, and faults are collected based on the addresses on the table. (1-2) Further, when collecting a failure state from the unit, a signal interruption on the processing unit is registered as a failure of the input unit in a collection destination address table of the input unit. (1-3) Before collecting faults from the unit, check the mounting status of the unit. If it is not mounted, do not perform collection, and add processing to clear the collection destination address table.

As for the problem (2), immediately after mounting the input unit, the deactivate (deactivat
e) It is necessary to provide a means for masking the signal interruption failure that occurs during the time.

However, since there is a possibility that signal disconnection has actually occurred, simply masking is a problem. Therefore, (2-1) means for detecting that the input unit changes from not mounted to mounted is newly provided before collecting the fault on the unit. (2-2) If the input unit changes from not mounted to mounted by the above processing, the deactivate time is temporarily set to 0, and then processing for immediately returning to the original set value is added. Also, the activiate time, once
Return to 0 to return to the original value.

That is, (1-1) to (1-3) and (2-1), (2-
By using the means of item 2), the above problems (1) and
(2) can be solved.

[0041]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a diagram showing a main part of a transmission device monitoring system, FIG.
FIG. 3 is an explanatory diagram (part 1) of a collection destination address table according to the first and second embodiments of the present invention, and FIG. 4 is an explanatory diagram (part 2) of a collection destination address table according to the first and second embodiments of the present invention. FIG. 5 is a flowchart (part 1) of the collection processing of the first and second embodiments of the present invention.

FIG. 6 is a flowchart (part 2) of the collection process according to the first and second embodiments of the present invention. FIG. 7 is a flowchart (part 3) of the collection process according to the third embodiment of the present invention.
FIG. 14 is a flowchart (part 4) of a collection process according to the third embodiment of the present invention.

FIG. 9 is an explanatory diagram of all the processes relating to the fault monitoring, FIG. 10 is a flowchart of the collection process and the idle process (part 1), FIG. 11 is a flowchart of the collection process and the idle process (part 2), and FIG. It is a flowchart of a next mask process.

FIG. 13 is a flowchart of the data link construction process, FIG. 14 is a flowchart of the entire alarm determination process, FIG. 15 is a flowchart of the unit redundancy process and a flowchart of the line process, and FIG. 16 is a flowchart of the line pass process and the TSI pass process. flowchart,
FIG. 17 is a flowchart of the CH path processing.

Hereinafter, the present invention will be described in detail with reference to FIGS. First, as shown in FIG. 1, the transmission device monitoring system has a configuration in which a monitoring device (NMS) 6 monitors a plurality of transmission devices (NEs).

The transmission device 8 shown in FIG. 2 has a portion for detecting and processing a fault that has occurred on its own. The detected transmission fault information and device fault information are sent to the monitoring device 6 via the network 7 as a report. You will be notified.

Normally, the transmission apparatus is divided into an interface processing section for performing interface processing with the monitoring apparatus, a main signal unit control section for monitoring the state of the apparatus, a main signal unit, and the like.

As shown in FIGS. 3 and 4, the monitoring points of the unit, the processing unit, and the input unit are predetermined.
The addresses of these monitoring points are registered on the table. Therefore, at the time of collection, the corresponding address on this table is accessed to collect fault information.

However, the signal interruption on the processing unit is limited to the failure of the input unit which is monitoring the failure of the processing unit. Address ".

For example, when the processing unit detects a signal interruption of the input unit shown in the lower part of FIG. 4, the "address of the signal interruption failure of the processing unit" is registered in the table of the input unit (FIG. 4 * Mark).

Next, the processing using the table will be described with reference to FIGS.
This will be described with reference to the flowchart of FIG. First, the flowchart shown in FIG. 5 will be described. In the figure, step S23 is a part for performing the processing of the item (1-1) in the above means, and step S25 is a step (1-2)
This is the part that processes the term.

In step S21, the register B is set to 0, and then, in step S22, the counter J is set to 0 to match the beginning. Subsequently, in step 23, TJ indicating the unit collection destination address table is set in the pointer variable P.

Subsequently, in step S24, the counter I is set to 0, and in step S25, the contents stored in the area indicated by the value of P + counter I are stored in the register A. That is, data is collected from the destination indicated by the table.

Subsequently, in step S26, the contents stored in the register A are stored in the area indicated by CR + counter I.
Subsequently, the content stored in the register A in step S27,
An exclusive OR XOR of the contents stored in the area indicated by the value of PR + counter I is obtained to obtain a difference value, and this is stored in the register A.

Subsequently, in step S28, the contents stored in the register A are stored in the area indicated by XOR + the value of the counter I. That is, the presence or absence of a change is held. Subsequently, in step S29, the result obtained by calculating the logical sum of the contents stored in the registers A and B is stored in the register B.

Subsequently, at step S30, the value of the counter I is incremented by one.
Is the value of the counter I. That is, the value of the counter I is increased by 1 for the next item collection. Subsequently, in step S31, the magnitude of the value of the counter I and the value of NJ are determined.
If small (YES), the process returns to step S25 to repeat the above processing. However, the value of the counter I is larger than the value of NJ (N
If O), the process proceeds to step S32. The value of the counter I indicates the number of items collected in the unit.

In step S32, the value of the counter J is obtained by adding 1 to the value of the counter J for collecting the next unit. Subsequently, in step S33, the magnitude of the value of the counter J and the value of M are determined, and if the value of the counter J is small (YES), the flow returns to step S23 to repeat the above processing. However, if the value of the counter J is larger than the value of M (NO), step S34
Proceed to.

That is, in step S33, it is determined whether collection of all units is completed. Then, in step S34, register B
Is determined to be 0 (whether or not at least one has changed from the previous value). If the value is not 0, it indicates failure occurrence and failure recovery. send. Therefore, in step S35, a secondary mask process is performed as described later, and the processing result is sent to step S36. However, 0
If so, the determination of no change is sent directly to step S36.

Subsequently, in step S36, for example, about 100 ms
After waiting for a while, the contents of the internal buffer (CR) are transferred to the buffer (PR) where the previous contents are stored, and step S21 is performed.
Return to

Then, the above processing is repeated. The flowchart shown in FIG. 6 will be described. Step S43 and steps S56 to S59 in the figure correspond to the processing part (1-3) in the above means.

The register B is set to 0 in step S41, and the value of the counter J is set to 0 in step S42. Subsequently, in a step S43, it is determined whether or not the J unit is being mounted. If the judgment result is not implemented, the counter I is determined in step S56.
Is set to 0, the value of CR + counter I is set to 0 at step 57, and the value obtained by adding 1 to the value of counter I is set to counter I at step S58.

Subsequently, in step S59, the value of the counter I and N
It is determined whether the value of J is small. If the value is small, the process returns to step S57 to repeat the above processing. However, if the value of the counter I is N
If the value is larger than J, the process proceeds to step S51. If the determination result indicates that the unit is being mounted, the unit collection destination registration table TJ is set to the pointer variable P in step 44, and then the value of the counter I is set to 0 in step S45.

Subsequently, in step S46, the contents of the area indicated by the value of P + counter I are stored in the register A, and in step S47, the contents stored in the register A are stored in the area indicated by the value of CR + counter I. Store.

Subsequently, in step S48, a difference value obtained by taking an exclusive OR XOR between the content of the register A and the content stored in the area indicated by the value of the PR + counter I is obtained. To be stored.

Subsequently, in step S49, the contents of the register A are stored in the area indicated by XOR + the value of the counter I. The contents obtained by ORing the contents of register A with the contents of register B are stored in register B. The value obtained by adding 1 to the value of the counter I is defined as the value of the counter I.

Subsequently, at step S50, the value of the counter I and N
It is determined whether the value of J is small or large.
And the above processing is repeated. However, if the value of the counter I is larger (NO) than the value of NJ, the process proceeds to step S51.

In step S51, a value obtained by adding 1 to the value of the counter J is set as the value of the counter J. Subsequently, in step S52, the magnitude of the value of the counter J is compared with the value of M. If the value is smaller than (YES), the process returns to step S43 to repeat the above processing, and if larger (NO), step S5
Proceed to 3.

In step S53, it is determined whether or not the content of the register B is 0. If not (NO), a secondary mask process is performed in step S54, and then the process proceeds to step S55. However, 0
If (YES), the process directly proceeds to step S55.

In step S55, for example, after waiting for processing for about 100 ms, the contents of the internal buffer (CR) are transferred to the buffer (PR) in which the previous contents are stored, and the process returns to step S43.
The above process is repeated.

That is, in step S43, it is determined whether or not the J-th unit is mounted. If not, no collection is performed, and in steps S56 to S58, processing for skipping NJ bytes of the CR table is added. I do.

The reason for performing such a process is that there is no effect since collection is performed even if the unit has been omitted in the related art.
However, in the present invention, as described above, there has been a case where an input unit failure is handled due to a signal interruption of the processing unit, and thus such processing is added.

Thus, the problem (1) can be solved. The flowcharts shown in FIGS. 7 and 8 will be described. Steps S62 to S64, S75, and S7 in FIG.
6 is the processing part of paragraph (2-1), and steps S65 to 67 are
This is the processing part of the section (2-2).

Now, in step S61, register B is set to 0,
The value of the counter J is set to 0. Subsequently, in a step S62, it is determined whether or not the J unit is being mounted. If the result of determination is not implemented, it is determined in step S75 whether the unmounted unit is an input unit. If it is an input unit (YES), the variable CS is set to 1 in step S76, but not (NO). If so, step S76 is passed.

Subsequently, the value of the counter I is set to 0 in step S77.
Then, in step 78, the value of CR + counter I is set to 0, then in step S79, the value obtained by adding 1 to the value of counter I is set in counter I, and then, in step S80, counter I is set.
The value of NJ and the value of NJ are determined. If the value is small (YES), the process returns to step S78 to repeat the above processing. However, large (N
If O), the process proceeds to step S70. If the determination result is mounting, it is determined in step S63 whether the mounting unit is an input unit. If the mounting unit is an input unit (YES), it is determined in step S64 whether the value of the variable CS is 1 or not, If CS = 1, it indicates that the input unit has not been mounted the previous time, so in step S65 deactivate and
Activate is set to 0 for each moment, and then returned to the set value.

Subsequently, at step S66, the variable CS is set to 0 to bring the input unit into a mounted state, and then at step S67 T
J is set to the pointer variable P, and the value of the counter I is set to 0.

Subsequently, in step S68, the contents of the area designated by the value of P + counter I are stored in register A,
Is stored in the area indicated by the value of CR + counter I, and the contents of register A and the content stored in the area indicated by the value of PR + counter I are XORed.
Then, the difference value is calculated and stored in the register A.

The contents of the register A are stored in the area indicated by the value of XOR + counter I.
OR the contents of B into register B and the value of counter I
The value obtained by adding 1 is used as the value of the counter I.

Subsequently, at step S69, the value of the counter I and N
The magnitude of the value of J is determined, and if the value is small (YES), step S68
And the above processing is repeated. If it is large (NO), the value obtained by adding 1 to the value of the counter J in step S70 is
Then, in step S71, the magnitude of the value of the counter J is compared with the value of M. If the value of the counter J is smaller than the value of M (YES), the flow returns to step S61 to repeat the above processing. If it is large (NO), the process proceeds to step S72.

In step S72, it is determined whether or not the content of the register B is 0. If not (NO), a secondary mask process is performed in step S73, and then the process proceeds to step S74. However, 0
If (YES), the flow directly proceeds to step S74.

In step 74, for example, after waiting for processing for about 100 ms, the contents of the internal buffer (CR) are transferred to the buffer (PR) in which the previous contents are stored, and the flow returns to step S61. That is, in steps S62, S75, and S76, the unit mounting state processing is performed to maintain the state of the input unit, and in steps S63, S63,
In S64, a process of detecting a change in the next process is added, and in Step S65, a process of instantly setting the deactivate and the activate time to 0 is provided.

As described above, by setting deactivate to 0 for a moment before collecting information, if the line disconnection has been recovered, it is possible to recover the line disconnected failure state and treat the information collection as having no failure. Become.

However, if a line disconnection has occurred, deactiva
Even if te is set to 0, the fault condition is not cleared, so that it can be handled as occurrence at the time of information collection. 9 to 17 will be described.

In FIG. 9, when the status information is collected from the input / output circuit 15, the XOR (exclusive OR) circuit 16 compares the status information read from the previous collection table 19 with the status information collected from the input / output circuit 15. XOR the result and the result is
In addition to storing the result in the XOR table 18, the logical sum of the obtained XOR result is stored in the XOR OR value memory 17.

The status information collected this time is stored in the current collection table 20. In the above collection process, XO
When 0 is stored in the OR value memory 17 of R, it indicates that there is no previous change, and the subsequent processing is not performed.

When the OR value memory 17 of XOR is not 0, secondary mask processing is performed. In the secondary mask processing, the information stored in the secondary mask pattern memory 21 and the current collection table
The logical product with the state information stored in 20 is taken by the AND circuit 22 and stored in the secondary mask table 23 this time.

Then, the XOR circuit 25 compares the information stored in the secondary mask table 23 this time with the previous secondary mask table.
The exclusive OR with the information stored in 24 is calculated, the result is stored in the XOR table 26, and the OR value memory of XOR
27 stores the sum of the exclusive OR.

If the content of the OR value memory 27 of this XOR is 0, the next data link construction processing is omitted. However, if the content of the OR value memory 27 of the XOR is not 0, data link construction processing is performed.

The result obtained by this data link construction processing first indicates to the generated data link AX that the information pointed to by the data link AX is occurring A.
The occurring A has the fault information and the next pointer, and points to the occurring B here. Outbreak B and outbreak C, recovery D, new E, etc. are also pointed out sequentially.

When the information of the signal that has been generated C is recovered, the recovery D is pointed to the recovery data link AY, and this link configuration is deleted from the generated data link AX.

For example, when it is determined that a failure has occurred by the above-described secondary mask processing, the new
The information of E is linked to the last position of the generated data link AX. After such a data link construction process is performed, data on the link is processed by an alarm determination process and an external output process is executed.

Although the flow of all the processes has been described with reference to FIG. 9, each process will be described in more detail below. “Flowchart of Collection Processing and Idle Processing” in FIGS. 10 and 11
Will be briefly described because they are the same as those in FIGS.

First, the register B and the counter J are set to 0 in step S91, and it is determined in step S92 whether the J unit is mounted (YES) or not (No). If No, it is determined in step S105 whether or not the input unit. If YES, CS is set to 1 in step S106, and if No, step
The processing in S106 is omitted.

At step S107, I is set to 0, and at step S108
To set CR + counter I to 0, and set I + 1 to 1 in step S109.
In step S110, the magnitude of I and NJ is determined, and I is NJ
If it is smaller (YES), the process returns to step S100, and if it is larger (NO), the process returns to step S108, and the above processing is repeated.

On the other hand, if step S92 is YES, step S93 is an input unit, and if step S94 is CS = 1, deactivate and activate are temporarily set to 0 in step S95, and are returned to the set values. In step S97, P is set to TJ and I is set to 0 in step S97. In step S98, the contents of (P + I value) are stored in register A, the contents of register A are stored in (CR + I), and the contents of register A XOR ( After storing the contents of (PR + I value), the contents of register A in (XOR + I), and the contents of register A OR register B in register B,
Perform processing to set I + 1 to I.

If it is not I <NJ in step S99 (NO), J + 1 is set to J in step S100, J is larger than M in step S101 (NO), and if the register B is not 0 in step S102,
In step S103, a secondary mask process is performed, and in step S104, a process of transferring contents from CR to PR is performed after waiting for a predetermined time.

FIG. 12 is a flowchart of the secondary mask processing in the above-described collection processing. First, step S121
Creates a secondary mask pattern, sets the register B to 0 in step S122, and sets the value of the counter I to 0 in step S123.

Subsequently, in step S124, the value of CR + counter I is stored in register A. In step S125, the logical product of the content of register A and the value of MP + counter I, that is, the value in which the mask pattern is stored, is obtained. In step S126, the contents of register A are stored in CR2 + counter I. In step S127, the exclusive OR of the contents of register A and the contents obtained in the previous master pattern is obtained. In step S128, the contents are stored in the area of the value of XOR2 + counter I.

Subsequently, in step S129, the logical sum of the register A and the register B is obtained and stored in the register B.
At step 130, the value of the counter I is incremented by one. At step S131, it is determined whether or not the value of the counter I is smaller than the N value. When the value is smaller (YES), the process returns to step S124 to repeat the above processing.

However, at step S131, the value of the counter I is
When it becomes larger than N (NO), the register is set in step S132.
Determine if B is 0 or not. Register B is 0 (YES)
If, processing is terminated, but register B is not 0 (NO)
At this time, a data link construction process is performed in step S133, an alarm determination process is performed in step S134, and the result is further performed in an external output process step S135. Then, the entire process ends.

In FIG. 13, the value of the counter I is set to 0 in step S141, the value of XOR2 + counter I is stored in the register A in step S142, and the value of the register A is set to 0 in step S143.
It is determined whether or not.

If the value of the register A is not 0, it is determined that there is a change, and the content stored in the area of the value of CR2 + the value of the counter I is stored in the register A in step S144, and it is determined whether or not the register A is 0 in step S145 I do.

This is for judging whether an alarm has occurred or the alarm that has occurred has recurred. When the determination is not 0, the counter I is determined in step S146.
Is performed at the end of the generated data link. If the alarm data is 0, an alarm indicated by the counter I is obtained from the generated data link in step S147.

In step S148, the alarm indicated by the counter I is removed from the generated data link.
In S149, the alarm indicated by the counter I is connected to the end of the recovery data link, and in step S150, registers A and PR2
+ Exclusive OR with counter I and store it in register A.

When the value of the register A is 0 in step S143, and when the processing in steps S146 and S150 is completed, the value of the counter I is incremented by 1 in step S151.
In S152, it is determined whether the value of the counter I is smaller than N, and
If (YES), the flow returns to step S142 again to repeat the above processing.

The above-described step S146 is for connecting to a link to data, steps S147 to S150 are for disconnecting the link, and further, processing for connecting to the end of the restored data link. In FIG. 14, the group flag, the line flag, and the pass flag are cleared in step S161, a process to be performed twice is instructed in step S162, and an instruction to perform the generated data link is issued in step S163.

In step S164, the type of data link alarm is determined. If the target alarm is the alarm, unit redundancy processing is performed in step S165. If the target alarm is alarm, the line processing is performed in step S166, and then the line bus processing is performed in step S167.

If the target alarm is detected, the TSI process is performed in step S168. If the target alarm is detected, the DICH process is performed in step S169. This process is performed twice for all data. By repeating these two times, for example, it is possible to determine what the connection destination is, and it is possible to perform a highly accurate determination that has not been obtained conventionally.

In FIG. 15, the unit redundancy processing is the same as the processing for each check, and is a judgment for each unit. First, it is determined in step S171 whether the group flag is 1 or not. If it is 1, the target alarm is determined to be a failure (SA) that causes a failure in the transmission service, and the flag is set to 1. If not, it is determined in step S172 whether or not there is a redundant configuration.
Judge as SA.

However, if the configuration is redundant, step S173
It is determined whether or not the unit is operating. If the unit is operating, it is determined in step S174 that the target alarm is SA, but if the unit is not operating, the process ends. By the above processing
The flag 1 determined as SA can be obtained.

In FIG. 16, at step S181, a process to be performed at all the connection destinations is instructed. At step S182, it is determined whether the connection destination has a pass or line flag of 1.
Determines in step S183 whether or not PSR is Y. If it is Y, it determines in step S184 whether or not path operation is in progress. If it is not in path operation (N), nothing is performed.

However, when the connection destination path or line flag is 1 in step S182 (Y), when PSR is not Y in step S183 (N), and when the path is operating in step S184 (Y), step S185 is performed. Then, the target alarm is determined to be SA, and the connection flag is set to 1.

In FIG. 17, it is determined whether or not the own path is 1 in step S191. If the own path is not 1 (N), the process proceeds to step S192.
Determines if PSR is Y, and if Y, steps
In S193, it is determined whether the path is operating or not. If the path is not operating (N), the target alarm is NSA (Non Se
rvice Affect: a failure that is relieved by the redundancy function in the transmission device and does not affect the transmission service).

However, in step S191, the own path flag is set to 1
(Y), when the PSR is not Y in step S192 (N), and when the path is operating (Y) in step S193,
In S195, the target alarm is determined to be SA, and the connection flag is set to 1.

Note that the LINE processing shown in FIG.
And the TSI processing is the same as the LINE pass processing shown in FIG. this is,
ALM is only for units, ALM for LI
This is because it is related to the NE path.

[0115]

As described in detail above, by using the method of the present invention, it becomes possible to monitor the unit failure of the opposing unit in the apparatus without abnormality due to the signal interruption failure of another unit. There is an effect.

[Brief description of the drawings]

FIG. 1 is a main component of a transmission device monitoring system.

FIG. 2 is an explanatory diagram of a main part of a transmission device monitoring system.

FIG. 3 is an explanatory diagram (part 1) of a collection destination address table according to the first and second embodiments of the present invention.

FIG. 4 is an explanatory diagram (part 2) of a collection destination address table according to the first and second embodiments of the present invention.

FIG. 5 is a flowchart (part 1) of a collection process according to the first and second embodiments of the present invention.

FIG. 6 is a flowchart (part 2) of a collection process according to the first and second embodiments of the present invention.

FIG. 7 is a flowchart (part 3) of a collection process according to the third embodiment of the present invention;

FIG. 8 is a flowchart (part 4) of a collection process according to the third embodiment of the present invention;

FIG. 9 is an explanatory diagram of all processes related to fault monitoring.

FIG. 10 is a flowchart (part 1) of a collection process and an idle process.

FIG. 11 is a flowchart (part 2) of a collection process and an idle process.

FIG. 12 is a flowchart of a secondary mask process.

FIG. 13 is a flowchart of a data link construction process.

FIG. 14 is a flowchart of the entire alarm determination process.

FIG. 15 is a flowchart of a unit redundancy process and a flowchart of a line process.

FIG. 16 is a flowchart of a line pass process and a flowchart of a TSI pass process.

FIG. 17 is a flowchart of a CH path process.

FIG. 18 is an explanatory diagram of a conventional fault monitoring method.

FIG. 19 is an example of a unit mounting explanatory view in a shelf.

FIG. 20 is a flowchart of a collection process in a conventional example.

FIG. 21 is an explanatory diagram of a problem.

[Explanation of symbols]

 Reference Signs List 6 monitoring device 7 network 8 transmission device 15 input / output circuit 16, 25 XOR (exclusive OR) circuit 17 XOR OR value memory 18 XOR table 19 previous collection table 20 current collection table 21 secondary mask pattern 22 AND (logical product) ) 23 Secondary mask this time 24 Previous secondary mask

Claims (3)

[Claims] When a monitoring device collects fault information from a monitored device in which a plurality of units are mounted, a monitoring destination address table is provided, and before the fault information is collected, whether the unit is in a non-mounted state is determined. In the mounted state, perform processing to pass through the corresponding area in the collection destination address table, and in the mounted state, collect failure information using the collection destination address table. A unit failure monitoring method, characterized in that: 2. When a failure occurs in the own unit due to an address of an area where predetermined failure information is stored for each unit in the collection destination address table and a failure occurring in another unit, 2. The unit fault monitoring method according to claim 1, wherein the fault information generated in the unit is stored with an address of an area of the other unit. 3. A mounting state change detecting means for detecting a change in the mounting state of the unit, wherein the mounting state change detecting means comprises:
When detecting that the unit has changed from the unmounted state to the mounted state, the deactivate time and the activate time are temporarily set to 0, and immediately returned to the set values. 2. The unit fault monitoring method according to claim 1, wherein: