JPH10136044A - Automatic frequency control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an automatic frequency control circuit which can highly precisely control the pull-in of a frequency without a clock synchronization. SOLUTION: A fixed pattern detection circuit 110 monitors the delay detection output of a delay detection circuit 100 and detects the fixed pattern reception of a burst signal. An offset detection circuit 130 obtains the addition average of delay detection output and obtains the offset (frequency error) of delay detection output from a difference between the addition average and the addition average (ideal value) of delay detection output with respect to the fixed pattern without a frequency error, which has been set previously. A switch 140 inputs offset to an adder 120, when fixed pattern reception is detected in the fixed pattern detection circuit 110. On the other hand, the adder 120 removes the offset delay detection output.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic frequency control circuit used for demodulating a received signal in a digital radio apparatus or the like that performs communication using a burst signal of a phase modulation method having a preamble.

[0002]

2. Description of the Related Art In a digital radio apparatus for performing burst communication, clock synchronization is performed by using a fixed pattern included in a preamble portion of a burst signal as shown in FIG. Control and frequency pull-in control (frequency control corresponding to an unknown frequency error between the own device and the other device) are performed. This frequency pull-in control is performed by an automatic frequency control circuit.

A conventional automatic frequency control circuit is, for example, shown in FIG.
It is configured as shown in FIG. A phase-modulated wave signal S (t) having a specific phase corresponding to transmission data for each symbol period is
It is received from space and input to the differential detection circuit 800.

The delay detection circuit 800 includes an instantaneous phase detection circuit 801 and a delay circuit (T) as shown in FIG.
802 and an adder 803. The phase modulated wave signal S (t) is input to the instantaneous phase detection circuit 801.

[0005] The instantaneous phase detection circuit 801 detects the phase of the phase modulated wave signal S (t), and outputs the detected phase to the delay circuit 8.
02 and the first input terminal of the adder 803. The delay circuit 802 delays the phase by the symbol period T, and inputs the delayed signal to the second input terminal of the adder 803. The adder 803 subtracts the phase input to the second input terminal from the phase input to the first input terminal, and outputs the result of the subtraction as a delayed detection output R (t). Here, assuming that the amplitude is A, the carrier angular frequency is ωc, and the time series of phases allocated according to the differentially decoded transmission code is θ (t), the phase modulated wave signal S (t) is

[0006]

(Equation 1) It can be expressed as. On the other hand, the delay detection circuit 800
The differential detection output R (t) of

[0007]

(Equation 2) Becomes And

[0008]

(Equation 3) Assuming that

[0009]

(Equation 4) Becomes

When differential encoding is performed during transmission, the transmission code can be decoded from the differential detection output R (t). If the carrier angular frequency when there is an error in the carrier frequency is ωc + Δω, the differential detection output R
(T) is expressed by the following equation.

[0011]

(Equation 5)

That is, according to the delay detection circuit 800,
The frequency error of the carrier between the transmitter and the receiver is the differential detection output R
Appears as an offset of (t). The delay detection output R (t) obtained as described above is output to a subsequent signal processing unit (not shown) after an offset described later is subtracted by an adder 810, and is also subjected to code point offset detection. The signal is input to the circuit 820.

The code point offset detection circuit 820 utilizes the fact that the differential detection output R (t) at the symbol timing ideally takes only a few specific values (code points) to obtain the offset (frequency error). Is to be detected.

FIG. 10 shows a code point offset detection circuit 82.
In the example of the configuration of 0, the case of detecting the offset of the burst signal of the BPSK method shown in FIG. 12 will be described. In FIG. 12, a solid line waveform shows an ideal (no frequency error) differential detection output R (t), and a dotted line waveform shows an actual differential detection output R (t) with a frequency error.

The code point determination circuit 821 determines which code point (0 or π) the differential detection output R (t) at the symbol timing (nT, (n + 1) T, (n + 2) T,...) Is close to. The code point determination result is added to the adder 8
22 is input to a second input terminal.

The adder 822 subtracts the code point determination result input to the second input terminal from the differential detection output R (t) input to the first input terminal, thereby obtaining the signal shown in FIG.
The above frequency error (offset E (nT), E
｛(N + 1)｝ T, E ｛(n + 2)｝ T,...

The offset (frequency error) detected in this way is amplified by an amplifier 830 shown in FIG. 8, then averaged by an averaging circuit 840 and input to an adder 810. The adder 810 subtracts the offset from the differential detection output R (t) as described above, and inputs the result of the subtraction to the code point offset detection circuit 820 and a signal processing unit at the subsequent stage.

As described above, in the conventional automatic frequency control circuit, the code point offset detection circuit 820 detects the offset of the delay detection output R (t), and removes the detection result from the delay detection output, thereby transmitting and receiving. The frequency error of the carrier wave between machines is corrected.

As shown in FIG. 11, the burst signal has a time constraint that both the clock synchronization control and the frequency pull-in control must be completed before the reception of the information portion following the preamble portion. The control can be performed only after the clock synchronization is established because the symbol timing is used as described above. For this reason, in some cases, there is a possibility that the information section may be received before sufficient frequency pull-in is performed.

In the prior art, for example, the gain of the amplifier 830 is increased to reduce the time constant of the feedback loop so that the pull-in operation can be performed in a short time. However, this method makes the pull-in operation unstable. A new problem has arisen.

[0021]

In the conventional automatic frequency control circuit, there is a time constraint that both the clock synchronization control and the frequency pull-in control must be sequentially completed before the reception of the information section. Otherwise, the frequency pull-in control cannot be performed, so that depending on the state of the received signal, there is a problem that much time is spent on the clock synchronization control, and there is a possibility that the frequency pull-in control cannot be sufficiently performed.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and has as its object to provide an automatic frequency control circuit capable of performing frequency pull-in control with high accuracy even without clock synchronization. .

[0023]

In order to achieve the above object, an automatic frequency control circuit according to the present invention comprises an automatic frequency control circuit for performing frequency control using known data contained in a burst signal of a phase modulation system. A delay detecting means for detecting a phase of the burst signal at a timing based on a symbol cycle, obtaining a difference between a current phase and a phase before a predetermined symbol cycle, and outputting the result as a delayed detection output; Frequency error detection means for adding the delay detection output detected by the detection means and calculating a frequency error generated in the burst signal from a difference between the addition result and a preset ideal value; and a frequency error detection means for the delay detection output. And a frequency error correcting means for correcting the frequency error obtained in the above.

The automatic frequency control circuit having the above configuration focuses on the fact that an offset due to a frequency error appears in the differential detection output. First, the phase difference (delay detection output) obtained by the delay detection means is added within a unit time. Then, for example, an addition result (ideal value) in the case where no frequency error has occurred is obtained in advance, and the difference between the obtained ideal value and the addition result obtained during operation is removed from the differential detection output to perform correction. I do it.

Therefore, according to the automatic frequency control circuit having the above structure, the frequency error is obtained by comparing the addition results for the unit time, so that the frequency error is obtained even if the clock is not synchronized. Corrections can be made.

Further, the automatic frequency control circuit according to the present invention includes a frequency error level monitoring means for monitoring the level of the frequency error obtained by the frequency error detection means, and the frequency error correction means comprises a frequency error level monitoring means. Only when it is determined that the error level is lower than a preset reference level, the frequency error obtained by the frequency error detection means is corrected for the delayed detection output.

The automatic frequency control circuit having the above structure focuses on the fact that the level of a frequency error that can occur in a desired burst signal can be predicted to some extent. Set it. Then, a large value that cannot be expected to be detected when an offset is detected from data obtained by performing delay detection on an unnecessary signal may be obtained. This means that the data handled was not what was desired. By not correcting the frequency error at this time, it is possible to prevent a frequency pull-in operation for an unnecessary signal.

The automatic frequency control circuit according to the present invention sets a result obtained by adding a delay detection output of the delay detection means to known data for a unit time as the ideal value, and monitors the delay detection output. And delay detection output monitoring means for determining whether or not delay detection has been performed on a burst signal containing known data, wherein the frequency error correction means determines whether the delay detection output monitoring means has a delay with respect to the burst signal containing known data. When it is determined that the detection has been performed, the frequency error obtained by the frequency error detection means is corrected for the delayed detection output.

In the automatic frequency control circuit having the above configuration, a frequency error is obtained from an ideal value based on known data, and when it is determined that delay detection has been performed on a burst signal containing known data, the frequency error is corrected. I do it.

Therefore, according to the automatic frequency control circuit having the above-described configuration, it is possible to prevent a frequency pull-in operation from being performed on an irrelevant signal that does not include known data, and even if clock synchronization has not been established. It is possible to correct a frequency error that constantly occurs in a desired burst signal including known data.

Further, the automatic frequency control circuit according to the present invention determines the sign of the delay detection output using a clock synchronized with the symbol clock, and determines the burst signal from the difference between the sign determination result and the delay detection output before the sign determination. A code point frequency error detecting means for obtaining a frequency error generated in the delay detection output monitoring means, and a code point frequency error detection means for the delayed detection output when the delay detection output monitoring means determines that delay detection has been performed on a burst signal containing known data. Means for correcting the frequency error obtained by the detection means.

In the automatic frequency control circuit having the above configuration, the sign of the differential detection output is determined using a clock synchronized with the symbol clock, and a burst signal is generated from the difference between the sign determination result and the delay detection output before the code determination. Find the frequency error. Then, when it is determined that the delay detection has been performed on the burst signal including the known data, the frequency error is corrected.

Therefore, according to the automatic frequency control circuit having the above-described configuration, the frequency error that occurs steadily is detected and corrected based on the known data of the burst signal, and based on the sign determination result of the delayed detection output. Frequency pull-in can be performed by correcting a frequency error that occurs unsteadily after clock synchronization.

Further, in the automatic frequency control circuit according to the present invention, when the frequency error correction means corrects the frequency error obtained by the frequency error detection means with respect to the delay detection output, the frequency error is held and the delay detection is performed. It is characterized in that the output is corrected.

Therefore, according to the automatic frequency control circuit having the above configuration, when correcting the frequency error, the frequency error is held and the delay detection output is corrected, so that the unknown data follows the known data, for example. Even for the information part of the burst signal, it is possible to correct the frequency error that occurs steadily.

Further, the automatic frequency control circuit according to the present invention calculates a delay detection circuit for generating an output proportional to a phase difference of a phase-modulated wave for each predetermined symbol period, and calculates an offset of an average of outputs of the delay detection circuit. An offset detection circuit that holds a calculation result for a predetermined period; a subtractor that subtracts the output of the offset detection circuit from an output of the delay detection circuit; and a fixed pattern detection circuit that detects a known fixed pattern from the output of the delay detection circuit And a switch that opens and closes a path for inputting the output of the offset detection circuit to the subtractor according to the output of the fixed pattern detection circuit, and outputs a delayed detection output corrected by the subtractor when the switch is closed. It is characterized by doing.

In the automatic frequency control circuit having the above configuration, when a known fixed pattern is detected, the held offset is subtracted from the output of the delay detection circuit to control the frequency of the delay detection output. ing.

Therefore, according to the automatic frequency control circuit having the above configuration, the offset obtained from the fixed pattern before the detection of the fixed pattern can be used for the frequency control of the differential detection output.

Further, the automatic frequency control circuit according to the present invention has an offset level monitoring means for monitoring the offset level obtained by the offset detection circuit, and when the level of the offset is smaller than a preset reference level by the monitoring means. When it is determined, the offset obtained by the offset detection circuit is corrected for the output of the delay detection circuit.

Usually, the frequency error that occurs in the desired signal is
A signal having an excessively large frequency error is not a desired signal because it is known in advance that the frequency is in an approximate range. The present invention focuses on this point,
Since the frequency control is performed only when the offset is smaller than the reference level, it is possible to prevent an unnecessary signal from being followed.

[0041]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a first embodiment of an automatic frequency control circuit according to the present invention will be described with reference to the drawings. FIG. 1 shows the configuration. This automatic frequency control circuit includes a delay detection circuit 100, a fixed pattern detection circuit 110, an adder 120, an offset detection circuit 130, and a switch 140.

The delay detection circuit 100 detects the phase difference between one symbol period by performing delay detection on the received phase modulation signal. Then, the phase difference detected by the delay detection circuit 100 is input to the fixed pattern detection circuit 110 and the first input terminal of the adder 120 as a delay detection output. Note that the delay detection circuit 100
Has the same configuration as that of the conventional differential detection circuit 800 shown in FIG. 9, and thus a detailed description of the configuration will be omitted.

The fixed pattern detection circuit 110 monitors whether or not the received signal contains a fixed pattern of the burst signal based on the delay detection output. For example, as shown in FIG. Fixed pattern storage circuit 202, correlator 203, level comparator 2
04.

The shift register 201 stores the differential detection output for a predetermined number of samples, and inputs the data stored for each symbol timing to the correlator 203 in parallel.

The fixed pattern storage circuit 202 stores, for example, R
It is composed of a semiconductor memory such as an OM, and stores in advance the differential detection output when the fixed pattern included in the burst signal is received by the predetermined number of samples.

The correlator 203 is a fixed pattern storage circuit 2
02 and the shift register 20
The actual differential detection output input in parallel from 1 is compared with each sample for each sample to obtain a correlation. Here, the obtained correlation value is input to a synchronization control circuit (not shown) and used for establishing clock synchronization.
04 is input.

When the above-mentioned correlation value exceeds a preset threshold level th1, the level comparator 204
A fixed pattern detection signal is output assuming that the fixed pattern has been detected. This fixed pattern detection signal is input to the offset detection circuit 130 and the control terminal of the switch 140.

The adder 120 subtracts the later-described offset inputted to the second input terminal from the differential detection output inputted to the first input terminal. The result of the subtraction is output to a signal processing unit (not shown) at the subsequent stage and is also input to the offset detection circuit 130.

The offset detection circuit 130 includes the adder 12
In order to detect an offset (frequency error) based on the delay detection output via 0, for example, as shown in FIG. 3, a cumulative adder 301, an averaging circuit (1 / n) 302, a subtractor 303, And a register 304.

The accumulator 301 accumulatively adds the delayed detection output from the adder 120 by n samples, and inputs the addition result to the averaging circuit 302. This averaging circuit 302 divides the delay detection output cumulatively added by the cumulative adder 301 by n. That is, the differential detection output via the adder 120 is averaged by the accumulator 301 and the averaging circuit 302. The averaged differential detection output is input to a first input terminal of the subtractor 303.

As described above, the subtracter 303 has the first input terminal to which the averaged differential detection output is input, and the second input terminal to which the average value of the averaged differential detection output is input. You. Here, the ideal value of the averaged differential detection output indicates a value obtained by averaging the differential detection output obtained by delay-detecting a fixed pattern having no offset (no frequency error).

Then, by subtracting the average value of the averaged differential detection output inputted from the second input terminal from the averaged differential detection output inputted from the first input terminal, the actual delay is obtained. Find the difference (offset) between the detection output and the ideal value. This offset is input to the register 304.

The register 304 temporarily stores the offset. When a fixed pattern detection signal is input from the fixed pattern detection circuit 110, the register 304 holds and outputs the offset at that time. Register 304
Is output to the input terminal of the switch 140.

When the fixed pattern detection signal is input to the control terminal, the switch 140 short-circuits the input terminal and the output terminal, and inputs the offset to the second input terminal of the adder 120.

Next, the operation of the automatic frequency control circuit having the above configuration will be described. The delay detection output detected by the delay detection circuit 100 is
And whether or not a fixed pattern of the burst signal is included is monitored.

The delay detection output is input to the offset detection circuit 130 via the adder 120, and the average of the delay detection output is obtained. Then, by calculating the difference between the obtained average and the average (ideal value) when there is no frequency error, an offset is obtained and stored in the register 304.

Eventually, upon receiving the desired burst signal,
When a fixed pattern is detected, the fixed pattern detection circuit 1
10, the fixed pattern detection signal is the offset detection circuit 1
30 and the control terminal of the switch 140.

On the other hand, the switch 140 short-circuits the input terminal and the output terminal. Further, the offset detection circuit 13
“0” outputs and holds the offset currently stored in the register 304. Then, this offset is input to the second input terminal of the adder 120 via the switch 140.

In the adder 120, the offset is canceled from the delay detection output obtained by the delay detection circuit 100. Thereafter, while the burst signal is being received, the offset is maintained, and a delay detection output without a frequency error is output to the subsequent signal processing unit.

As described above, in the automatic frequency control circuit having the above configuration, the offset detection circuit 130 calculates the addition average of the delay detection output, and calculates the addition average when there is no frequency error set in advance. The offset of the differential detection output is obtained from the difference from the ideal value.

As described above, since the offset is detected from the averaging, the offset can be detected even if the clock synchronization is not established. Therefore, the frequency pull-in control is performed in parallel with the clock synchronization when receiving the preamble portion. Can be performed. That is, it is possible to sufficiently perform the frequency pull-in of the delay detection output without being subjected to the time constraint by the clock synchronization control.

In the above embodiment, when a fixed pattern of a burst signal is detected, the detected offset is held, and the frequency pull-in operation is started using this offset. It is possible to remove a frequency error that occurs steadily, and also to prevent tracking of an unnecessary received signal.

Next, a second embodiment according to the present invention will be described with reference to FIG. FIG. 4 shows the configuration, which focuses on the fact that the offset detected from the delayed detection output of unnecessary burst signals and noise tends to take a large value. In this embodiment, a switch 410 and a level comparator 420 are added to the automatic frequency control circuit shown in FIG.

In the first embodiment, the fixed pattern detection signal of the fixed pattern
In contrast to direct input to the control terminal of 0,
In the present embodiment, the fixed pattern detection signal is
The control signal is input to the control terminal of the switch 140 via the switch 10.

The level comparator 420 compares the offset detected by the offset detection circuit 130 with a preset threshold level th2, and when the offset is smaller than the threshold level th2, the level of the switch 4
10 is controlled to be in an ON state. Note that the threshold level th2 is set based on the maximum offset amount that can occur in the received desired burst signal.

Therefore, according to the automatic frequency control circuit having the above structure, even if a fixed pattern is erroneously detected from unnecessary burst signals or noise, the level comparator 420 has an offset larger than the threshold level th2. , Switch 410 is not short-circuited.

As a result, the fixed pattern detection signal is not input to the control terminal of the switch 140, and the switch 140 remains open, so that the frequency pull-in operation for an unnecessary received signal can be prevented.

On the other hand, when the fixed pattern is detected from the desired burst signal, the switch 410 is short-circuited because the offset is smaller than the threshold level th2. As a result, the switch 140 is also short-circuited, the offset is input to the adder 120, and the frequency pull-in operation is performed.

Next, a third embodiment according to the present invention will be described with reference to FIG. FIG. 5 shows the configuration, in which a feedback loop surrounded by a chain line is added to the automatic frequency control circuit shown in the first embodiment.

This feedback loop is connected to the switch 5
8 and an adder 810, a code point offset detection circuit 820, an amplifier 830, and an averaging circuit 840 shown in FIG.

The code point offset detection circuit 820 has the first
The delay detection output output from the automatic frequency control circuit shown in the embodiment is input. Then, as described in detail in the section of the prior art, the code at the symbol timing of the differential detection output is determined, and the offset is detected by subtracting the determination result from the differential detection output. This offset is input to the input terminal of the switch 500.

The switch 500 outputs an offset input from the code point offset detection circuit 820 when the fixed pattern detection signal of the fixed pattern detection circuit 110 is input to the control terminal. The offset output from the switch 500 is amplified by the amplifier 830, averaged by the averaging circuit 840, and input to the adder 810.

The adder 810 includes the delay detection circuit 100,
The offset is provided between the fixed pattern detection circuit 110 and the adder 120, and subtracts the offset from the delay detection output from the delay detection circuit 100. The result of the subtraction is input to the fixed pattern detection circuit 110 and the adder 120, respectively.

In the automatic frequency control circuit having the above configuration, the first
According to the configuration described in the first embodiment (the configuration surrounded by a broken line in FIG. 5), an offset that is constantly present in a received signal detected during reception of a fixed pattern is canceled. The above-described feedback loop makes it possible to cancel an offset that occurs unsteadily due to, for example, a temperature change or noise.

Therefore, according to the automatic frequency control circuit having the above-described configuration, not only the offset which is constantly present in the burst signal due to the configuration surrounded by the broken line but also the burst signal after receiving the fixed pattern due to the configuration surrounded by the dashed line The offset which occurs irregularly during the reception of the information section can be removed.

The present invention is not limited to the above embodiment. For example, in the above embodiment, the offset detection circuit 130 has been described with the configuration shown in FIG. 3, but an offset detection circuit having the configuration shown in FIG. 6 may be used instead. The offset detection circuit 13 shown in FIG.
For 0, an n-stage shift register 601 and an n-stage adder 602 are provided instead of the accumulator 301.

The n-stage shift register 601 is composed of n shift registers and stores the delay detection output of n samples. Each time a new delay detection output is input, the delay detection output stored in each register is represented by n. A parallel input is made to the stage adder 602. On the other hand, the n-stage adder 602 calculates n
The n differential detection outputs input from the stage shift register 601 are added and input to the averaging circuit 302. Even with such a configuration, similar data can be obtained because data obtained by cumulatively adding the differential detection outputs of n samples can be obtained as in the case of the cumulative adder 301.

Further, the offset detecting circuit 130 is provided in FIG.
May be used. The offset detection circuit 130 shown in FIG.
1 and an averaging circuit 302, a p-sample accumulator 701, an m-stage shift register 702, an m-stage adder 7
03 and an averaging circuit 704 are provided.

A p-sample accumulator 701 accumulates and adds the differential detection output by p samples and outputs the sum to m
Input to the stage shift register 702. The m-stage shift register 702 is composed of m shift registers, and stores m cumulative addition results of the p-sample cumulative adder 701. Each time a new cumulative addition result is input, it is stored in each register. The result of the cumulative addition is input to the m-stage adder 703 in parallel.

On the other hand, the m-stage adder 703 adds the m cumulative addition results input from the m-stage shift register 702 and inputs the result to the averaging circuit 704. Averaging circuit 70
4 divides the addition result of the m-stage adder 703 by (p × m), and averages the differential detection outputs of p × m samples.

According to this configuration, it is possible not only to obtain the cumulative average of the differential detection output as in the case of using the cumulative adder 301 and the averaging circuit 302, but also to set the number of registers of the m-stage shift register 702 to n. It can be 1 / p of the stage shift register 601.

In the above embodiment, offset detection and offset removal are performed by the feedback loop. However, it goes without saying that the same effect can be obtained by the feedforward loop.

Further, in the above-described embodiment, the setting of the ideal value in the offset detection circuit 130 uses the averaging result of the delay detection result with respect to the fixed pattern of the burst signal. On the other hand, for example, when the data of the information section of the burst signal is, for example, an audio signal, if the data is subjected to delay detection and averaging, the data tends to approach a predetermined value. If an ideal value is set by paying attention to this point, a frequency error can be obtained based on the data of the information section, and the frequency error constantly occurring in the burst signal can be corrected. It goes without saying that various modifications can be made without departing from the spirit of the present invention.

[0084]

As described above, according to the present invention, the addition result of the phase difference (delay detection output) obtained by the delay detection means within a unit time and the frequency error previously obtained do not occur. The frequency error generated in the burst signal is detected by comparing the addition result (ideal value), and the correction is performed.

Therefore, according to the present invention, the frequency error is obtained by comparing the result of adding the phase difference. Therefore, even if the clock is not synchronized, the automatic frequency can be corrected. A control circuit can be provided.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing a configuration of a first embodiment of an automatic frequency control circuit according to the present invention.

FIG. 2 is a circuit block diagram showing a configuration of a fixed pattern detection circuit of the automatic frequency control circuit shown in FIG.

3 is a circuit block diagram showing a configuration of an offset detection circuit of the automatic frequency control circuit shown in FIG.

FIG. 4 is a circuit block diagram showing a configuration of a second embodiment of the automatic frequency control circuit according to the present invention.

FIG. 5 is a circuit block diagram showing a configuration of a third embodiment of the automatic frequency control circuit according to the present invention.

6 is a circuit block diagram showing another configuration example of the offset detection circuit of the automatic frequency control circuit shown in FIG.

FIG. 7 is a circuit block diagram showing another configuration example of the offset detection circuit of the automatic frequency control circuit shown in FIG.

FIG. 8 is a circuit block diagram showing a configuration of a conventional automatic frequency control circuit.

FIG. 9 is a circuit block diagram showing a configuration of a delay detection circuit of the conventional automatic frequency control circuit shown in FIG.

FIG. 10 is a circuit block diagram showing a configuration of a code point offset detection circuit of the conventional automatic frequency control circuit shown in FIG.

FIG. 11 is a diagram illustrating a configuration of a burst signal at the start of communication.

FIG. 12 is a signal waveform diagram for explaining detection of an offset generated in a burst signal of the BPSK method.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 delay detection circuit 110 fixed pattern detection circuit 120, 810 adder 130 offset detection circuit 140, 410, 500 switch 201 shift register 202 fixed pattern storage circuit 203 correlator 204, 420 level comparator 301 ... Accumulator 302 ... Averaging circuit (1 / n) 303 ... Subtractor 304 ... Register 601 ... N-stage shift register 602 ... N-stage adder 701 ... P-sample cumulative adder 702 ... M-stage shift register 703 ... m Stage adder 704: Averaging circuit 820: Code point offset detection circuit 830: Amplifier 840: Averaging circuit

Claims (9)

[Claims] An automatic frequency control circuit for performing frequency control using known data included in a burst signal of a phase modulation method, wherein the phase of the burst signal is detected at a timing based on a symbol period, and a current phase and a predetermined phase are detected. A phase difference before the symbol period is obtained, a phase difference detection means for outputting the phase difference as a phase detection output, and a phase detection output detected by the phase detection means within a unit time are added, and this addition result is set in advance. Frequency error detecting means for obtaining a frequency error generated in the burst signal from the difference between the ideal value and the frequency error correcting means for correcting the frequency error obtained by the frequency error detecting means with respect to the delayed detection output. An automatic frequency control circuit characterized by: 2. A frequency error level monitoring means for monitoring a frequency error level obtained by said frequency error detection means, wherein said frequency error correction means sets said frequency error level in advance by said frequency error level monitoring means. 2. The automatic frequency control circuit according to claim 1, wherein when it is determined that the frequency difference is smaller than the reference level, the frequency error obtained by the frequency error detection means is corrected for the differential detection output. 3. A method in which a result obtained by adding a delay detection output of the delay detection means to the known data for a unit time is set as the ideal value, and whether delay detection is performed on a burst signal including the known data. A delay detection output monitoring unit that determines whether or not the delay detection output monitoring unit has performed the delay detection when the delay detection output monitoring unit determines that the delay detection has been performed on the burst signal including the known data. 2. The automatic frequency control circuit according to claim 1, wherein a frequency error obtained by said frequency error detection means is corrected for an output. 4. A code determination is performed on the differential detection output using a clock synchronized with a symbol clock, and a frequency error generated in the burst signal is obtained from a difference between the code determination result and the differential detection output before code determination. Code point frequency error detection means, and when the delay detection output monitoring means determines that delay detection has been performed on the burst signal including the known data, the code point frequency error detection means 4. The automatic frequency control circuit according to claim 3, further comprising means for correcting the obtained frequency error. 5. The frequency error correction means, when correcting the frequency error obtained by the frequency error detection means with respect to the delay detection output, corrects the delay detection output while holding the frequency error. 4. The automatic frequency control circuit according to claim 3, wherein: 6. A delay detection circuit for generating an output proportional to a phase difference of a phase-modulated wave for each predetermined symbol period, calculating an offset of an average of outputs of the delay detection circuit, and holding the calculation result for a predetermined period. An offset detection circuit, a subtracter for subtracting an output of the offset detection circuit from an output of the delay detection circuit, a fixed pattern detection circuit for detecting a known fixed pattern from an output of the delay detection circuit, A switch that opens and closes a path for inputting an output to the subtractor in accordance with the output of the fixed pattern detection circuit, wherein when the switch is closed, the differential detection output is output from the subtractor. Features automatic frequency control circuit. 7. An offset level monitoring means for monitoring an offset level obtained by said offset detection circuit, wherein said delay is provided when said monitoring means determines that said offset level is smaller than a preset reference level. 7. The automatic frequency control circuit according to claim 6, wherein an offset obtained by said offset detection circuit is corrected for an output of a detection circuit. 8. The automatic frequency control circuit according to claim 6, wherein a shift register is used for calculating the averaging of said offset detection circuit. 9. The automatic frequency control circuit according to claim 6, wherein a cumulative adder is used for calculating an average of said offset detection circuit.