JPH10135350A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To rectify a bias of a threshold value voltage in a CMOS circuit. SOLUTION: The threshold value voltages of an N-channel type semiconductor device is separately controlled from a P-channel type semiconductor device, by utilizing a decrease in the threshold value voltage due to a narrow channel effect and an increase in the threshold value voltage due to a narrow channel effect. At this time, the threshold value voltage of the N-channel type semiconductor device is increased and the threshold value voltage of the P-channel type semiconductor device is decreased, so as to make the absolute values of both threshold value voltages almost equal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD [0001] The invention disclosed in the present specification is:
The present invention relates to a semiconductor device using a semiconductor film having crystallinity and a manufacturing method thereof. In particular, the present invention relates to a semiconductor device having a CMOS structure using a single crystal silicon film as a semiconductor film.

[0002]

2. Description of the Related Art In recent years, CMOS technology using an insulated gate transistor has been actively developed. However, as described in JP-A Nos. 4-206971 and 4-286339, the electrical characteristics of an N-type transistor having a crystalline silicon film as an active layer shifts in the depletion direction (negative side). , P-type transistor in the enhancement direction (negative side)
Tend to shift. This is considered to be due to a difference in work function between the gate electrode and the active layer due to a difference in conductivity type.

FIG. 2 shows a schematic diagram of the electrical characteristics (Id-Vg characteristics) of the above-described transistor. The horizontal axis Vg is the gate voltage, and the vertical axis Id is the drain current. 201 is N
202 shows the characteristics of a P-type transistor. In addition, shown by 201 and 202
The contact where the Id-Vg characteristic is in contact with the Vg axis indicates the threshold voltage.

Here, what is indicated by 203 is the window width (Vwin), which is the threshold voltage (Vth, n) of the N-type transistor and the threshold voltage (Vth) of the P-type transistor.
th, p) (= Vth, n-Vth, p). Also,
Reference numeral 204 denotes a window center (Vcen), which is defined by the center value of the window width (= 1/2 Vwin).

At this time, the window width (Vwin) of the conventional CMOS circuit is shifted to the negative side as a whole, and as a result, the window center (Vcen) becomes 0 V or less. JP-A-4-
According to Japanese Patent No. 206971, the bias of the output voltage due to the difference in the threshold voltage causes the characteristics of the CMOS circuit to deteriorate.

As a solution to this problem, there is a method of controlling the threshold by adding an impurity (phosphorus or boron) imparting one conductivity to the channel forming region (hereinafter, referred to as a channel doping method). However, in this method, there is a problem that the impurity ions cause carrier scattering and cause a reduction in operation speed.

In particular, in the deep submicron region where the channel length is 0.01 to 0.1 μm, the number of impurity ions existing in the channel region is one to several, so that the electric characteristics may be totally changed by the presence of the impurity ions. It has been reported.

[0008]

2. Background of the Invention Here, it is necessary to mention the short channel effect suppression technique (pinning technique) proposed by the present inventors. The outline is described below with reference to FIG.

The short channel effect is a general term for a decrease in threshold voltage, a decrease in withstand voltage due to a punch-through phenomenon, and a decrease in sub-threshold characteristics. Further, these phenomena occur because the depletion layer on the drain side extends to the source region, which makes it difficult to control carriers only by the gate voltage.

That is, a technique for suppressing the spread of the depletion layer on the drain side is a pinning technique, which can be achieved by artificially and locally providing an impurity region in a channel formation region. The present inventors use the term "pinning" to mean "deterrence".

Specifically, the active region of the transistor is shown in FIG.
The structure is as shown in FIG. In FIG. 3A, reference numeral 301 denotes a source region, 302 denotes a drain region, and 303 denotes a channel formation region. In the channel formation region 303, an impurity region 304 is artificially formed. In the channel formation region 303, a region 305 other than the impurity region 304
Is a substantially intrinsic region, which is a region where carriers move.

The impurity region 304 is obtained by forming a fine pattern by an electron drawing method or the like. Although FIG. 3A shows an example in which the impurity region is formed in a linear pattern shape, the impurity region may be formed in a dot-like dot pattern shape.

FIG. 3B is a sectional view of FIG. 3A taken along the line AA '. Reference numeral 306 denotes a field oxide film for separating the elements from each other, and reference numeral 307 denotes a channel stopper. FIG. 3C is a cross-sectional view of FIG. 3A taken along a line BB ′.

At this time, the impurity region 304 disposed in the channel formation region 303 locally forms a region having a high diffusion potential (energy barrier) in the channel formation region.
Then, the energy barrier can effectively suppress (pin) the spread of the drain side depletion layer to the source side.

The impurity region 304 contains oxygen, nitrogen,
Addition of any of carbon can form a sufficient energy barrier. For an N-type transistor, B
(B) may be added to P (phosphorus) if it is a P-type transistor.

With the above-described configuration, it is expected that a decrease in the threshold voltage, which is one of the short channel effects, can be effectively suppressed. Of course, it is also possible to suppress the deterioration of the breakdown voltage and the sub-threshold characteristic due to the punch-through phenomenon.

The configuration shown in FIG. 3 is expected to produce a narrow channel effect separately from the above-described effects. That is,
By making the interval between the impurity regions 304 sufficiently narrow, a narrow channel effect can be artificially generated in the region 305 where carriers move.

As described above, the pinning technique proposed by the present inventors is limited to the extent that a short channel effect occurs (a channel length of 2 μm or less) and to a finer sub-micron region (a channel length of 0.01 to 0.1 μm). μm) device technology.

However, the shift of the window center (Vcen) due to the difference in work function between the gate electrode and the active layer, as described in the conventional example, is a phenomenon that occurs similarly in the pinning technique. Therefore, in the submicron region, it is necessary to control the threshold voltage while suppressing the short channel effect.

[0020]

SUMMARY OF THE INVENTION The present invention corrects a difference in threshold voltage by a method other than the channel doping method in a CMOS circuit miniaturized to such an extent that a short channel effect can occur (0.01 to 2 .mu.m). The task is to provide technology.

In other words, the window center (Vce
n) is provided with a technique for approaching 0V as much as possible. This means that the control is performed so that the absolute values of the threshold voltages of the N-channel type and P-channel type semiconductor devices are substantially the same.

[0022]

SUMMARY OF THE INVENTION The gist of the present invention is to provide a short channel effect (Short channel effect) caused by miniaturization of device elements.
Channel Effect (SCE) and Narrow Channel Effect (Nallow)
Channel Effect: threshold voltage (V) using NCE
th) to correct the difference in Vth of the CMOS circuit.

Therefore, the structure of the invention disclosed in this specification is a semiconductor device having a CMOS structure in which an N-channel semiconductor device and a P-channel semiconductor device are complementarily combined. The N-channel semiconductor device is provided with means for strengthening the narrow channel effect so that the absolute value of the threshold voltage of the P-channel semiconductor device becomes substantially the same. The means for strengthening is provided.

More specifically, impurity regions are artificially and locally arranged in the channel forming regions of the N-channel semiconductor device and the P-channel semiconductor device substantially in parallel with the channel direction. Means for intentionally narrowing the arrangement interval of the impurity regions arranged in the N-channel semiconductor device, and means for enhancing the short-channel effect means the arrangement arranged in the P-channel semiconductor device. The method is characterized in that the arrangement interval of the impurity regions is relatively wider than the arrangement interval in the N-channel semiconductor device.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An N-channel type semiconductor device and a P-type semiconductor device which are problematic in manufacturing a semiconductor device having a CMOS structure are described.
The difference in the absolute value of the threshold voltage of a channel type semiconductor device is corrected by a new means not based on the channel doping method.

Therefore, the threshold voltage of the N-channel semiconductor device and the threshold voltage of the P-channel semiconductor device are separated by utilizing the decrease in the threshold voltage due to the short channel effect and the increase in the threshold voltage due to the narrow channel effect. Shift to

The structure in which the narrow channel effect appears strongly can be achieved by using the pinning technique to narrow the interval between the impurity regions arranged in the channel forming region, that is, to increase the pinning effect. Conversely, if the distance between the impurity regions is designed to be wider, the pinning effect is weakened, and the short channel effect is stronger.

[0028]

【Example】

[Embodiment 1] In this embodiment, a CMO using an insulated gate transistor (IGFET) utilizing a pinning technique is used.
An example in which the structure of the active region is different between an N-type transistor and a P-type transistor when designing an S circuit will be described.

As described in the conventional example, when the channel forming region is a crystalline silicon film, the electrical characteristics (Id-Vg characteristics) of the N-type transistor and the P-type transistor are both shifted to the negative side (negative side). And the window center (Vcen) becomes 0 V or less.

Therefore, the window center (Vcen) is set to 0
In order to obtain V, the threshold voltage (V
th, n) must be moved in the increasing direction, and the threshold voltage (Vth, p) of the P-type transistor must be moved in the decreasing direction.

That is, an impurity region is formed with respect to a channel forming region so that a narrow channel effect is generated more strongly in an active region of an N-type transistor and a short channel effect is generated more strongly in an active region of a P-type transistor. It is sufficient to arrange them (actually, enhancing the short channel effect means relatively weakening the narrow channel effect).

Here, the structures of the N-type transistor and the P-type transistor when this embodiment is implemented are simplified and shown in FIGS. The channel length is 0.01 to
The channel width may be determined in an arbitrary range in consideration of a desired on-current and reliability.

In FIG. 1A, 101 is a source region, 102 is a drain region, and 103 is a channel formation region. The interval between the impurity regions 104 is adjusted so that a desired threshold voltage is obtained. FIG. 1A shows an active region of an N-type transistor. Therefore, it is important to adjust the interval between the impurity regions 104 to be narrow so that a narrow channel effect appears more strongly.

In using the present invention, the required shift amount of the threshold voltage differs depending on the operator. In other words, in consideration of the original (not according to the present invention) threshold voltage of the semiconductor device manufactured by the practitioner, it is necessary to experimentally design the interval between the impurity regions so as to obtain a desired threshold voltage. is there.

Typically, the interval between impurity regions 104 is set to 30 to 1000 ° (preferably 50 to 100 nm) in order to enhance the narrow channel effect.
~ 500 Å). In other words, the impurity region 1 is divided such that the width of the channel formation region is divided into about 100 to 1000 pieces.
04 may be arranged.

According to the present invention, it is estimated that the threshold voltage (Vth, n) of an N-type transistor having an active region having a structure as shown in FIG. 1A changes as shown in FIG. Is done. In FIG. 1B, a dotted line indicates an example in which the present invention is not implemented, and a solid line indicates an example in which the present invention is implemented.

That is, Vth, n shifts in the increasing direction by adopting a configuration in which the narrow channel effect appears stronger.
Also, it is considered that the effect of pinning the depletion layer is enhanced, so that the subthreshold characteristic is also improved (the slope of the Id-Vg characteristic indicated by the solid line in FIG.

Since FIG. 1C shows an active region of a P-type transistor, it is important to widen the interval between the impurity regions 105 so that a short channel effect appears more strongly. Typically, if the impurity region 105 is arranged so as to divide the width of the channel formation region into about 5 to 100 pieces, the short channel effect will appear strongly. As a result, it is assumed that the threshold voltage (Vth, p) of the P-type transistor changes as shown in FIG.

However, the fact that the short-channel effect appears stronger means that the electrical characteristics deteriorate. Therefore, as shown in FIG.
Since the slope of the g characteristic becomes small, attention must be paid to the balance between the deterioration of the characteristic and the control of Vth, p.

As described above, the threshold voltages of the N-type transistor and the P-type transistor are controlled by intentionally enhancing the short channel effect or enhancing the narrow channel effect by using the pinning technique. Thus, the difference in the absolute value of the threshold voltage in the CMOS circuit can be corrected. That is, it differs from the conventional pinning technique in that the interval between the impurity regions is different depending on the conductivity type.

The concept of utilizing the short channel effect and the narrow channel effect, which were conventionally recognized only as factors that hinder the miniaturization of the element, for controlling the threshold voltage is completely new. According to the present invention, the threshold voltage can be controlled without using the channel doping method.

Therefore, when the present invention is used, the region where carriers move in the channel forming region is an intrinsic or substantially intrinsic region. Intrinsic or substantially intrinsic means that the activation energy is almost 1/2 (the Fermi level is located in the center of the forbidden band), the region where the impurity concentration is lower than the spin density, Undoped region where no impurity is added.

[Embodiment 2] In this embodiment, the structure of a CMOS circuit to which Embodiment 1 is applied will be described with reference to FIG. Since the basic structure of a CMOS circuit is known, only necessary parts will be described with reference numerals.

FIG. 4A shows a CM to which the present invention is applied.
FIG. 3 is a top view of an OS circuit. The left side is an N-type transistor and the right side is a P-type transistor, which has basically the same structure. Reference numerals 401 and 402 denote active regions, above which a gate electrode 403 and a data wiring 404 are arranged.

The active region 401 of the N-type transistor
An impurity region 405 formed by the pinning technique is arranged in the channel formation region of the active region 402 of the P-type transistor.
Similarly, impurity region 406 is arranged in the channel formation region.

At this time, according to the present invention, the impurity region 405 is formed.
Are set narrower than the intervals at which the impurity regions 406 are arranged. Specific numerical values and the like need to be experimentally obtained by the practitioner.

FIGS. 4B and 4C show cross sections of FIG. 4A taken along AA 'and BB'. What is indicated by 407 is a single crystal silicon substrate. At this time, FIG.
FIG. 4B shows a cross section of the active region 401 in the channel width direction, and FIG. 4C shows a cross section of the active region 402 in the channel width direction.

FIG. 4D shows FIG. 4A by CC '.
2 shows a cross section that appears when cutting is performed. 408
Is a field oxide film, and 409 is a gate insulating film. In FIG. 4D, the reason why the hatching is changed when describing the impurity regions 405 and 406 is to show that the arrangement density is different between the N-type transistor and the P-type transistor.

As described above, when the structure of the present invention shown in the first embodiment is applied to a CMOS circuit, as is apparent from FIGS. 4B and 4C, the impurity region 405 arranged in the N-type transistor is used. Is narrower than the distance between the impurity regions 406 arranged in the P-type transistor.

Embodiment 3 In this embodiment, an embodiment of a CMOS circuit to which the present invention is applied will be described with reference to FIG. Since the structure of the CMOS circuit is publicly known, only the schematic structure will be described with reference numerals.

The CMOS circuit shown in FIG. 5A has a structure in which a low-concentration impurity region for relaxing an electric field is provided between a source region or a drain region and a channel formation region by a known technique. Basically, an N-type transistor and a P-type transistor are different only in conductivity type and have no structural difference. Therefore, an N-type transistor will be mainly described.

In FIG. 5A, reference numeral 501 denotes a single crystal silicon substrate, and 502 denotes a field oxide film. The active region includes a source region 503, a drain region 504, and a low concentration impurity region 505. 506 is a gate insulating film; 507 is a gate electrode; 508 is an interlayer insulating film;
9 is a data wiring.

Impurity regions 510 and 511 are arranged in the channel formation region immediately below gate electrode 507 according to the present invention. The impurity region 510 arranged in the N-type transistor is different from the impurity region 5 arranged in the P-type transistor.
The hatching indicates that the arrangement interval of the impurity regions is smaller than that of No. 11.

Next, the structure shown in FIG. 5B is an example where the present invention is applied to an SOI structure. In FIG. 5B shown in this embodiment, a SIMOX substrate is taken as an example of the SOI substrate, but it can be easily applied to an SOS substrate, a bonded substrate, or the like.

The active layer formed of a single crystal silicon thin film includes a source region 513, a drain region 514, a low concentration impurity region 515, and a channel formation region 516. 517 is a gate insulating film, 518 is a gate electrode, 519 is an interlayer insulating film, and 520 is a data wiring.

As shown in FIG. 5B, also in the impurity regions 521 and 522 according to the present invention, as shown in FIG. (The hatching pattern is
(The same as (A) is used.)

Next, the structure shown in FIG.
BiC combining circuit and bipolar transistor
It is a MOS circuit. In FIG. 5C, reference numeral 501 denotes a P-type silicon substrate; 523, a buried N ⁺ region;
Reference numeral 4 denotes a p-well formed by epitaxial growth, and the p-well on the buried N ⁺ region 523 is inverted to an N-type to be an n-well 525 functioning as a collector. Also, 526 is a DeepN ⁺ region serving as take-out electrode from the buried N ⁺ region 523.

[0058] 527 is a field oxide film formed by normal selective oxidation method, the p-well 524 n ⁺ regions 5
28, and ap ⁺ region 529 is formed in the n well region 525. The n-well 525 on the side forming the bipolar transistor has ap ⁻ region 530 serving as an active base.
Are formed first and then the p ⁺ region 53 serving as an external base
1, an n ⁺ region 532 is provided.

Incidentally, impurity regions 533 and 534 are arranged in both the P-type transistor and the N-type transistor. Of course, the arrangement intervals of the impurity regions 533 arranged in the N-type transistor according to the present invention are narrower.

Then, the gate electrode 535 and the interlayer insulating film 5
36, a data line 537 is arranged to form a BiCMOS circuit. Since the BiCMOS circuit has a circuit configuration for effectively using the high-speed operation of the bipolar transistor and the low power consumption of the CMOS circuit effectively, the CMO according to the present invention is used.
Reducing the power consumption of the S circuit is very significant.

The structure of the CMOS circuit described above shows one embodiment, and it is up to the practitioner to apply the present invention to other structures. Therefore, for example, a multi-gate type structure (double-gate type or triple-gate type) can be adopted, and the present invention can be applied to a case where a CMOS circuit is constituted by an inverted staggered FET.

Embodiment 4 A semiconductor device using the present invention can be applied to an active matrix type electro-optical device in which a pixel matrix circuit and a logic circuit are integrated on the same substrate. The electro-optical device includes a liquid crystal display device, an EL display device, an EC display device, and the like.

The logic circuit refers to an integrated circuit for driving the electro-optical device, such as a peripheral drive circuit and a control circuit. The control circuit includes a processor circuit, a memory circuit, a clock generation circuit,
It includes all electric circuits necessary for driving an electro-optical device such as a / D (D / A) converter circuit.

Since the FET to which the present invention is applied controls the threshold voltage without lowering the operation speed, a high-performance integrated circuit can be formed. Further, by setting the window center (Vcen) to 0 V or reducing the window width (Vwin), a necessary driving voltage can be reduced, and an electro-optical device with low power consumption can be manufactured.

[Embodiment 5] In this specification, the term "semiconductor device" refers to any device that functions by utilizing a semiconductor. Therefore, a single FET, a semiconductor integrated circuit (CMO)
Logic circuits such as S circuits, DRAM circuits, and SRAM circuits), active matrix electro-optical devices, and their applied products are included in the category of semiconductor devices.

In this embodiment, the applied product will be described with reference to the drawings. Examples of the semiconductor device using the present invention include a TV camera, a head mounted display, a car navigation, a projection (a front type and a rear type), a video camera, a personal computer, a portable device (a mobile phone, a mobile computer, and the like). . A brief description is given with reference to FIG.

FIG. 6A shows a mobile computer, which comprises a main body 2001, a camera section 2002, and an image receiving section 200.
3, an operation switch 2004, and a display device 2005. The present invention is applied to the display device 2005 and the integrated circuit 2006 incorporated in the device.

FIG. 6B shows a car navigation system.
Main body 2101, display device 2102, operation switch 210
3. It is composed of an antenna 2104. The present invention can be applied to the display device 2102 and the integrated circuit 2105 in the device. Since it is a vehicle-mounted type, a highly reliable semiconductor device that is resistant to voltage fluctuations is required.

FIG. 6C shows a mobile phone, which is a main body 230.
1, audio output unit 2302, audio input unit 2303, display device 2304, operation switch 2305, antenna 2306
It consists of. The present invention can be applied to the display device 2304 and the integrated circuit 2105 in the device. Since it is important to reduce power consumption in the standby state, the present invention can be said to be very effective.

FIG. 6D shows a video camera,
401, display device 2402, audio input unit 2403, operation switch 2404, battery 2405, image receiving unit 240
6. The present invention can be applied to the display device 2402 and the integrated circuit 2407 in the device. Since long-term use by battery driving is required, it is very significant to reduce power consumption according to the present invention.

[0071]

According to the present invention, the short channel effect and the narrow channel effect generated with the miniaturization of device elements are utilized.
Vth of CMOS circuit without using channel doping method
Differences can be corrected.

Therefore, a semiconductor capable of high-speed operation not only preventing a decrease in operation speed and malfunction of a CMOS circuit caused by bias voltage deviation but also reducing the influence of impurity scattering in a channel formation region. The device can be realized. Further, since the absolute value of the threshold voltage of the semiconductor device can be reduced, power consumption of the semiconductor device can be reduced.

Further, due to an energy barrier (impurity region or crystal grain boundary) formed substantially parallel to the channel direction in the channel formation region, there is a problem in that the characteristics are deteriorated due to the short channel effect even in a fine region of 0.01 to 2 μm. A highly reliable semiconductor device that does not have a high reliability can be realized.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration of an active layer.

FIG. 2 is a diagram for explaining a conventional example.

FIG. 3 is a diagram illustrating a pinning technique.

FIG. 4 is a diagram illustrating a configuration of a CMOS circuit.

FIG. 5 illustrates a configuration of a CMOS circuit.

FIG. 6 illustrates an example of a semiconductor device (applied product).

[Explanation of symbols]

 Reference Signs List 101 Source region 102 Drain region 103 Channel formation region 104 Impurity region of N-channel semiconductor device 105 Impurity region of N-channel semiconductor device

Claims (12)

[Claims] 1. A semiconductor device having a CMOS structure in which an N-channel type semiconductor device and a P-channel type semiconductor device are complementarily combined, wherein the threshold voltages of the N-channel type semiconductor device and the P-channel type semiconductor device are The N-channel type semiconductor device is provided with means for strengthening the narrow channel effect, and the P-channel type semiconductor device is provided with means for enhancing the short channel effect so that the absolute values are substantially the same. Semiconductor device. 2. The semiconductor device according to claim 1, wherein an impurity region is artificially and locally disposed in a channel forming region of the N-channel semiconductor device and the P-channel semiconductor device substantially in parallel with a channel direction. The means for enhancing the channel effect is a means for intentionally reducing the arrangement interval of the impurity regions arranged in the N-channel semiconductor device. The means for enhancing the short-channel effect is arranged in the P-channel semiconductor device. A semiconductor device, wherein an arrangement interval of the impurity regions is relatively wider than an arrangement interval of the N-channel type semiconductor device. 3. A semiconductor device having a CMOS structure in which an N-channel semiconductor device and a P-channel semiconductor device are complementarily combined, wherein a channel is formed in a channel forming region of the N-channel semiconductor device and the P-channel semiconductor device. An impurity region formed artificially and locally is arranged substantially parallel to the direction, and the absolute values of the threshold voltages of the N-channel semiconductor device and the P-channel semiconductor device are substantially the same. A semiconductor device, wherein a distance between impurity regions disposed in the N-channel semiconductor device is smaller than a distance between impurity regions disposed in the P-channel semiconductor device. 4. The semiconductor device according to claim 1, wherein at least a region for forming a channel of the N-channel semiconductor device and the P-channel semiconductor device is formed of single crystal silicon. 5. The semiconductor device according to claim 2, wherein one or more elements selected from oxygen, nitrogen, and oxygen are added to the impurity region. 6. The method according to claim 2, wherein
P (phosphorus) or As (arsenic) is added to an impurity region of a channel type semiconductor device, and B (boron) is added to an impurity region of the P channel type semiconductor device. apparatus. 7. When manufacturing a semiconductor device having a CMOS structure in which an N-channel semiconductor device and a P-channel semiconductor device are complementarily combined, a threshold of the N-channel semiconductor device and the P-channel semiconductor device is provided. The N-channel type semiconductor device is provided with a means for enhancing the narrow channel effect, and the P-channel type semiconductor device is provided with means for enhancing the short channel effect so that the absolute values of the voltage values are substantially the same. Of manufacturing a semiconductor device. 8. The narrow channel effect according to claim 7, wherein an impurity region is artificially and locally formed in a channel forming region of the N-channel semiconductor device and the P-channel semiconductor device substantially in parallel with a channel direction. The means for intentionally narrowing the interval between the impurity regions arranged in the N-channel type semiconductor device as a means for strengthening the arrangement of the impurity regions arranged in the P-channel type semiconductor device as the means for enhancing the short channel effect A method for manufacturing a semiconductor device, wherein an interval is made relatively wider than an arrangement interval in the N-channel semiconductor device. 9. When manufacturing a semiconductor device having a CMOS structure in which an N-channel semiconductor device and a P-channel semiconductor device are complementarily combined, a channel formation region of the N-channel semiconductor device and the P-channel semiconductor device is provided. At least a step of artificially and locally forming an impurity region substantially parallel to a channel direction with respect to the N-channel semiconductor device and the P-channel semiconductor device, wherein absolute values of threshold voltages are substantially the same. A method of manufacturing a semiconductor device, wherein the interval between impurity regions arranged in the N-channel semiconductor device is made smaller than the interval between impurity regions arranged in the P-channel semiconductor device. 10. The method according to claim 7, wherein said N
A method for manufacturing a semiconductor device, wherein an active layer of the channel semiconductor device and the P-channel semiconductor device is formed of a polycrystalline silicon film. 11. The method for manufacturing a semiconductor device according to claim 8, wherein one or more elements selected from oxygen, nitrogen, and oxygen are added to the impurity region. 12. The semiconductor device according to claim 8, wherein P (phosphorus) or As (arsenic) is added to the impurity region of the N-channel semiconductor device, and B is added to the impurity region of the P-channel semiconductor device. A method for manufacturing a semiconductor device, comprising adding (boron).