JPH10135282A - Probe card provided with wafer mounting means - Google Patents

Probe card provided with wafer mounting means

Info

Publication number
JPH10135282A
JPH10135282A JP28510796A JP28510796A JPH10135282A JP H10135282 A JPH10135282 A JP H10135282A JP 28510796 A JP28510796 A JP 28510796A JP 28510796 A JP28510796 A JP 28510796A JP H10135282 A JPH10135282 A JP H10135282A
Authority
JP
Japan
Prior art keywords
wafer
integrated circuit
circuit chip
analysis
card
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP28510796A
Other languages
Japanese (ja)
Inventor
Fumito Ota
文人 太田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP28510796A priority Critical patent/JPH10135282A/en
Publication of JPH10135282A publication Critical patent/JPH10135282A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To quickly complete a preparing work which is performed for failure position analysis, in order to perform heat generating analysis, optical pumping current analysis, etc., to an integrated circuit chip in a wafer, by making the other side surface of the integrated circuit chip observable. SOLUTION: A wafer 5 is fixed on a wafer mounting card 4 with a clamper 7, together with a wafer chuck 6. As a matter of course, the fixing is so performed that the wafer 5 and the wafer chuck 6 can be moved by a fine adjustment equipment 9. The wafer mounting card 4 is set on a fixing adjustment equipment, and the fine adjustment equipment 9 is so operated that each pin electrode of a probe aggregate 3 coincides with the position of each electrode pad of an integrated circuit chip as an object of failure position analysis in the wafer 5 by using an optical system. After that, electrical contact of the probe aggregate 3 and electrode pads is ensured by using an elevating mechanism, and the preparing work is completed.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】この発明は、ウェーハ中の集
積回路チップについて行う故障位置解析等に用いるプロ
ーブカードに関するものである。
[0001] 1. Field of the Invention [0002] The present invention relates to a probe card used for failure location analysis performed on an integrated circuit chip in a wafer.

【0002】[0002]

【従来の技術】集積回路チップの故障位置推定には、従
来からエミッション顕微鏡を用いた発光解析や赤外顕微
鏡等を用いた発熱解析、さらにはレーザー顕微鏡を用い
たOBIC(Optical Beam induced Current:光励起電
流)解析等の手法が用いられている。これらの方法で
は、赤外光が集積回路チップのSi基板を透過しやすい
ことを利用し、集積回路チップの表面、裏面のいずれか
らも故障位置解析を行うことができる。しかし、これら
の方法はいずれも集積回路チップに所定の電圧を印加し
ながら電流を検出する必要があり、集積回路チップのパ
ッド電極を通して集積回路チップと解析装置とを電気的
に接続することが必須の条件になる。裏面から故障位置
解析を行う場合は、パッド電極へのプロービングが難し
いため、モールドパッケージを行った後、Si基板を露
出させるために裏面を研磨しこの研磨面に対して故障位
置解析を行うことも行われている。この方法では、ウェ
ーハ状態での故障位置解析はできない。このような問題
を解消するために、例えば特開平7−14898号公報
にはウェーハ状態のままで集積回路チップに対して表面
からの電気的測定を行いながら裏面からの発光、裏面へ
の光照射によって生じる現象などを観察することやそれ
を実現する機構等が記載されている。
2. Description of the Related Art Conventionally, a failure location of an integrated circuit chip is estimated by a light emission analysis using an emission microscope, a heat generation analysis using an infrared microscope, and the like, and an OBIC (Optical Beam induced Current) using a laser microscope. A technique such as current analysis is used. These methods utilize the fact that infrared light easily passes through the Si substrate of the integrated circuit chip, and can perform a failure position analysis from both the front surface and the back surface of the integrated circuit chip. However, in all of these methods, it is necessary to detect a current while applying a predetermined voltage to the integrated circuit chip, and it is essential to electrically connect the integrated circuit chip and the analyzer through pad electrodes of the integrated circuit chip. Condition. When performing a failure position analysis from the back surface, it is difficult to probe the pad electrode.Therefore, after performing a mold package, the back surface is polished to expose the Si substrate, and the failure position analysis may be performed on the polished surface. Is being done. With this method, failure position analysis in a wafer state cannot be performed. To solve such a problem, for example, Japanese Unexamined Patent Publication No. Hei 7-14898 discloses that an integrated circuit chip is electrically measured from the front surface while the wafer is in a wafer state, and light emission from the back surface and light irradiation to the back surface are performed. It describes observation of phenomena and the like caused by the phenomenon and a mechanism for realizing the observation.

【0003】また、特開平5−196638号公報に
は、ウェーハ中の集積回路チップをテストするためのプ
ローブカードであって、集積回路チップの品種ごとに行
うことが必要な交換作業を容易にするために、プローブ
カードをマザーカードと環状ドーターカードとから構成
して、この環状ドーターカードのマザーカードに対する
取付・取外しを容易になしうるように工夫したものが記
載されている。
Japanese Patent Application Laid-Open No. Hei 5-196666 discloses a probe card for testing an integrated circuit chip in a wafer, which facilitates replacement work which must be performed for each type of integrated circuit chip. For this reason, there is described a probe card composed of a mother card and an annular daughter card so that the annular daughter card can be easily attached to and detached from the mother card.

【0004】[0004]

【発明が解決しようとする課題】しかしながら、多品種
のウェーハについて上記のような故障位置解析を行う場
合、各ウェーハ毎に故障位置解析装置に対する準備作業
が必要で故障位置解析装置の稼働率の向上を阻害する要
因になっている。
However, when performing the above-described failure position analysis on a wide variety of wafers, preparation work for the failure position analysis device is required for each wafer, and the operation rate of the failure position analysis device is improved. It is a factor that hinders.

【0005】[0005]

【課題を解決するための手段】この発明に係るウェーハ
搭載手段を備えたプローブカードは基板に固定され集積
回路チップの片面に設けた複数のパッド電極と電気的に
接続するプローブ集合体と、基板に対して所定の位置に
集積回路チップを含むウェーハを所定の姿勢に把持する
ウェーハ搭載手段を有するとともに集積回路チップの他
の片面を観察可能に構成したものである。また、プロー
ブ集合体を基板から分離可能に構成したものである。
A probe card provided with a wafer mounting means according to the present invention comprises: a probe assembly fixed to a substrate and electrically connected to a plurality of pad electrodes provided on one surface of an integrated circuit chip; A wafer mounting means for holding a wafer including the integrated circuit chip in a predetermined position at a predetermined position, and observing the other side of the integrated circuit chip. Further, the probe assembly is configured to be separable from the substrate.

【0006】[0006]

【発明の実施の形態】BEST MODE FOR CARRYING OUT THE INVENTION

実施形態1.以下、この発明によるウェーハ搭載手段を
備えたプローブカード(以下、単に解析カードと呼ぶ)
の実施形態を図を用いて説明する。図1はこの解析カー
ドを正面図と断面図で示した構成図、図2はこの発明に
よる解析カードに解析対象ウェーハを取付けるための取
付調整装置にセットしたときの光学顕微鏡などの光学系
と解析カードの関係を示す配置図である。図において、
1は解析カード、2はマザーカード、3はマザーカード
2上に取付けた複数の針状電極を有するプローブ集合
体、4はウェーハ5をウェーハチャック6に挟み込んで
固定するウェーハ搭載カードであり、中央部にはプロー
ブ集合体3をウェーハ5中の解析対象である集積回路チ
ップの電極パッドに接触させるための開口部4’が設け
てある。7はウェーハ5を取付けたウェーハチャック6
をウェーハ搭載カード4に取付けるクランパであり中央
部には観察用の開口部7’が設けてある。8はウェーハ
搭載カード4をマザーカード2に対して昇降させる昇降
機構、9はウェーハ5の位置あわせ用微動装置で、押圧
ロッド91 とばね92 とを備えウェーハ5およびウェー
ハチャック6をウェーハ搭載カード4に対してその軸方
向に移動させるように付勢する微動装置9aと、微動装
置9aの軸線上に配置したねじロッド93 を備えこれを
回してウェーハ5およびウェーハチャック6をその軸方
向に移動させるようにした微動装置9bの一対からな
り、ウェーハ搭載カード4上のそれぞれ直交する2軸方
向に2組ずつ設けてある。各軸方向の2つの微動装置9
bのねじロッド93 を同一方向に回せばウェーハ5およ
びウェーハチャック6を当該軸方向に微動させることが
でき、一方のみを回しあるいは2つを互いに逆方向に回
せばウェーハ5およびウェーハチャック6を回転方向に
微動させることができる。図示しないが、マザーカード
2には上記以外に故障位置解析装置と信号等を授受する
ための電気コネクタ等が設けてある。10は光学系、2
0は取付調整装置に備えた解析カード固定台であり、解
析カード1をねじ等の締結手段を用いて取付ける。
Embodiment 1 FIG. Hereinafter, a probe card provided with a wafer mounting means according to the present invention (hereinafter simply referred to as an analysis card)
The embodiment will be described with reference to the drawings. FIG. 1 is a structural view showing the analysis card in a front view and a cross-sectional view. FIG. 2 shows an optical system such as an optical microscope when the analysis card is set on a mounting adjustment device for mounting a wafer to be analyzed on the analysis card according to the present invention. FIG. 4 is a layout diagram showing a relationship between cards. In the figure,
1 is an analysis card, 2 is a mother card, 3 is a probe assembly having a plurality of needle-shaped electrodes mounted on the mother card 2, 4 is a wafer mounting card for holding the wafer 5 by sandwiching it in the wafer chuck 6, and The portion is provided with an opening 4 ′ for bringing the probe assembly 3 into contact with the electrode pad of the integrated circuit chip to be analyzed in the wafer 5. 7 is a wafer chuck 6 on which the wafer 5 is mounted.
Is attached to the wafer mounting card 4 and has an opening 7 'for observation in the center. 8 elevating mechanism for raising and lowering the wafer mounted card 4 against the mother card 2, 9 in the fine motion device for alignment of the wafer 5, the wafer 5 and the wafer chuck 6 and a push rod 9 1 and the spring 9 second wafer mounted cards and fine movement device 9a for biasing to move in the axial direction with respect to 4, fine movement device 9a axially wafer 5 and the wafer chuck 6 with a screw rod 9 3 pass this placed on the axis of the , And two sets of fine movement devices 9b are provided in the two axial directions orthogonal to each other on the wafer mounting card 4. Two fine movement devices 9 in each axial direction
turning the b threaded rod 9 3 in the same direction the wafer 5 and the wafer chuck 6 can be finely moved in the axial direction, the wafer 5 and the wafer chuck 6 turning the the turning or two only one in opposite directions It can be finely moved in the rotation direction. Although not shown, the mother card 2 is provided with an electrical connector and the like for transmitting and receiving signals and the like to and from the failure position analysis device in addition to the above. 10 is an optical system, 2
Reference numeral 0 denotes an analysis card fixing base provided in the mounting adjustment device, and the analysis card 1 is mounted using fastening means such as screws.

【0007】次に解析対象ウェーハを解析カード1にセ
ットして解析作業を行う手順について説明する。解析対
象のウェーハ5をウェーハチャック6とともにクランパ
7によってウェーハ搭載カード4に取付ける。ウェーハ
5およびウェーハチャック6が微動装置9の操作によっ
て移動可能な程度に固定する必要があることはいうまで
もない。これを取付調整装置にセットして光学系10に
よりプローブ集合体3の各針状電極とウェーハ5中の故
障位置解析の対象である集積回路チップの各電極パッド
の位置とが合致するように微動装置9を操作する。しか
る後に昇降機構によってプローブ集合体3と電極パッド
の電気的接触を確保して完了する。以上のように解析対
象ウェーハを解析カード1にセットして故障位置解析装
置に載置し所望の故障解析を行う。解析対象ウェーハを
解析カード3にセットするのに取付調整装置を用いて行
うものとして説明したが、解析装置上でセット可能なこ
とはいうまでもない。
Next, a procedure for setting an analysis target wafer on the analysis card 1 and performing an analysis operation will be described. The wafer 5 to be analyzed is mounted on the wafer mounting card 4 by the clamper 7 together with the wafer chuck 6. Needless to say, it is necessary to fix the wafer 5 and the wafer chuck 6 to such an extent that they can be moved by the operation of the fine movement device 9. This is set in the mounting adjustment device, and the optical system 10 moves the needle-shaped electrodes of the probe assembly 3 and finely adjusts them so that the positions of the electrode pads of the integrated circuit chip to be analyzed for the failure position in the wafer 5 are matched. The device 9 is operated. Thereafter, electrical contact between the probe assembly 3 and the electrode pads is secured by the lifting mechanism, and the process is completed. As described above, a wafer to be analyzed is set on the analysis card 1 and mounted on the failure position analysis device to perform a desired failure analysis. Although it has been described that the analysis target wafer is set on the analysis card 3 using the mounting adjustment device, it goes without saying that the wafer can be set on the analysis device.

【0008】以上の説明では、プローブ集合体3をマザ
ーカード2に取付けるものとしたが、図3に示すよう
に、プローブ集合体3を取付けたプローブアダプター
3’を設けて、これをマザーカード2に取付けるように
してもよい。このようにすれば、集積回路チップの品種
に応じてプローブアダプター3’を交換することによっ
て集積回路チップの各品種に対応することができる。
In the above description, the probe assembly 3 is attached to the mother card 2. However, as shown in FIG. 3, a probe adapter 3 'to which the probe assembly 3 is attached is provided, and this is attached to the mother card 2. You may make it attach to. In this way, it is possible to deal with each type of integrated circuit chip by exchanging the probe adapter 3 'according to the type of integrated circuit chip.

【0009】さらに、ウェーハ搭載カード4へのウェー
ハチャック6の固定にクランパ7を用いるものとした
が、磁気的な吸着力を利用してクランパ7を省略しても
よい。例えば、ウェーハ搭載カード4とウェーハチャッ
ク6の何れか一方の接触面に永久磁石を設け他方を磁性
材で構成すればよい。もちろん、永久磁石の替わりに電
磁石を用いることも可能である。このような構成例を図
4に示す。
Further, although the clamper 7 is used for fixing the wafer chuck 6 to the wafer mounting card 4, the clamper 7 may be omitted by utilizing a magnetic attraction force. For example, a permanent magnet may be provided on one of the contact surfaces of the wafer mounting card 4 and the wafer chuck 6, and the other may be made of a magnetic material. Of course, it is also possible to use electromagnets instead of permanent magnets. FIG. 4 shows an example of such a configuration.

【0010】[0010]

【発明の効果】この発明に係るウェーハ搭載手段を備え
たプローブカードは、基板に固定され集積回路チップの
片面に設けた複数のパッド電極と電気的に接続するプロ
ーブ集合体と、基板に対して所定の位置に集積回路チッ
プを含むウェーハを所定の姿勢に把持するウェーハ搭載
手段を有するとともに集積回路チップの他の片面を観察
可能に構成したので、ウェーハ中の集積回路チップに対
して発熱解析やOBIC解析等を行うために故障位置解
析装置に対して行う準備作業をすばやく完了させること
ができる。もちろん、LOCパッケージ対応の集積回路
チップのように、中央部に電極パッドを配置しているた
め、プローブによっておもて面側からの観測視野を遮ら
れたり、おもて面側に光を遮る物質が多く存在する集積
回路チップについても裏面側からの故障位置解析を容易
に行える。
According to the present invention, there is provided a probe card provided with a wafer mounting means, comprising: a probe assembly fixed to a substrate and electrically connected to a plurality of pad electrodes provided on one surface of an integrated circuit chip; Having a wafer mounting means for holding the wafer including the integrated circuit chip at a predetermined position in a predetermined position and observing the other side of the integrated circuit chip so that the integrated circuit chip in the wafer can be analyzed for heat generation or the like. It is possible to quickly complete the preparation work performed on the failure position analysis device for performing the OBIC analysis and the like. Of course, like the integrated circuit chip compatible with LOC package, the electrode pad is located in the center, so that the probe blocks the observation field of view from the front side or blocks the light to the front side. Failure position analysis from the back side of an integrated circuit chip containing a large amount of material can be easily performed.

【0011】さらに、プローブ集合体を基板から分離可
能に構成したので、当該部分を交換することによって集
積回路チップの各品種に対応することができる。
Further, since the probe assembly is configured to be separable from the substrate, it is possible to cope with various types of integrated circuit chips by exchanging the portion.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 この発明によるウェーハ搭載手段を備えたプ
ローブカードの実施形態を示す構成図である。
FIG. 1 is a configuration diagram showing an embodiment of a probe card provided with a wafer mounting means according to the present invention.

【図2】 図1に示すウェーハ搭載手段を備えたプロー
ブカードの使用方法を説明するための配置図である。
FIG. 2 is a layout diagram for explaining a method of using the probe card provided with the wafer mounting means shown in FIG.

【図3】 図2に示すウェーハ搭載手段を備えたプロー
ブカードの変形例を示す構成図である。
FIG. 3 is a configuration diagram showing a modified example of the probe card provided with the wafer mounting means shown in FIG. 2;

【図4】 図2に示すウェーハ搭載手段を備えたプロー
ブカードの他の変形例を示す構成図である。
FIG. 4 is a configuration diagram illustrating another modified example of the probe card including the wafer mounting unit illustrated in FIG. 2;

【符号の説明】[Explanation of symbols]

1 ウェーハ搭載手段を備えたプローブカード 2
マザーカード 3 プローブ集合体 4 ウェーハ搭載カード 5
ウェーハ 6 ウェーハチャック 7 クランパ 8
昇降機構 9 微動装置 10 光学系 20
カード固定台
1 Probe card with wafer mounting means 2
Mother card 3 Probe assembly 4 Wafer mounted card 5
Wafer 6 wafer chuck 7 clamper 8
Elevating mechanism 9 Fine movement device 10 Optical system 20
Card holder

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 基板に固定され集積回路チップの片面に
設けた複数のパッド電極と電気的に接続するプローブ集
合体と、前記基板に対して所定の位置に前記集積回路チ
ップを含むウェーハを所定の姿勢に把持するウェーハ搭
載手段を有するとともに前記集積回路チップの他の片面
を観察可能に構成したことを特徴とするウェーハ搭載手
段を備えたプローブカード。
A probe assembly fixed to a substrate and electrically connected to a plurality of pad electrodes provided on one surface of the integrated circuit chip; and a wafer including the integrated circuit chip at a predetermined position with respect to the substrate. A probe card having a wafer mounting means, comprising: a wafer mounting means for gripping the integrated circuit chip in a different posture, wherein the other side of the integrated circuit chip can be observed.
【請求項2】 前記プローブ集合体を前記基板から分離
可能に構成したことを特徴とする請求項1に記載のウェ
ーハ搭載手段を備えたプローブカード。
2. The probe card according to claim 1, wherein the probe assembly is configured to be separable from the substrate.
JP28510796A 1996-10-28 1996-10-28 Probe card provided with wafer mounting means Pending JPH10135282A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP28510796A JPH10135282A (en) 1996-10-28 1996-10-28 Probe card provided with wafer mounting means

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28510796A JPH10135282A (en) 1996-10-28 1996-10-28 Probe card provided with wafer mounting means

Publications (1)

Publication Number Publication Date
JPH10135282A true JPH10135282A (en) 1998-05-22

Family

ID=17687217

Family Applications (1)

Application Number Title Priority Date Filing Date
JP28510796A Pending JPH10135282A (en) 1996-10-28 1996-10-28 Probe card provided with wafer mounting means

Country Status (1)

Country Link
JP (1) JPH10135282A (en)

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