JPH10135281A - Ic package - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform an electric test of a CSP(chip size package) IC package while protecting the mounting electric contact against damage. SOLUTION: An IC package having solder bumps 23 rearranged on the element forming surface of an IC chip 1 using a bump rearranging board 21 is turned, on the side face thereof, by means of an insulating frame body 11 through which conductive measuring pins 12 are penetrating. First electrode pads 2 arranged along the fringe part of the element forming surface while being connected electrically with solder bumps 23 through second bonding wires 4 are also connected with the measuring pins 12 through first bonding wires 3 and third electrode pads. Electric measurement is made by touching a measuring probe to the exposed end face of a measuring pin 13 from the rear side 11 of the IC package. Since the solder bumps 23 do not touch the measuring means at all, they are protected against abrasion, damage an falling.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CSP (chip size package) type IC package capable of supporting high-density mounting and increasing the number of pins while maintaining the same package size as an IC chip body. The present invention relates to a novel structure that enables electrical inspection while preventing damage to contacts.

[0002]

2. Description of the Related Art In the field of manufacturing electronic devices, there is an increasing demand for smaller, lighter, lower cost, and shorter delivery times, and similar demands are imminent for IC packages that form the heart of such devices. It has become. The current mainstream of IC packages is called QFP (Quad Flat Package), in which a number of external leads are drawn out on four sides of a rectangular package. However, the lead pitch is 0.4m
As the transition from m to 0.3 mm has occurred, the connection quality has become a problem, and it is not always easy to cope with further miniaturization and increase in the number of pins.

Research and development of CSP (Chip Scale Package) as an IC package that can solve this problem
Development is active. CSP does not yet have a unified standard, and various companies have been proposed. However, the common idea is that (a) the element formation surface of an IC chip is mounted on a mounting board ( (B) all electrode pads are formed on the element forming surface of the IC chip, and the arrangement pattern of the electrode pads is some kind of intermediate layer ( Through an interposer), which is converted into a regular arrangement pattern of electrical contacts, and this electrical contact is a mounting contact that is actually connected to a wiring pattern on the substrate. As the mediation layer, a ceramics substrate or a polyimide film is used. Further, the electric contact is constituted by electrodes patterned in a grid pattern and bumps arranged in a grid pattern. In particular, the latter method of arranging bumps is a BGA (ball
Grid array).

[0004]

As described above, as the number of pins of the IC package is increased and the pin spacing is also reduced, the electrical inspection probe is accurately connected to the fine inspection terminal at the time of electrical inspection. Moreover, it is becoming more difficult to make contact with both without damaging them.

[0005] For a conventional package using a lead frame, several structural ideas have been proposed to solve this problem. For example, JP-A-5-25
No. 9367 discloses a structure in which an electrical inspection pin connected to each lead is exposed on an upper surface of a flat type IC package, and a probe is brought into contact with the pin to perform an inspection. Also, Japanese Patent Application Laid-Open No. 6-2043
No. 58 discloses an inspection contact end provided on a lead frame inside a mold, and an opening for exposing the inspection contact end is provided on the upper surface of the mold. A structure of an IC package capable of performing the following is disclosed. The techniques described in each of the above publications have been proposed for the purpose of preventing deformation of the lead frame and poor contact with the probe. Here, the member to be contacted by the probe is a lead or a pin connected thereto, and these members are entirely fixed to the mold resin except for the exposed portions.

On the other hand, in order to conduct an electrical test on a CSP type IC package, it is necessary to arrange probes on electric contacts arranged on the element forming surface side of an IC chip that is not molded over the entire surface. In particular, when the electrical contact is a bump, such as a BGA-type IC package, the bump itself is increasingly miniaturized in recent years, and it is difficult to secure the adhesive strength to the base. Defects such as abrasion, deformation, and dropping are likely to occur. The IC package in which these defects occur causes a substrate mounting failure at the mounting stage, and is disadvantageous in manufacturing. Accordingly, an object of the present invention is to provide a CSP type IC package capable of performing a highly reliable electrical inspection without causing a defect in an electrical contact used for connection with a mounting substrate. I do.

[0007]

SUMMARY OF THE INVENTION An IC package according to the present invention is designed so that an electrical test probe can be contacted from a direction opposite to an element forming surface of an IC chip in which electrical contacts are rearranged. A first electrode pad electrically connected to the electrical contact is disposed on the element forming surface along a side of the IC chip, and the first electrode pad is formed so as to penetrate a frame surrounding the IC chip in a height direction. The above-mentioned object is achieved by drawing a conductor to be connected to the frame to the back surface of the frame (however, this is an upper surface during mounting) and making the exposed portion of the conductor on the back surface a contact point of the electrical inspection probe. Is what you do. What plays the role of the conductor is a conductive measurement pin embedded in the frame, and the measurement pin may be individually connected to the corresponding first electrode pad using the first connection means. .

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention is directed to an IC package in which an arrangement pattern of electrode pads on an element forming surface of an IC chip is converted to an arrangement pattern of another electric contact by using an intermediate layer. And Here, the mediation layer can be formed using a known insulating material such as a ceramics substrate, an epoxy resin substrate, or a polyimide film. The electrical connection between the first electrode pad and the electrical contact can be made through an internal structure of the mediating layer, but the electrical connection between the electrical contact and the side of the mediating layer can be made. It is convenient to arrange two electrode pads and to electrically connect the second electrode pads to the first electrode pads using the second connection means. It is convenient to use a bonding wire as the first connection means and the second connection means. Note that the first connection means and the second connection means
The connecting means includes not only a bonding wire but also a base metal film used in consideration of adhesion and contact resistance with the wire.

The present invention is suitable for application to all kinds of CSPs. In particular, if the present invention is applied to a BGA type IC package in which electric contacts are formed of bumps made of solder or other metal, the present invention can be applied to an electric test. It is possible to effectively prevent the abrasion, damage and dropping of the bump.

Next, as a specific embodiment of the present invention, a configuration example of a BGA type IC package will be described with reference to FIG.
This will be described with reference to FIG. FIG. 1 is a diagram in which a part of a square BGA type IC package is cut away and the element forming surface side I is directed upward, and FIG.
It is a line sectional view. In this IC package, the IC chip 1 is wound around four sides by a frame 11. Although a large number of electrode pads (not shown) are formed on the element forming surface of the IC chip 1, the arrangement pattern of the electrode pads is such that sufficient mounting accuracy can be obtained and the arrangement of the solder bumps 23 is regular. The intermediate layer that is converted into the pattern is the bump rearranged substrate 21. The bump rearrangement substrate 21
For example, it is formed using a glass fiber reinforced epoxy resin.

A first electrode pad 2 is arranged in a region along four sides of the IC chip 1, and a second electrode pad 2 is also formed in a region along four sides of the bump rearrangement substrate 21.
2 are arranged. The second electrode pad 22 is connected to the internal wiring 2.
4 are electrically connected to the individual solder bumps 23. The first electrode pad 2 and the second electrode pad 22
Are formed using, for example, an Al-based material film, and are provided in the same number. These electrode pads are arranged such that the pads corresponding to each other are each provided with a second bonding wire 4.
Are connected on the element forming surface side I. This second bonding wire 4 is formed using Au or an Al-based material.

The first electrode pad 2 and the second electrode pad 2
Numeral 2 denotes terminals for electric measurement formed on the element forming surface side I, and a member enabling access of the electric inspection probe from the back side II to these terminals is a frame 11 and a frame. The measuring pin 12 embedded therein. The frame 11 is a member made of epoxy resin having a width of 0.1 mm and a height of 0.4 mm. The height is slightly higher than the height of the IC chip 1, but this is
When performing resin sealing only on the peripheral portion of the C chip 1,
This is for increasing the holding power of the sealing layer 5.

A measuring pin 12 made of an Al-based or Cu-based material having a side of 0.05 mm extends through the frame 11 in the height direction. This measuring pin 12
On the back side II, the exposed surface can be used as it is as a contact point of the probe for electric measurement, but on the element forming surface I, since wire bonding is performed as described later, the end of the bonding wire is in close contact with the metal ball. Properties and contact resistance are problems. Here, the measuring pin 1 on the element forming surface side I
The third electrode pad 13 made of Au was formed on the end face of No. 2.

In order to form the measuring pin 12 and the third electrode pad 13 penetrating in the height direction of the frame body 11 as described above, for example, an Au layer serving as the third electrode pad 13 is previously formed at one end. A method of filling the gaps between the pins by setting the adhered Al pins or Cu pins in a molding die and injecting a resin into the molding die can be adopted.

The third electrode pad 13 and the second electrode pad 13 are connected to each other by use of a first bonding wire 3. The first bonding wires 3 and the second bonding wires 4 are sealed with a sealing layer 5 made of, for example, an insulating resin. Since this IC package is face-down bonded onto a mounting substrate, it is particularly important that the height of the sealing layer 5 be within the range of the height of the solder bumps 23. Thus, in the present IC package, the measuring pin 12 → the third electrode pad 13 → the first bonding wire 3 → the first electrode pad 2 → the second bonding wire 4 → the second electrode pad 22 → the internal wiring 24 → conduction is made along the path of the solder bumps 23.

In order to perform the electrical measurement on the IC package, as shown in FIG.
Then, the electrical inspection probe 31 is brought into contact with the measurement pin 12. The electrical inspection probe 31 is, for example, of the type provided in a commercially available probe card. As described above, in the present invention, various test signals can be input from the probe 31 while the probe 31 is in contact with the measurement pin 12. That is, solder bump 2
Since there is no risk of the probe 3 coming into contact with the probe 31, no defect such as abrasion, damage, and dropping of the bump is generated. In FIG. 3, the electrical inspection probe 31 is brought into contact with the IC package in a state where the IC package is mounted face-down, but this may be performed by mounting the IC package in a face-up manner.

Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and the details of the configuration of the IC chip, the dimensions of each member, and the constituent materials of each member are not limited thereto. It can be changed or selected as appropriate.

[0018]

As is clear from the above description, the IC package of the present invention enables highly reliable electrical inspection without causing defects in electrical contacts used for connection with a mounting substrate. It is. Therefore, the reliability and manufacturing yield of all types of CSP type IC packages including the BGA type can be improved. A chip that has been proved to be a good chip before mounting, ie, KG
D (known good die) can be easily obtained, and the role of CSP in practical use is extremely large.

[Brief description of the drawings]

FIG. 1 is a partially enlarged perspective view showing a part of a BGA type IC package to which the present invention is applied.

FIG. 2 is a sectional view taken along line AA of FIG.

FIG. 3 is a schematic perspective view showing a state in which an electrical inspection probe is brought into contact with the IC package of FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 IC package 2 1st electrode pad 3 2nd bonding wire 4 1st bonding wire 5 Sealing layer 6 Wiring pattern 11 Frame 12 Measurement pin 13 3rd electrode pad 21 Bump rearrangement board 22 2nd electrode pad 23 Solder bump 24 Connection hole 31 Electrical inspection probe

Claims (5)

[Claims] 1. An electrical contact for mounting electrically connected to a first electrode pad on an element forming surface using an insulating mediating layer laminated on an element forming surface of an IC chip. An IC package comprising: the first electrode pads are arranged on an exposed surface of the element forming surface outside the lamination region of the mediation layer; and the side surfaces of the IC chip have the same number of conductive members as the first electrode pads. The first electrode pad and the corresponding measurement pin are respectively wrapped around an insulating frame formed by penetrating the measurement pin in the height direction using the first connection means on the element forming surface side. An IC package which is electrically connected so that an electrical inspection probe is brought into contact with the measurement pin exposed on the frame from a direction opposite to the element formation surface. 2. An electrical connection between the first electrode pad and the electrical contact, comprising: a second electrode pad disposed on a side of the mediation layer and electrically connected to the electrical contact; 2. The IC package according to claim 1, wherein said IC package is achieved by using a second connection means for electrically connecting each of said pads and said second electrode pad. 3. The IC package according to claim 1, wherein said first connection means and said second connection means both include bonding wires. 4. The IC package according to claim 3, wherein only the vicinity of the connection portion by the bonding wire is selectively sealed with an insulating sealing material. 5. The IC package according to claim 1, wherein said electric contact is a bump.