JPH10133798A - Circuit for inputting key - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the number of terminals at the time when a circuit for inputting key is made to be IC by allowing a common signal to have plural voltage levels which are successively increased, and supplying the common signals as a key scan signal to the two columns of a key matrix. SOLUTION: The lines of two columns of a key matrix 2 are connected with one common output terminal 70 and 71. Then, forward diodes 20 and 21 and backward diodes 22 and 23 are inserted into connected lines from the output terminal 70 or 71 to the key matrix 2. An invertor 130 having a first threshold voltage Vt H and an invertor 131 having a second threshold voltage Vt L are connected in parallel with an input terminals 120 in an IC4. In this case, common signals COM1 and COM2 are allowed to have any of three different voltage levels, and the first threshold voltage Vt H is set to a voltage level between VDD/2 and VDD and the second threshold voltage Vt L is set to a voltage level between 0V and VDD/2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a key input circuit for scanning a key matrix by using a driver output for driving a liquid crystal.

[0002]

2. Description of the Related Art Hitherto, an IC having both a function of processing a key input signal from a key matrix and a function of driving a liquid crystal display device has been developed. Generally, such an IC is provided with an output terminal for transmitting a key scan signal to a key matrix and an input terminal for inputting a key input signal from the key matrix for key input processing. In addition, an output terminal for sending a common signal and a segment signal to the liquid crystal display device for driving the liquid crystal is provided separately from the input / output terminal described above.

In such a configuration, the number of terminals of the IC becomes very large, so that as shown in FIG.
Has been proposed to supply a segment signal to the key matrix 2 as a key scan signal. However, since the segment signal is a signal having a predetermined level only in the segment to be lit originally, it cannot be used as it is as a key scan signal.

Therefore, conventionally, a partial period of each segment signal is allocated for key scanning, and a pulse signal having a narrow width such that each segment signal sequentially becomes a predetermined level is inserted during this period.

[0005]

In the conventional configuration using the segment signal as the key scan signal, the pulse width of the pulse signal for performing the key scan becomes narrow, so that the key scan is easily affected by noise and the like. There was a problem that can not be. Further, since the segment signal is at a predetermined level when it is not necessary for the display device, it is not preferable in terms of display contrast, viewing angle and temperature characteristics.

[0006]

SUMMARY OF THE INVENTION The present invention provides a key matrix, an input terminal for inputting a key input signal from the key matrix, a key decoder for generating key data based on the key input signal, and a liquid crystal display. In a key input circuit including a common driver and a segment driver for respectively outputting a common signal and a segment signal for driving the device, the common signal sequentially increases from the first to the n-th (n: an integer of 3 or more) The same common signal is supplied as a key scan signal to two columns of the key matrix, and two supply lines for supplying the common signal are provided with diodes whose directions are opposite to each other. The input threshold voltage is applied to the input terminal, the input terminal, and the first and second input terminals, respectively.
And a second input circuit having an input threshold voltage between the (n-1) th and nth voltage levels is connected in parallel. I do.

Alternatively, the input terminal has an input threshold voltage at a voltage level between the first and second levels during a first period, and an input threshold voltage at the (n−1) th and second levels during a second period. An input circuit that switches to a voltage level between n is connected.

[0008]

FIG. 3 is a block diagram showing a schematic block configuration of an embodiment of the present invention. Reference numeral 4 denotes an IC having both a key input processing function and a liquid crystal driving function. The IC 4 includes a common driver 6 for generating common signals COM1 and COM2 based on a timing signal from the timing generation circuit 5, and a common signal for the liquid crystal display device 1.
Output terminals 70 and 71, a shift register 8 that takes in display data serially transferred from the outside and converts it into parallel data, a latch circuit 9 that latches the contents of the shift register 8, and an output of the latch circuit 9. A segment driver 10 for generating a segment signal in response thereto;
Output terminals 110, 111,... For transmitting the segment signals SEG1, SEG2,.

Further, input terminals 120, 121,... For inputting key input signals from the key matrix 2, an input circuit 13 connected to these input terminals for determining an input signal level, and a timing generation circuit 5 A key decoder 14 for generating key data based on the strobe signal STB and an output signal of the input circuit 13 and a key buffer 15 for storing the generated key data are provided as components for key input processing.

Next, FIG. 1 shows an input circuit shown in FIG. 3 and a main part circuit showing in detail a connection relationship between a common output terminal and a key matrix. In the first embodiment shown in FIG.
Two columns of the key matrix 2 are connected to one common output terminal 70 and 71, respectively, and two rows of lines of the key matrix 2 are connected to the input terminals 120 and 121, respectively. Key switches S1 to S8 are connected to intersections of each row and each column of the key matrix 2, and switches S3, S4, S
In the column to which S7 and S8 are connected, diodes 20 and 21 in the forward direction are inserted in the connection line from the output terminal 70 or 71 to the key matrix 2. On the other hand, in the column to which the switches S1, S2, S5, and S6 are connected, diodes 22 and 23 in opposite directions are inserted in the connection line from the output terminal 70 or 71 to the key matrix 2.

The input terminal 12 inside the IC 4
Inverter 130 having a first threshold voltage VtH and inverter 131 having a second threshold voltage VtL are connected in parallel to 0, and a normal inverter 132 is connected to the output side of inverter 130.
Further, the input terminal 120 is connected via a resistor 133 to VDD / 2 in the 1/2 bias system and to V DD in the 1/3 bias system.
DD / 3 or 2VDD / 3. The configuration of the input circuit connected to the input terminal 121 is the same as the configuration connected to the input terminal 120, and the inverter 134 has the first threshold voltage VtH and the inverter 135
Has a second threshold voltage VtL.

Here, the common signals COM1, COM2
Takes one of three different voltage levels of 0V, VDD / 2 and VDD (0V <VDD / 2 <VDD), as shown in FIGS. The threshold voltage VtH is set to a voltage level between VDD / 2 and VDD, and the second threshold voltage VtL is set to 0.
It is set to a voltage level between V and VDD / 2.

Accordingly, the switches S3 and S4 are for the VDD period of the common signal COM1, the switches S1 and S2 are for the 0V period of the common signal COM1, the switches S7 and S8 are for the VDD period of the common signal COM2, and the switches S5 and S6 are for the common signal COM1. The 0V period of the signal COM1 is used as a key scan signal, and the inverters 130, 131, 134, and 135 determine whether the switches S4 and S8, the switches S2 and S6, the switches S3 and S7, and the switches S1 and S5 are on. Or to detect.

For example, when only the switch S1 is on,
During the period when the common signal COM1 is VDD, this VDD signal is input to the key matrix 2 via the diode 21. However, since the switches 3 and 4 are both off, the output I
1, I3 remain at the L level (FIGS. 4g, i). When the common signal COM1 becomes 0V, this 0V is applied to the diode 2
3 and as a key input signal to the input terminal 121 via the switch S1, and becomes lower than the threshold voltage VtL of the inverter 135, so that the output I4 of the inverter 135 becomes L level (FIG. 4j). Next, the common signal C
During the period when OM2 is VDD, this VDD signal is input to the key matrix 2 via the diode 20, but since both the switches 7 and 8 are off, the outputs I1 and I3 remain at the L level (FIG. 4g, i). Common signal COM2
Becomes 0 V, this 0 V is input to the key matrix 2 via the diode 22, but since the switches 5 and 6 are both off, the outputs I2 and I4 remain at the L level (FIG. 4h, j).

Similarly, when only the switch S8 is ON, when the common signal COM2 becomes VDD, this VDD is input to the input terminal 120 as a key input signal via the diode 20 and the switch S8, and the threshold voltage of the inverter 133 is changed. VtH, inverter 1
The output I1 of the output 33 takes the H level (FIG. 4g). As described above, in the first embodiment, the two common signals COM1, C
With OM2, the key scan can be executed in four rows, which is twice the normal number, and the number of terminals can be reduced to half.

Next, a second embodiment shown in FIG. 2 will be described. In this embodiment, only the configuration of the input circuit 13 is different, and other connection relationships are exactly the same as those in FIG. Here, the positive input terminal of the comparator 137 is connected to the input terminal 120, the negative input terminal of the comparator 137 is connected to VDD via the resistor 138, and grounded via the resistor 139. Further, a resistor 140 and an N-channel MOS transistor 141 as a switch are connected in series, and these are connected in parallel to a resistor 139. By appropriately selecting the resistance values of the resistors 138, 139, and 140, the input threshold voltage of the comparator 137 becomes the above-mentioned VtH when the transistor 141 is off, and the input threshold voltage when the transistor 141 is on. Are switched to VtL described above.
Also, as the switching signal TMG of the transistor 141, as shown in FIG. 5k, the common signals COM1 and COM2 are set to 0.
A signal which becomes L level only during the period when the signal becomes V is used. The input circuit connected to the input terminal 121 has the same configuration as the input circuit connected to the input terminal 120 described above.

Accordingly, the second embodiment performs the same operation as the first embodiment, and as shown in FIG.
When S1 and S8 are turned on, the same operation as in FIG. 4 is performed.
Regarding the threshold voltage, for example, a resistor 138,
139 and 140 are represented by R1, R2 and R3, respectively.
1 = 25K ohm, R2 = 75K ohm, R3 = 9.3
By setting to 7K ohm, the desired VtH =
0.75 VDD and VtL = 0.25 VDD are obtained.

The common signals COM1 and COM2 are 1
In the case of the / 3 bias system, 0V, VDD / 3, 2VDD /
3, VDD (0V <VDD / 3 <2VDD / 3 <VDD), so that the first threshold voltage VtH is set to a voltage level between 2VDD / 3 and VDD. , The second threshold voltage VtL may be set to a voltage level between 0 V and VDD / 3.

As described above, the input circuit 1 shown in FIG.
In 3, the key input signal corresponding to the pressed key is obtained. By the way, since the common signal has a voltage of 3 or 4 levels as described above, if it is supplied to the key decoder 14 as it is, the decoding process becomes troublesome. Therefore, as shown in FIGS.
4 and 5 in which H level is set only during the period when M2 is at VDD.
Strobe signals STB1H and STB2H shown in c and e
And the strobe signals STB1L and STB2L shown in FIGS. 4 and 5d and 5f, which become H level only during the period when the common signals COM1 and COM2 become 0V, are generated by the timing generation circuit 5, and these signals are inputted to the key decoder 14. ing. As a result, key decoding can be performed in the same manner as in the related art.

[0020]

According to the present invention, a display common signal can be used as a key scan signal only by adding a simple circuit, and two columns of a key matrix can be scanned by one common signal. Since it is possible, the number of terminals can be significantly reduced when an IC is formed.

[Brief description of the drawings]

FIG. 1 is a main part circuit diagram showing a configuration of a first embodiment of the present invention.

FIG. 2 is a main part circuit diagram showing a configuration of a second embodiment of the present invention.

FIG. 3 is a block diagram illustrating a schematic configuration of an embodiment of the present invention.

FIG. 4 is a timing chart for explaining the operation of the first embodiment.

FIG. 5 is a timing chart for explaining the operation of the second embodiment.

FIG. 6 is a block diagram showing a configuration of a conventional key input circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Liquid crystal display device 2 Key matrix 4 IC6 Common driver 10 Segment driver 13 Input circuit 14 Key decoder 20-23 Diode 120,121, ... Input terminal 130-132,134-136 Inverter 137,143 Comparator

Claims (2)

[Claims] A key matrix; an input terminal for inputting a key input signal from the key matrix; a key decoder for generating key data based on the key input signal;
In a key input circuit including a common driver for outputting a common signal and a segment signal for driving a liquid crystal display device, and a segment driver, the common signal sequentially increases in order from the first to the n-th (n: 3 or more). The same common signal is supplied as key scan signals to two columns of the key matrix, and two supply lines for supplying the common signals have opposite directions. A diode is inserted, a first input circuit having an input threshold voltage between the first and second voltage levels, and an input threshold voltage between the (n-1) th and nth input terminals. A key input circuit characterized by connecting in parallel a second input circuit located between the two voltage levels. 2. A key matrix, an input terminal for inputting a key input signal from the key matrix, a key decoder for generating key data based on the key input signal,
In a key input circuit including a common driver for outputting a common signal and a segment signal for driving a liquid crystal display device, and a segment driver, the common signal sequentially increases in order from the first to the n-th (n: 3 or more). The same common signal is supplied as key scan signals to two columns of the key matrix, and two supply lines for supplying the common signals have opposite directions. A diode is inserted into each of the input terminals, and an input threshold voltage becomes a voltage level between the first and second during the first period,
In the period, the input threshold voltage is the (n-1) th.
A key input circuit, wherein an input circuit that switches to a voltage level between the key input circuit and the n-th input circuit is connected.