JPH10133617A - Storage control device, method therefor and liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decrease the number of times of write in the same storage position and to improve durability of a storage medium when data indicating a setting state and the like of a display device is stored in a rewritable storage medium. SOLUTION: In this display control device, a wound in which at least one bit of a state '1' is included by a parity bit is stored in an EEPROM as adjustment level data, while zero is written in all other words. When the device is started, data is successively read out from the leading address of the EEPROM, data including a bit of a state '1' is detected (S91-S96), and it is used for controlling the device as adjustment level data (S97). Then zero is written in a retrieved address position (S98), while a value in which 1 is added to the detected address is held as a writing address of adjustment level data in cutting off a power source of the device (S100).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage control device and method using a CPU, a storage medium that is rewritable and can hold data when power is shut off, and a display device using the storage control device. About.

[0002]

2. Description of the Related Art Whether a display is a CRT or a display using a liquid crystal, the display needs to be adjusted so that many users can comfortably use it in various use environments.

FIG. 22 is a block diagram showing an example of a general liquid crystal display device. The liquid crystal display device shown in FIG.
Image data generator 1 including graphic board 1800
801 and a liquid crystal display panel 1 including a drive circuit (not shown)
811, a backlight 1810 for illuminating the liquid crystal display panel 1811 from the back, a lighting circuit 1809 for driving a fluorescent lamp included in the backlight while adjusting the brightness, and a panel controller 1 for controlling the liquid crystal display panel 1811
804, a power supply controller 1806 for supplying drive power to the liquid crystal display panel 1811, a DA converter 1805,
A thermistor 1812 for detecting the temperature near the liquid crystal panel,
A switch board 1813 for inputting a user's adjustment operation to the liquid crystal display device such as the brightness of the backlight 1810;
Panel controller 1804 and power supply controller 18
MPU1 which controls the operation of the entire liquid crystal display device by controlling the 06
807, power supply 180 for supplying power to the entire liquid crystal display device
8.

[0004] Also, 1802 is a graphic board 18.
The image bus 1803 transfers image data from the MPU 1 to the panel controller 1804. A data request signal 1803 from the MPU 1807 to the graphic board 1800 and an MPU 1
A control line including serial communication for mutually communicating between the 807 and the graphic board 1800.

The MPU 1807 has a ROM for storing a program to be executed by a built-in CPU, a RAM used for executing the program, an AD converter, a digital I / O port, and other timers / counters. MP
Of the storage means incorporated in the U1807, the ROM can only read out predetermined contents, and the RAM loses its stored contents when the power of the MPU 1807 is cut off.

The MPU 1807 operates according to a program stored in a built-in ROM.
When the display is performed on the liquid crystal display panel 1811,
Adjust the driving conditions of. For this, the thermistor 181
2 is input through a built-in AD converter, temperature information near the liquid crystal display panel 1811 is obtained, and optimal driving conditions for driving the liquid crystal display panel 1811 are selected. Here, the driving conditions are, for example, a driving time (horizontal frequency) of one line and a liquid crystal driving voltage. Based on the selected driving conditions, the driving time (1H) of one line is set in the panel controller 1804, and the liquid crystal driving voltage (Vop) is set in the power supply controller 1806 through the DA converter 1805. Next, the power supply controller 1806 is instructed to turn on the liquid crystal driving power, and the lighting circuit 1809 is instructed to turn on the backlight 1810.

[0007] Graphic card 1 from MPU 1807
When image data is requested to the image bus 180,
2, the image data for one line is transferred to the panel controller 1804. When the MPU 1807 measures the timing and instructs the panel controller to start driving for one line, the panel controller 1804 processes the received image data into a form that can be received by the liquid crystal display panel 1811 and transfers it. As a result, an image of one line is displayed on the liquid crystal display panel 1811.

FIG. 23 is a diagram showing the connection between the MPU 1807 and the switch board 1813. Variable resistor 1815, 1
817 and a digital switch 1816 are adjustment input means for performing adjustment so that the user can use the liquid crystal display device in an optimal use state. For example, the variable resistor 1817 is connected to the lighting circuit 1809 and enables the brightness of the backlight 1810 to be adjusted. That is, when the user operates the variable resistor 1817 on the switch board 1813, a luminance adjustment signal is given to the lighting circuit 1809, and the luminance of the backlight changes. Although individual functions and operations are not described in detail with respect to other adjustments, any of these input means can store the degree of adjustment even when the power of the entire liquid crystal display device is cut off. That is, when the power is turned on, the brightness adjustment variable resistor 1817 can automatically reproduce the degree of the brightness adjustment before the power is turned off by the adjustment position of the variable resistor 1817.

[0009]

However, recent display devices tend to employ an adjustment operation using a button switch. In the input means of the liquid crystal display device as described above, components such as a mechanical variable resistor and a digital switch that have been generally used for adjustment operation are far smaller than the size of a small tact switch or a membrane switch. Requires a lot of space, which is disadvantageous not only in terms of design and operability, but also in miniaturization and space saving of the device.

On the other hand, the tact switch and the membrane switch can only determine whether or not the user is operating at a certain moment, but have no function of storing the adjustment degree when the power is turned off. For this reason, in a display device using a button switch, it is necessary to have a memory means for storing a user's operation state (setting state of the apparatus) when the power is turned off and for reproducing this when the power is turned on again.

The memory means includes, for example, a method using an SRAM with a battery backup and a method using an EEPROM. Among them, the EEPROM does not require a battery and has advantages in cost and simplicity of design, but has a problem that the number of times of endurance of writing is relatively small.

[0012] The failure modes of the EEPROM are a write failure due to the deterioration of the tunnel oxide film constituting the floating gate (it becomes 0 even if 1 is written) and a charge pump failure, the former being dominant. Therefore, 1
There has been a problem that the number of times of writing per cell must be reduced and the apparent endurance of the device must be increased.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problem, and when data indicating a setting state of a display device is stored in a rewritable storage medium, the number of times of writing to the same storage location is reduced, It is an object of the present invention to provide a storage control device and method for improving the durability of a medium and a display device using the storage control device.

[0014]

A storage control device according to the present invention for achieving the above object has the following arrangement.
That is, a storage control device having a storage medium having a word having a predetermined number of bits as a rewritable unit, wherein the first data having a data configuration including N words including a predetermined word having at least one inversion bit is provided. Detecting means for detecting a storage position in the storage medium based on the predetermined word, and a position shifted by at least one word from a storage position of the first data recognized by the recognition means as a new storage position. A first writing unit for writing the second data having the data configuration to the new storage location in the storage medium; and a second data by the first writing unit among words stored in the first data. And second writing means for setting all bits of a word which is not updated by writing to a non-inverting state.

Preferably, the predetermined word is a head word of N words in the data configuration, and the detecting means sequentially reads data from a head address in a predetermined area of the storage medium, and detects at least one inversion bit. Is detected, the address of N words starting with the word is detected as the storage location of the first data.

Preferably, the predetermined word includes one odd parity bit for setting the number of inverted bits to an odd number.

[0017] Preferably, the predetermined word includes at least one bit which is always fixed in an inverted state.

Preferably, the apparatus further comprises reading means for reading the first data from a storage position detected by the search means, and wherein the second data writing means comprises a means for writing the first data after execution of the reading means. Before the implementation of the measures.

Preferably, the first data and the second data
The apparatus further includes control means for comparing data with the data and executing the first and second writing means when the first and second data are different.

A storage control device having another configuration according to the present invention for achieving the above object has the following configuration. That is,
A storage control device for performing storage control of a control range of a predetermined number of words in a storage medium having a word having a predetermined number of bits as a rewritable unit, the storage control device having N words and having at least one inversion bit Writing means for writing data having a data structure including a word into a predetermined storage location of the storage medium, counting means for counting the number of times of writing by the first writing means, and when writing data by the writing means,
Updating means for updating the storage position to be written by the writing means to a position shifted by at least one word when the number of writings counted by the counting means exceeds a predetermined value.

Preferably, holding means for holding a pointer indicating a storage position of a writing target by the writing means at a predetermined address in the control range, and updating of the storage position of the writing target by the writing means by the updating means. And a second updating unit that updates the storage position held by the holding unit when the operation is performed.

Preferably, the data read position and the data storage position of the writing means are determined by a pointer held by the holding means.

Preferably, the counting means holds count information indicating the number of times of writing at a storage location having a predetermined relationship with a storage location to be written by the writing means.

Preferably, the storage position of the count information in the counting means is a position following the storage position to be written by the writing means.

Preferably, the apparatus further comprises control means for executing writing by the writing means when new data to be written by the writing means is different from data previously stored.

Further, in the display device of the present invention that achieves the above object, the storage control device described above is used to hold data indicating the setting state of the display device.

A storage control method according to the present invention for achieving the above object is a control method for a storage control device having a storage medium having a word having a predetermined number of bits as a rewritable unit. A detection step of detecting, based on the predetermined word, a storage position of the first data having a data configuration including N words including a predetermined word having an inverted bit, based on the predetermined word; A first writing step in which a position shifted by at least one word from the storage position of one data is set as a new storage position, and the second data having the data configuration is written in the new storage position in the storage medium; A second writing method for setting all bits of a word that is not updated by the writing of the second data in the first writing step among the stored words of one data in a non-inverted state Provided with a door.

According to another aspect of the present invention, there is provided a storage control method for performing storage control of a control range of a predetermined number of words in a storage medium having a word having a predetermined number of bits as a rewritable unit. A storage control method for writing data having a data configuration including a predetermined word having N words and including at least one inversion bit to a predetermined storage location on the storage medium; A counting step of counting the number of times of writing in the step; and, when writing the data in the writing step, when the number of times of writing counted in the counting step exceeds a predetermined value, at least one storage location to be written in the writing step is determined. An updating step of updating to a position shifted by words.

[0029]

Preferred embodiments of the present invention will be described below with reference to the accompanying drawings.

[First Embodiment] FIG. 1 is a block diagram showing a configuration of a liquid crystal display device according to an embodiment of the present invention. The liquid crystal display device according to the present embodiment is included in an image data generation unit 101 including a graphic board 100, a liquid crystal display panel 111 including a drive circuit (not shown), a backlight 110 for illuminating the liquid crystal display panel from the back, and a backlight 110. A lighting circuit 109 for driving a fluorescent lamp while adjusting brightness, a panel controller 104 for controlling a liquid crystal display panel 111, a liquid crystal display panel 111
, A power supply controller 106 for supplying driving power to the LCD panel, a thermistor 112 for detecting a temperature near the liquid crystal panel, a switch board 113 for inputting a user's adjustment operation to the liquid crystal display device such as a backlight brightness, a panel. MP that controls the controller 104 and the power supply controller 105 to control the operation of the entire liquid crystal display device
U107, E that stores the adjustment state of the user when the power is turned off
The EPROM 114 includes a power supply 108 for supplying power to the entire liquid crystal display device.

Reference numeral 102 denotes a graphic board 100
Is an image bus for transferring image data from the computer to the panel controller 104. A control line 103 includes a data request signal from the MPU 107 to the graphic board 100 and serial communication for mutually communicating between the MPU 107 and the graphic board 100.

The liquid crystal display panel 111 is a display panel using a ferroelectric liquid crystal (hereinafter referred to as FLC) as a liquid crystal.
For example, a display of 1280 × 1024 pixels is performed using RGBW as one pixel. The liquid crystal material used here is a mixture containing biphenyl-based and phenylpyrimidine-based as main components. The phase transition temperature of the liquid crystal material is as follows. That is, Cryst → (-10 ℃) → Sm → (63 ℃) → SmA → (72 ℃) → Ch (90 ℃)
→ Iso.

The liquid crystal display panel 11 using FLC
In No. 1, the optimum driving condition changes depending on the temperature. FIG. 2 is a diagram illustrating driving conditions of the liquid crystal display panel 111. The driving conditions in this embodiment include a driving voltage (Vop), which is a voltage of a driving waveform applied to the liquid crystal, and one horizontal scanning time (1H), which is a time for driving one driving line. FIG.
As shown in (1), the optimum driving condition changes so that the product of Vop and 1H becomes smaller as the temperature becomes higher. MPU107
Is the temperature near the liquid crystal display panel 111 (thermistor 1
12 is detected, and 1H is set to the panel controller 104, and Vop is set to the power supply controller through the DA converter 105. This operation is called a temperature compensation operation.

In an actual temperature compensation operation, it is necessary to adjust a slight difference in characteristics between the liquid crystal display panels 111 and a variation in an electric circuit. Therefore, the liquid crystal display panel 1
In order to adjust the drive condition determined by the temperature near 11, an offset is given to the temperature information obtained by AD-converting the temperature signal. This offset adjustment is called image quality adjustment.

A liquid crystal panel 111 using the above-mentioned FLC
Is composed of one pixel consisting of RGBW sub-pixels.
Color display is performed, and color display corresponding to 32,000 colors can be pseudo-displayed by a technique such as an error diffusion method.
The image data processing for this is performed by the graphic board 100.
However, when a display close to a natural color such as a full-color photograph is performed, the display of one color is obtained by synthesizing the display of several surrounding pixels, so that the resolution is somewhat sacrificed. For this reason, whether the display is close to a natural color, or a high-resolution 16-color display suitable for displaying fine characters or the like, or a display in some state intermediate between the two, It is preferable to select and use any one of them. This adjustment is called color adjustment.

The lighting circuit 110 receives the supply of power from the power supply 108 and turns on the backlight 110. The turning on / off control is received from the MPU 107, and a dimming signal is received from the MPU 107 through the DA converter 105.

FIG. 3 shows the MPU 107 and the switch board 11
FIG. 3 is a diagram showing connection of No. 3; Tact switches 115-12
Reference numeral 0 denotes a switch pressed by the user for adjustment. When the switch is operated (pressed), the L level is input to the digital I / O port 121 of the MPU 107 when the switch is not operated (released). You. Tact switch 1
15 is an adjustment switch for lowering the brightness, tact switch 116 is an adjustment switch for increasing the brightness, tact switch 117 is an adjustment switch for decreasing the color, tact switch 118 is an adjustment switch for increasing the color,
The tact switch 119 is an adjustment switch for reducing image quality, and the tact switch 120 is an adjustment switch for increasing image quality.

Next, the operation of the liquid crystal display device of this embodiment will be described according to a program executed by the MPU 107.

FIG. 4 is a flowchart of the main program executed by the MPU 107. Note that the control program for realizing this flowchart is the RO program in the MPU 107.
M, and the CPU executes this.

When the power of the liquid crystal display device is turned on, the MPU 1
When power is supplied to 07, execution of the program starts from "start" in FIG. First, in step S11 (initial setting), initial settings of peripheral circuits incorporated in the MPU 107, initial settings of the panel controller 104, and initial settings of variables necessary for program execution are performed. Next, in step S12, the contents of the EEPROM 114 are read, and the state (adjustment by the user) of the liquid crystal display device immediately before the power is turned off is reproduced. The adjustments by the user include brightness of the backlight (brightness adjustment), parameter adjustment for image data processing of the graphic board 100 (color adjustment), and fine adjustment of the liquid crystal driving conditions (image quality adjustment). These are called a luminance level, a color level, and an image quality level. The operation of “memory read” in step S12 will be further described later.

Next, the flow advances to step S13 to prepare for driving the liquid crystal by the "ON sequence".

The "ON sequence" will be described with reference to FIG. FIG. 5 is a flowchart showing the procedure of the ON sequence. In the “ON sequence”, first, “thermistor monitoring” is performed in step S41, and a voltage signal from the thermistor 112 is input through an AD converter 121 built in the MPU 107. Next, proceeding to step S42, the optimal liquid crystal driving conditions "1H (horizontal scanning period)" and "Vop" are selected based on the obtained temperature information and the image quality level obtained in step S12. . The selected “1H” is sent to the panel controller 104 and the “Vop” is sent to the DA converter 105.
Power supply controller 10 as an analog voltage signal through
Set to 6

Then, the process proceeds to a step S43, where the counters 1 and 2 are initialized. Here, the counter 1 is a counter for counting the number of driving lines of the liquid crystal. As will be described later, this program counts the number of liquid crystal drive lines, measures the elapse of a certain time based on the number, and monitors whether the user is operating the switch. For example, when the driving time 1H of one line is 80 μsec, if the counter 1 is initialized at 1250 and the countdown is reduced to 0 every time one line is driven, the switch is monitored every 100 ms.

The counter 2 is a counter for counting the number of times of switch monitoring. Monitor the switch,
If any adjustment operation has been performed, temperature compensation is performed, but even if no adjustment operation is performed by the user, thermistor is monitored at regular time intervals to perform temperature compensation. For example, if counter 2 is initialized with 300, 3
Thermistors are monitored every 00 switches, at least every 30 seconds in the above example.

Then, the process proceeds to a step S44, wherein the MPU 10
A signal 7 is supplied to the power supply controller 106 to start outputting the liquid crystal driving power supply. The driving power is supplied to the liquid crystal display panel 111 only when this signal is turned on.

Next, in “dimming signal output” in step S45, the MPU 107 gives the luminance level to the lighting circuit 109 through the DA converter. Further, step S46
In “BL lighting signal output”, the MPU 107 turns on the lighting signal to the lighting circuit 109, and the backlight 110
Is turned on. The “ON sequence” is as described above.

Returning to FIG. 4, the continuation of the main program will be described. In step S14, the value of the counter 1 is checked. If the counter 1 is not 0, the process proceeds to step S15, and if the counter 1 is 0, the process proceeds to step S20.

In step S15, the liquid crystal display panel 11
One one-line drive is performed. Here, the MPU 107 requests the graphic board 100 for one line of image data. The graphic card 100 has a liquid crystal display panel 11
The image data for one line to which the address on one screen is added is transferred to the panel controller 104. MPU1
07 measures the timing and instructs the panel controller 104 to start display driving for one line. The panel controller 104 processes the received image data into a form that can be received by the liquid crystal display panel 111 and transfers the processed image data according to an instruction from the MPU 107. As a result, 1
The image data of the line is displayed.

When the driving of one line is performed, that is, when the start of driving of one line is instructed, the process proceeds to step S16, and the content of the counter 1 is decremented by one. Next, in step S17, it is determined whether there is a received command in the serial communication reception buffer. If there is a received command, the process proceeds to step S18, where processing corresponding to the command is executed, and in step S19, status transmission is performed to notify the result to the graphic card. Thereafter, the program returns to step S14 again, and continues driving for each line until the counter 1 becomes 0.

Now, in step S14, the counter 1
Becomes 0, that is, when about 100 ms has elapsed since driving for each line is continued while performing command processing, the program branches to step S20 to perform “switch monitoring”.

"Switch monitoring" means switch board 11
This is a process for checking whether or not the tact switches 115 to 120 provided in 3 are depressed by the user.
The H / L level of the digital I / O port to which signals from the tact switches 115 to 120 are connected is checked, and if there is at least one L level signal, it is determined that an input operation has been performed (step S21). ). If it is determined that the input operation has been performed, the process proceeds to step S22, where the operation of the user is analyzed, the luminance / color / image quality level is changed, and adjustment (adjustment operation) according to the level is performed.

If it is determined in step S21 that the input operation has not been performed, the process proceeds to step S26, and the content of the counter 2 is decremented by one. At this time, if the content of the counter 2 becomes 0, the process proceeds from step S27 to step S22, and the "adjustment operation" and the temperature compensation operation are executed as in the case where the switch is operated.

If the value of the counter 2 is not 0 in step S27, the process proceeds to step S28, where the counter 1 is initialized, and then returns to step S14. Then, the above processing is repeated.

Next, the "adjustment operation" will be described with reference to FIGS.
This will be described below. FIG. 6 is a flowchart showing the procedure of the adjustment operation. FIG. 7 is a flowchart showing an adjustment procedure of each adjustment item. The adjustment items in the present embodiment are luminance, color, and image quality. For each item, it is determined whether the user has performed an up operation or a down operation, and the level (luminance level, color level, This is a subroutine for updating any one of the image quality levels.

First, referring to the flowchart of FIG. 7, when an up operation is detected in step S61, the process proceeds to step S66. Here, when the down operation is detected, the present process is terminated as it is. That is, up
The operation is valid only when either one of the switches is operated or down, and invalid when operated simultaneously. If only the up operation has been performed, step S
Proceed to 67 to raise the level of the corresponding item by one. In step S68, it is determined whether or not the level of the item has exceeded the upper limit. If the level has exceeded the upper limit, the level of the item is set to the upper limit (step S69).

When only the down operation is performed, the process proceeds to step S63, and the level of the item is lowered by one. Then, in step S64, it is determined whether or not the level of the item is lower than the lower limit. If the level is lower, the process proceeds to step S64 to set the level of the item to the lower limit.
Note that the level values of the luminance level, the color level, and the image quality level set by the processing of FIG.
07 is stored in the RAM.

In the "adjustment operation" shown in FIG.
The adjustment item operated based on the input signal from the switch board 113 is determined, and the procedure of FIG. 7 is executed for the operated adjustment item.

First, in step S51, the value immediately before the luminance level is stored as the immediately preceding level. Next, in step S52, the above-described processing of FIG. 7 is executed for the luminance level. Then, in step S53, the current luminance level is compared with the immediately preceding level stored in step S51. As a result of the comparison, if it is determined that the brightness level has been updated, the new brightness level is passed through the DA converter 105 to the lighting circuit 109 in step S54.
Set to

Next, in steps S55 to S57, processing similar to the above-described luminance level is performed for the color level.
If the color level has been changed, the new color level is notified to the graphic board 100 via serial communication (step S58).

Next, the image quality level is updated, and the "temperature compensation operation" is always executed using the temperature information and the image quality level obtained by "thermistor monitoring" regardless of whether or not the level is actually changed. I do. That is, step S5
In 9, the image quality level is set according to the procedure shown in FIG. 7, and the temperature compensation processing in steps S23 and S24 in FIG. 4 is executed.

FIG. 8 is a flowchart showing the procedure of the temperature compensation process. First, in step S31, the value of the thermistor acquired in step S23 and the current image quality level are added to determine an offset value. Next, in step S32, the value stored in the offset position of the 1H table is set as 1H, and in step S33, the value stored in the offset position of the Vop table is set as the liquid crystal drive voltage.

After executing the above “temperature compensation operation”,
Proceeding to step S25 in FIG. 4, the initialization of the counter 1 and the initialization of the counter 2 are executed, and the operation returns to the driving operation for each line again.

Next, the operation of the present liquid crystal display device when the power is turned off will be described.

FIG. 9 is a time chart showing the operation when AC power is supplied to the liquid crystal display device from the outside and when the AC power is cut off. The power supply 108 lowers the signal ACF to the L level when the AC power input is cut off or the power switch of the power supply 108 is turned off.
07, indicating that the power supply has been cut off, and at the same time, the power supply output is held for 20 ms from here. FIG. 9B
As shown in (2), during this 20 ms, the backlight 110 is turned off, black is written on the entire surface of the liquid crystal display panel 11 (all black erasure), and the liquid crystal driving power supply is shut off.

In the program of the MPU 107, the control is transferred to the interrupt program (OFF sequence) by the edge at which the ACF signal becomes L level. FIG.
9 is a flowchart showing a control procedure of an OFF sequence executed by an interrupt program at the time of FF.

First, if one-line driving has been performed when control is transferred to the interrupt program, the control waits for the end of the one-line driving (step S71). Next, a turn-off signal of the backlight 110 is output to the lighting circuit 109 (step S72), and subsequently, the adjustment level of the user at this time, that is, the luminance level, the color level, and the image quality level are written into the memory (EEPROM 114). (Step S7
3). Then, black is written on the entire surface of the liquid crystal display panel 111 in "all liquid crystal erasure" in step S75, and the liquid crystal driving power is shut off in "liquid crystal driving power OFF" in step S75.

FIG. 11 is a diagram showing a data structure of an EEPROM for holding the adjustment level in the present embodiment. As shown in FIG. 11B, the data of the adjustment level is formed of one word of 16 bits. The image quality level is a signed integer of a maximum of ± 31 levels, the luminance level is an unsigned integer of 32 levels, and the color level is an unsigned integer of 8 levels, and 7, 5, and 3 bits are assigned to each. The parity bit is set such that the number of 1 bits included in one word is odd. Therefore, this word must be 1
There is more than one bit. FIG. 11A shows the EEP
The assignment of the entire ROM 114 is shown. EEPROM 114
Has a capacity of 1024 bits, 16 bits / word × 64
It is a word composition. In the present embodiment, the adjustment level data is stored in one word, and 0 is stored in all other words.

FIG. 12 is a flowchart showing the procedure for writing data to the memory in this embodiment. The flowchart in FIG. 12 shows the details of step S73 in FIG. In step S81, the R in the MPU 107
The luminance level value, the color level value, and the image quality level value are read from the AM, and the adjustment level data of one word is configured by the allocation shown in FIG. Next, in step S82, the adjustment level data is written to the address of the EEPROM 114 determined at the end of "memory read" described later. MPU 107 to EEPROM 114
Data transfer to the memory cell is completed in about 20 μsec, but writing to the actual memory cell requires a maximum of 10 ms. For this reason, in the “OFF sequence”, first, data transfer to the EEPROM 114 is performed as “memory write”, a write instruction is issued, and then “all-black liquid crystal erase” is performed.
And after performing "LCD drive power OFF",
Wait for the end of the write operation of No. 14 (step S76).

Next, the "memory read" operation (step S12 in FIG. 4) performed when the display device is started up will be described with reference to the flowchart shown in FIG. This "memory read" is for reading the adjustment level data from the EEPROM 114, and is executed immediately after the power is turned on to the liquid crystal display device as shown in FIG. For this reason, although the address at which the adjustment level data is stored is unknown, the memory read processing described later (FIG. 1)
According to 3), the data 1 is stored in the EEPROM 114.
The word contains at least one bit of "1", and all parts other than the adjustment level data are stored with "0". That is, reading may be performed in order from address 0 until a word including 1 is found one by one.

First, in step S91, 0 is set to the address value to be read. Next, in step S92, it is determined whether or not the address value has exceeded the upper limit of the address of the EEPROM 114. Here, if the address value is E
If it is within the address range of the EPROM 114, one word stored at the address is read (step S93). If the data does not include 1, the address value is counted up until the address value exceeds the upper limit or until a word containing 1 is detected.
Words are read out word by word (steps S92, S94, S9
5).

In step S92, if the address value is E
If the upper limit of the EPROM 114 is exceeded, it means that the desired data has not been found, and the process proceeds to step S10.
Go to 5. In step S105, 0 is set as the address used in the above-described memory writing (FIG. 12), and in step S104, default values are set in the luminance level, color level, and image quality level, and the routine returns.

If 1 is included in the read word, the flow advances from step S94 to step S96 to perform a parity check on the data stored in the word.
If the parity check is normally performed, step S97
Then, the luminance level, the color level, and the image quality level are decoded from this word. Further, 0 is written in the word from which the data was read (step S98), and when the writing to the memory in step S98 is completed, the address is advanced by 1 (steps S99, S100). This updated address value becomes an address to be used in “memory writing (FIG. 12)” later.

On the other hand, if the parity is not correct in step S96, it is assumed that some error has occurred during writing or reading to the EEPROM 114, and that the data before the power was turned off was lost. Therefore, first, the process proceeds to step S101, where 0 is written to all bits of the word of the address, and when the writing is completed, the address is incremented by 1 (steps S102 and S103).
This updated address value is used later in the memory or landing process, as in step S100. Then, in step S104, default values are set for the luminance level, the color level, and the image quality level.

By the above procedure, the address at which data is stored is advanced by one for each write, and all addresses except one word at which data is stored are kept at 0. Further, the EEPROM 114 in this embodiment has a 64-word configuration, and each time power is turned off / on, writing is performed twice for each word. Therefore, the number of times of writing per word is reduced to 2 ÷ (64 words ÷ 1 word / time) = 1/32. This corresponds to the fact that the apparent endurance of writing can be increased 32 times when the EEPROM 114 is used.

On the other hand, at the time of memory reading, in the present embodiment, 32 words must be read on average, but reading of one word is about 20 μsec, and it can be determined that there is no problem when compared with the rise time of the device.

In the above embodiment, at least one bit is included in one word serving as data by using odd parity bits. However, if there is no problem in reliability required for data, this word is used. It is also possible to adopt a configuration in which the parity bit is always set to 1 in the embodiment.

Further, in this embodiment, the time during which the power supply can be operated when the power is turned off (the holding time of the power supply 108) is 20 ms.
During this time, there is only one memory write time,
Although the data is only one word, it is possible to write data of two or more words when the holding time is long and there is a lot of data to be stored. In this case, after reading the data, it is necessary to write 0 to a word that does not overlap with a portion to which data is to be written next among the portions where the read data is stored.

For example, as shown in FIG. 14, it is assumed that adjustment level data composed of N words (0 <N <W) is stored in an EEPROM having a W word structure, and an S word (0
It is assumed that the address is shifted by <S ≦ N).
Here, the average number of times of writing is (average number of times of writing) = (number of times of writing in one OFF / ON) / (number of times of writing). Here, the number of times of writing in one OFF / ON is the sum of S times of writing 0 to the shifted word at the time of reading and N times of the adjustment level data of N words written at the time of writing. Number of times of writing in OFF / ON times) = N [word] + S
[Word]. In addition, the number of cases of writing is such that W words are used by shifting S words at a time, so (number of cases of writing) = W [words] ÷ S [words].

Therefore, the average number of times of writing is (average number of times of writing) = (N [word] + S [word]) ÷ (W [word]
÷ S [word]). This means that when using the EEPROM 114,
The apparent endurance of writing is ((W [word] ÷ S [word])]
This corresponds to (N [word] + S [word]) times magnification.

The memory reading when the adjustment level data is composed of N words as described above is performed, for example, as follows. First, a word including a parity bit is set as a head word of the N words. Then, if a word containing 1 is detected in step S94 of FIG. 13, the data of the N words following the word is read to obtain the adjustment level data.

In the above embodiment, in the memory reading process at the time of starting the liquid crystal display device, the EEPR
The readout of the adjustment level data from the OM 114 and writing 0 after the readout (FIG. 13, step S98) are not limited to this. If the power holding time at the time of power-off is sufficient, at the time of the memory writing process at the time of power-off, FIG.
New adjustment level data is written to the address held in step S100, and 0 is added to the immediately preceding address.
May be written.

In the case where the above-described processing procedure is adopted, the adjustment level data is stored in the EEPROM 114 until it arrives in the memory. Therefore, the adjustment level data to be newly written and the EEP
It is also possible to compare the adjustment level data stored in the ROM 114 and execute data writing only when the two are different.

FIG. 15 shows EEP only when the adjustment level data has changed during memory writing when power is turned off.
9 is a flowchart illustrating a procedure for executing writing to a ROM. When applying this flowchart,
Step S9 in the memory reading procedure shown in FIG.
8. S99 is not executed.

First, in step S81. FIG.
11B, the luminance level, the color level, and the image quality level stored in the RAM of the MPU 107 are used.
The adjustment level data according to the format of is generated.
Next, in step S83, step S1 in FIG.
The adjustment level data stored at the address immediately before the address value obtained in 00 is acquired from the EEPROM. Then, in step S84, step S8
The adjustment level data generated in step S1 is compared with the adjustment level data acquired in step S83, and if they match, the process is terminated.

If the two do not match in step S84, it is determined that the adjustment level has been updated.
Proceed to step S85. In step S85, the address obtained in step S100 in FIG.
The adjustment level generated in step (1) is written. In the subsequent step S86, 0 is written to the address immediately before the adjustment level.

According to the above-described procedure, when the adjustment level changes, the EEPROM is written, so that the durability is further improved.

In the above-described processing at the time of writing to the memory, the case where the adjustment level data is composed of one word has been described. However, as described with reference to FIG. 14, the adjustment level data is composed of a plurality of words (N words). It is apparent that the procedure described with reference to FIG. 15 can be applied to the case where the shift amount is S words for one time.

In the first embodiment, the EEPRO
Although the entire area (addresses 00H to 3FH) of M114 is used, an arbitrary area may be used. Further, in the above embodiment, the used address is the EEPROM 11
When the address reaches the address 3FH of No. 4, the next memory write address returns to the head address (00H in this example). That is, step S100 in FIG.
After the process in S103, it is determined whether or not the updated address has exceeded the maximum value (3FH) of the address, and if it has, the process of returning the address value to 00H is performed.

[Second Embodiment] Next, a second embodiment of the present invention will be described. The second embodiment is different from the first embodiment in that the data structure and the use procedure on the EEPROM are different from each other, and provides another method for improving the apparent endurance of the EEPROM.

The configuration of the liquid crystal display device according to the second embodiment is the same as that of the first embodiment (FIG. 1). However,
In the second embodiment, the data storage format in the EEPROM 114 and the memory control procedure by the MPU 107 are different. Hereinafter, this point will be described.

The control operation of the MPU 107 in the second embodiment is performed according to the flowcharts shown in FIGS. 4, 5, 6, 7, 8, and 10 described in the first embodiment. However, for writing and reading of the memory, operations different from those of the first embodiment (FIGS. 12 and 13) are performed.

First, the EEPRO in the second embodiment
The memory allocation on M114 and the stored data structure will be described with reference to FIG. FIG. 16 is a diagram showing a data configuration of an EEPROM for holding an adjustment level according to the second embodiment.

In FIG. 16A, the EEPROM 1
14 has a capacity of 1024 bits, and 16 bits / word ×
It is composed of 64 words. At address 00h, a pointer indicating the address at which data is stored is stored. In the figure, the address k is stored. The address k stores one word of data, and the address (k + 1) stores a counter value indicating how many times the data of the address k has been written to the same address.

FIG. 16B is a diagram showing bit allocation of data. As in the first embodiment, the stored data is the adjustment state of the liquid crystal display device set by the user immediately before the power is turned off, that is, the luminance level, the color level, and the image quality level. The image quality level is a signed integer of a maximum of ± 31 levels, the luminance level is an unsigned integer of 32 levels, and the color level is an unsigned integer of 8 levels.
Allocate 5 or 3 bits. The parity bit is set so that the number of 1 bits included in one word is either a predetermined even number or an odd number.

Next, the memory read operation performed when the power is turned on will be described with reference to the flowchart shown in FIG. FIG. 17 is a flowchart illustrating a memory read procedure in the second embodiment. First, in step S111, a pointer stored at a predetermined address (00h in this embodiment) is read, and in step S112, parity is checked. The address where the pointer is stored is fixed, and therefore is always 00h in this example.

If the parity is correct in step S112, the flow advances to step S113 to read the adjustment level data (one word) from the address indicated by the pointer read in step S111 (address k in FIG. 16).
Then, in step S114, the parity is checked. If the parity in step S114 is correct, the process proceeds to step S115, in which the adjustment level data is decoded to obtain a luminance level, a color level, and an image quality level.
It is set in the liquid crystal display control device.

Then, the process proceeds to a step S116, wherein a counter value is read from the address next to the address pointed by the pointer (address k + 1 in FIG. 16), and a step S1 is executed.
At 17 the parity is checked. If the parity is correct, the flow advances to step S118 to decrease the counter value by one. As a result, if the counter value does not become 0, the process proceeds to step S126, and the value is returned to the original address (k + 1).
Write to.

On the other hand, if the counter value is 0 in step S119, the flow advances to step S122 to advance the value of the pointer by 2 (k + 2 in FIG. 16). Then, this is written as a new pointer at address 00h (step S123), and when the writing of the pointer is completed, C is written at address k + 2 as the initial value of the counter (steps S124 and S125). If the parity of the read counter value is not correct, the process proceeds from step S117 to step S122. If the parity of the read counter is not correct, the number of times of writing becomes unknown, and there is a possibility that normal writing cannot be performed at the address. Therefore, the process proceeds to step S122 to update the location where the adjustment level data and the counter value are written. The above processing is performed.

If the parity of the read adjustment level data is not correct, some error occurs when writing or reading data to or from the EEPROM 114, and it is determined that the data before the power is turned off is lost. The default values are set for the color level and the image quality level (steps S114 and S121). Then, the processing of steps S122 to S127, that is, the processing of updating the storage positions of the adjustment level data and the counter and writing the initial value C as the counter value is performed.

Further, even if the parity of the read pointer is incorrect, the process proceeds from step S112 to step S1.
Proceed to 20. In step S120, the pointer is returned to 0, and the storage positions of the adjustment level data and the counter value are returned to the initial state. Then, steps S121 to S
127 is performed. In this embodiment, since the data is stored in the even address and the counter is stored in the odd address following the even address, the minimum value of the pointer is 2 (2 is added to the pointer value in step S122 described later). . Of course, if you store data at odd addresses and then store counters at even addresses,
What is necessary is just to set the initial value of the pointer in step S120 to -1.

The memory write operation performed when the power is turned off will be described with reference to the flowchart shown in FIG. FIG. 18 is a flowchart showing a memory writing procedure according to the second embodiment. Note that the memory write process shown in FIG. 18 is an interrupt process by an ACF signal when the power is turned off, as in the first embodiment.

In step S131 of FIG.
The adjustment level data (one word) is configured from the luminance level, the color level, and the image quality level stored in the RAM 07 in the allocation shown in FIG. Subsequently, step S1
At 32, the value of the pointer after the above-described memory read processing is obtained. Then, in step S133, the address indicated by the pointer is accessed, and the adjustment level data generated in step S131 is written.

According to the above procedure, the address at which the data is stored advances by two every C times of writing. EEPROM2
Numeral 14 has a structure of 64 words, and the storage area of the data and the counter is 2 words × 31 in the area other than the storage area of the pointer. Therefore, the number of times of writing per word is C times ÷ (C times × 31 places) = It is reduced to 1/31. This corresponds to the fact that the apparent endurance of writing can be increased 31 times when the EEPROM 114 is used. Therefore, according to the second embodiment, the apparent durability of the EEPROM is improved.

In the second embodiment, similarly to the first embodiment, the time during which the power supply can be operated when the power is turned off (the power supply 10).
8 is 20 ms, and the memory write time can be obtained only once during this period. Therefore, the data is limited to one word. However, when the power supply has a long holding time and a large amount of data is stored, it is possible to write data of two or more words. For example, N words (0
In the case where data of <N <W) are stored and the pointer is shifted every C times of writing, the average number of times of writing can be obtained as follows.

In general, the average number of times of writing is represented by (average number of times of writing) = (number of times of writing to one address) / (number of times of writing). Here, the number of times of writing at one address until the entire memory is used one time is C, and the number of writes performed until the entire memory is used one time is one word out of W words used as a pointer. (Number of writing cases) = (W [word] −1 [word]) ÷ N [word] × C
[Times].

That is, the average number of times of writing is (average number of times of writing) = C [times] ÷ ((W [word] −1 [word])
{N [word] × C [times]) = N [word] ÷ (W [word] −1 [word]), and has nothing to do with C. On the other hand, the pointer is written each time the data storage address is changed, that is, every C times of data writing. Therefore, the average number of write times of the word stored in the pointer is (average number of write times) = 1 ÷ C [times]. Here, if the initial value C of the counter is C ≒ (W [word] −1 [word]) ÷ N [word], the writing frequency can be substantially the same over the entire memory. This is because, when using the EEPROM 214, the apparent endurance of writing is ((W [word]-
1 [word]) ÷ N [word]).

As in the first embodiment, if the power holding time of the power-off word can be made sufficiently long, the counter and the pointer can be updated at the time of writing to the memory. is there. In this case, EEP
If there is no change from the adjustment level data stored in the ROM, the writing process can be prevented from being performed, and the durability of the EEPROM is further improved.

FIG. 19 is a flowchart showing another procedure of the memory writing process according to the second embodiment. Note that, when the flowchart is executed, a reading process when the adjustment level data is normally read (see FIG. 1)
The counter value and pointer in 7) are not updated.
That is, if the parity is correct in step S117, the memory read processing ends as it is.

In FIG. 19, first, at step S131
To set the brightness level, color level and image quality level to MPU10.
7 to read out the adjustment level data. Then, in step S134, a pointer value is obtained, and the EEPROM 1 indicated by the pointer value is obtained.
The adjustment data is obtained from the 14 addresses. Step S
In 135, the adjustment level data obtained in step S131 is compared with the adjustment level data obtained in step S134. If the two match, the memory writing is not performed.
This processing ends.

On the other hand, if they do not match in step S135, the flow advances to step S136 to decrement the counter value stored at the address of the pointer value + 1. As a result,
If the counter value has become 0 (step S13
7) In step S138, the storage location is updated. In addition,
The update of the storage location is performed in steps S122 to S122 in FIG.
This is the same as the processing in step S126. Then, in step S133, the adjustment level data generated in step S131 is written to the address indicated by the pointer value.

By the above processing, the number of times of writing to the EEPROM can be reduced, and the apparent durability can be improved.

In step S122 of FIG. 17, if the value of the pointer is increased and exceeds the maximum address value of the EEPROM 114 (3FH in this example), the pointer value is set to 02H. As a result, the storage positions of the adjustment level data and the counter value can be circulated in the storage area of the EEPROM.

As described above, according to each of the above embodiments, the number of writes per word of the storage device can be reduced without increasing the cost only by adding the program, and the writing of the entire storage device can be performed. It is possible to increase the number of times of durability. In addition, even when an element having a relatively small number of write endurance times is used as a storage device in an EEPROM or the like, a liquid crystal display device that operates stably for a long time can be provided.

[Other Embodiments] Even if the present invention is applied to a system composed of a plurality of devices (for example, a host computer, an interface device, a reader, a printer, etc.), an apparatus composed of one device (for example, For example, the present invention may be applied to a copying machine, a facsimile machine, and the like.

Further, an object of the present invention is to provide a storage medium storing a program code of software for realizing the functions of the above-described embodiments to a system or an apparatus, and to provide a computer (or CPU) of the system or apparatus.
And MPU) read and execute the program code stored in the storage medium.

In this case, the program code itself read from the storage medium implements the functions of the above-described embodiment, and the storage medium storing the program code constitutes the present invention.

As a storage medium for supplying the program code, for example, a floppy disk, hard disk, optical disk, magneto-optical disk, CD-ROM, CD
-R, a magnetic tape, a nonvolatile memory card, a ROM, or the like can be used.

When the computer executes the readout program code, not only the functions of the above-described embodiment are realized, but also the OS (Operating System) running on the computer based on the instruction of the program code. ) May perform some or all of the actual processing, and the processing may realize the functions of the above-described embodiments.

Further, after the program code read from the storage medium is written into a memory provided in a function expansion board inserted into the computer or a function expansion unit connected to the computer, based on the instructions of the program code, It goes without saying that the CPU included in the function expansion board or the function expansion unit performs part or all of the actual processing, and the processing realizes the functions of the above-described embodiments.

When the present invention is applied to the storage medium, the storage medium stores program codes corresponding to the above-described flowcharts. As shown in the example of the memory map, the program modules are stored in the storage medium.

That is, as shown in FIG. 20, at least the program code of each of the "detection processing module", "first writing processing module" and "second writing processing module" may be stored in the storage medium.

Here, each of the modules constitutes a program code for performing storage control of a storage medium (for example, an EEPROM) in which a word having a predetermined number of bits is a rewritable unit. The detection processing module detects a storage position in the storage medium of the first data having a data configuration including N words including a predetermined word having at least one inverted bit based on the predetermined word. Do. Further, the first writing processing module sets a position shifted by at least one word from a storage position of the first data recognized in the recognition processing as a new storage position, and stores the new storage position in the storage medium in the new storage position.
A first write process for writing the second data having the data configuration is realized. Furthermore, the second write processing module is configured to perform a second write that sets all bits of a word that is not updated by the writing of the second data by the first write processing among the stored words of the first data in a non-inverted state. The processing is realized.

Further, as shown in FIG. 21, each program module of “write processing module”, “counting processing module” and “update processing module” may be stored.

Here, each program module performs storage control of a control range of a predetermined number of words in a storage medium (for example, an EEPROM) in which a word having a predetermined number of bits is a rewritable unit. Then, the writing module implements a writing process of writing data having a data structure including a predetermined word having N words and including at least one inversion bit to a predetermined storage location of the storage medium. The counting module implements a counting process for counting the number of times of writing by the first writing process. Further, when writing the data by the writing process, if the number of times of writing counted by the counting process exceeds a predetermined value, the update processing module shifts the storage position to be written by the writing process by at least one word. Perform update processing to update to.

[0125]

As described above, according to the present invention,
When data indicating the setting state of the display device is stored in a rewritable storage medium, the number of times of writing to the same storage position can be reduced, so that the durability of the storage medium is improved.

[0126]

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating driving conditions of a liquid crystal display panel 111.

FIG. 3 is a diagram showing a connection between an MPU 107 and a switch board 113.

FIG. 4 is a flowchart of a main program executed by the MPU 107.

FIG. 5 is a flowchart illustrating a procedure of an ON sequence.

FIG. 6 is a flowchart illustrating a procedure of an adjustment operation.

FIG. 7 is a flowchart illustrating an adjustment procedure of each adjustment item.

FIG. 8 is a flowchart illustrating a procedure of a temperature compensation process.

FIG. 9 is a time chart showing operations when AC power is supplied to the liquid crystal display device from the outside and when the AC power is cut off.

FIG. 10 is a flowchart illustrating a control procedure of an OFF sequence executed by an interrupt program when the power is turned off.

FIG. 11 is a diagram showing a data configuration of an EEPROM for holding an adjustment level in the embodiment.

FIG. 12 is a flowchart illustrating a memory writing procedure according to the present embodiment.

FIG. 13 is a flowchart illustrating a “memory read” operation performed when the display device starts up.

FIG. 14 is a diagram showing another example of a data configuration of an EEPROM for holding an adjustment level.

FIG. 15 is a flowchart illustrating a procedure for executing writing to the EEPROM only when adjustment level data has changed during memory writing when power is turned off.

FIG. 16 is a diagram showing a data configuration of an EEPROM for holding an adjustment level in the second embodiment.

FIG. 17 is a flowchart illustrating a memory reading procedure according to the second embodiment.

FIG. 18 is a flowchart illustrating a memory writing procedure according to the second embodiment.

FIG. 19 is a flowchart illustrating another procedure of the memory writing process according to the second embodiment;

FIG. 20 is a diagram showing an example of a memory map of a storage medium storing a control program according to the present invention.

FIG. 21 is a diagram showing an example of a memory map of a storage medium storing a control program according to the present invention.

FIG. 22 is a block diagram illustrating an example of a general liquid crystal display device.

FIG. 23 is a diagram showing a connection between the MPU 1807 and the switch board 1813.

Claims (18)

[Claims] 1. A storage control device having a storage medium having a word having a predetermined number of bits as a rewritable unit, comprising a data structure including N words including a predetermined word having at least one inversion bit. Detecting means for detecting a storage position of the first data in the storage medium based on the predetermined word; and a new position which is shifted by at least one word from the storage position of the first data recognized by the recognition means. A first writing unit that writes a second data having the data configuration to the new storage position in the storage medium as a storage location; and, among words stored in the first data, the first writing unit A second writing unit for setting all bits of a word that is not updated by writing the second data to a non-inverted state. 2. The method according to claim 1, wherein the predetermined word is N in the data structure.
A detecting unit that reads data sequentially from a starting address in a predetermined area of the storage medium and detects a word including at least one inversion bit; 2. The storage control device according to claim 1, wherein an address of the first data is detected as a storage position of the first data. 3. The storage control device according to claim 1, wherein the predetermined word includes one odd parity bit for setting the number of inverted bits to an odd number. 4. The storage controller according to claim 1, wherein said predetermined word includes at least one bit which is always fixed in an inverted state. 5. The information processing apparatus according to claim 1, further comprising: reading means for reading the first data from the storage position detected by the searching means; wherein the second data writing means executes the first data writing means after execution of the reading means. 2. The storage control device according to claim 1, wherein the storage control is performed before. 6. A control device for comparing the first data with the second data, and when the first and second data are different, the control unit executes the first and second writing units. The storage control device according to claim 1. 7. A storage control device for performing storage control of a control range of a predetermined number of words in a storage medium in which a word having a predetermined number of bits is a rewritable unit, comprising: N words; Writing means for writing data having a data configuration including a predetermined word having an inverted bit into a predetermined storage location of the storage medium; counting means for counting the number of times of writing by the first writing means; When writing, if the number of times of writing counted by the counting means exceeds a predetermined value, updating means for updating the storage position to be written by the writing means to a position shifted by at least one word is provided. Storage controller. 8. A storage unit for holding a pointer indicating a storage position of a writing target by the writing unit at a predetermined address in the control range, and a case where the storage position of the writing target by the writing unit is updated by the updating unit. 8. The storage control device according to claim 7, further comprising a second updating unit that updates a storage position held by said holding unit. 9. The storage control device according to claim 8, wherein a read position of the data and a storage position of the data by the writing unit are determined by a pointer held by the holding unit. 10. The apparatus according to claim 7, wherein said counting means holds the count information indicating the number of times of writing at a storage location having a predetermined relationship with a storage location to be written by said writing means. Storage controller. 11. The storage control device according to claim 10, wherein the storage position of the count information in the counting unit is a position following a storage position of a writing target by the writing unit. 12. The apparatus according to claim 7, further comprising control means for executing writing by said writing means when new data to be written by said writing means is different from data previously stored. 3. The storage control device according to claim 1. 13. The storage control device according to claim 1, a display for performing a display based on a video signal, and a content of the first data read from a storage position detected by the detection unit. Setting means for setting the display on the basis of the following; changing means for changing the setting state of the display; and generating means for generating a current setting state of the display as the second data. Display device. 14. A storage control device according to claim 7, further comprising: a display for performing display based on a video signal; and reading data from a predetermined storage position that is a writing target position by said writing means. Setting means for setting the display based on the data; changing means for changing the setting state of the display; and generation for generating the current setting state of the display as data for writing by the writing means. And a display device. 15. A method for controlling a storage control device having a storage medium having a word having a predetermined number of bits as a rewritable unit, comprising N words including a predetermined word having at least one inversion bit. A detecting step of detecting a storage position of the first data having a data configuration in the storage medium based on the predetermined word; and a position shifted by at least one word from the storage position of the first data recognized in the recognition step. As a new storage location, a first writing step of writing the second data having the data configuration to the new storage location in the storage medium, and a first writing step of a word stored in the first data. A second writing step of setting all bits of a word not updated by the writing of the second data in a non-inverting state. 16. A storage control method for performing storage control of a control range of a predetermined number of words in a storage medium having a word composed of a predetermined number of bits as a rewritable unit, comprising: N words; A writing step of writing data having a data configuration including a predetermined word having an inversion bit into a predetermined storage location of the storage medium; a counting step of counting the number of times of writing in the first writing step; When writing, if the number of times of writing counted by the counting step exceeds a predetermined value, an updating step of updating a storage position to be written in the writing step by at least one word is provided. Memory control method. 17. A computer-readable memory for storing a program code for performing storage control of a storage medium in which a word having a predetermined number of bits is a rewritable unit, including a predetermined word having at least one inversion bit. A code of a detection step of detecting a storage position of the first data having a data configuration of N words in the storage medium based on the predetermined word, and a storage position of the first data recognized in the recognition step. A position shifted by at least one word is set as a new storage position, a code of a first writing step of writing the second data having the data configuration to the new storage position in the storage medium, and storage of the first data Setting all the bits of the word that is not updated by the writing of the second data in the first writing step in the non-inverted state, 2. A computer readable memory, comprising: a code of two writing steps. 18. A computer-readable memory for storing a program code for performing a storage control of a control range of a predetermined number of words in a storage medium having a word having a predetermined number of bits as a rewritable unit, comprising N words And a code of a writing step of writing data having a data configuration including a predetermined word having at least one inversion bit into a predetermined storage location of the storage medium, and a count for counting the number of times of writing in the first writing step When writing the data in the writing step and the data in the writing step, if the number of writes counted in the counting step exceeds a predetermined value, the storage location to be written in the writing step is updated to a position shifted by at least one word. A computer-readable memory comprising: