JPH1013253A - Convolutional interleaver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify the circuit constitution of a convolutional interleaver by using a dual-port RAM as a delay medium, when the convolutional interleaver must be set and changed. SOLUTION: At the reading side of a dual port RAM 4, the address signals applied to the address terminal, placed at the reading side of the RAM 4, are inputted to a subtracter 5 and an adder 6. These input results are inputted to a selector 7. The selector 7 selects the signal of the subtracter 5 or the adder 6 by the carry signal received from the subtracter 5 and outputs this selected signal to a latch 8. The latch 8 holds the address signals in synchronism with the input clocks. The RAM 4 is used as a delay medium and consists of a counter, a computing element, etc., with regard to the designation of the addresses. Thus, the circuit constitution of a convolutional interleaver can be simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a convolutional interleaver.
In particular, the present invention relates to an interleave method for preventing a decrease in the error correction capability of a Reed Solomon code corresponding to a continuously generated burst error in a digital modulator / demodulator used in satellite communication.

[0002]

2. Description of the Related Art Since an earth station of a digital satellite line receives a very weak signal, it is inevitable that an error occurs in a digital code due to noise or the like. Various error correction codes are considered as a method for correcting this error.
As a method to cope with burst errors, especially
Solomon codes are promising.

As shown in FIG. 4, a conventional convolutional interleaver includes an S / P converter 23 for converting input data of a data input terminal 21 into N-stage parallel data, and a parallel data of the converter 23. (N-1) shift registers 28, 29, 3
0, 31 and P / P for converting the N-stage parallel data delayed by the shift register into serial data.
An S converter 25 and the shift registers 28, 29, 3
And a frequency divider 24 that divides the frequency by N to supply clock signals to 0 and 31.

Here, an input clock signal from a clock input terminal 22 is applied to an S / P converter 23, a P / S converter 25, and a frequency divider 24, and is also output to a clock output terminal 27, where Used for signal processing. The shift register 28 is an M-stage shift register, the shift register 29 is a 2M-stage shift register, the shift register 30 is a 3M-stage shift register, and the shift register 31 is (N−1) ·.
It is composed of M stages of shift registers, each of which is shifted by one-Nth clock signal.

Conventionally, data is rearranged by such a configuration. The Reed-Solomon modem is added outside this convolutional interleaver, considering the transmission path as the center.

[0006]

As described above,
Conventional convolutional interleaver (Convol
(Utional Interleaver) used a number of shift registers to constitute the delay medium. Therefore, if the depth and the number of stages are set to be large in order to improve the performance of the interleaver, the number of shift registers to be used increases and the circuit scale becomes large, and the depth and the number of stages of the interleaver are fixed. When the change is made, the circuit configuration is changed in accordance with the change in the number of shift registers used. Therefore, a significant change operation is required, and the operation is not limited to a simple addition operation.

Further, in such a Reed-Solomon code, for example, it is possible to almost certainly correct the occurrence of a burst error within 10 bytes in one frame of 200 bytes. As for the burst error exceeding, the error correction capability was remarkably reduced.

[0008] Referring to JP-A-1-124163, which discloses an address control circuit used for data interleaving in a digital data recording / reproducing apparatus for recording / reproducing digital data on a magnetic recording medium or the like, the memory address is set higher and lower. By handling these two-dimensionally and combining those data with an adder (adder), various addressing can be supported. In addition, the system mode of the system mode by switching between those address data, addition data, and various signal processings can be handled. With a configuration in which all switching data is stored as a table in a common ROM, various interleaving methods and error correction methods are supported only by changing the table data in the ROM.

However, in such a configuration, although a single operation by an interrupt signal is shown, there is no mention of a continuous interleave operation.

Referring to Japanese Utility Model Laid-Open Publication No. 1-154562, an operation ROM (Read Only Memory) storing operation instructions for a plurality of addressing counters of a RAM (Random Address Memory) and a constant RO for setting constants are disclosed.
M, and sequentially reads out the operation instructions stored in the operation ROM, updates the address counter and sets constants according to the contents of the operation instructions, and obtains the specified address of the RAM, thereby shortening the operation cycle. Although high-speed processing is possible, such a configuration is
It is an interleaved system, not a convolutional interleaved system.

Therefore, an object of the present invention is to change and read out the memory arrangement without changing the circuit configuration,
It is an object of the present invention to provide a convolutional interleaver that performs burst error dispersion without failing to reduce the correction capability of the Reed-Solomon code and ensures error correction.

[0012]

In order to solve the above-mentioned problems, a convolutional interleaver according to the present invention comprises a counter for generating a write address by an input clock, input data being written in accordance with the write address, and a read address. , A subtractor that inputs and subtracts the read address, outputs a calculation result and a carry signal, and inputs and adds the read address, and outputs the calculation result. An adder, a selector for selecting and outputting one of the outputs of the subtractor and the adder based on a carry signal from the subtractor, and holding the output of the selector in synchronization with the input clock. And a latch for outputting to the dual port RAM.

Here, the subtractor and the adder perform an operation based on a constant determined by the number of stages and the depth which are the settings of the convolutional interleaver, and the convolutional interleaver has a depth of 12, It can be configured with 17 stages.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to the block diagram of FIG. 1 showing one embodiment of the present invention, the configuration of a convolutional interleaver of this embodiment is such that data is input and output according to an input address and an output address. A dual port ROM 4, a counter 3 for generating an input address based on a clock signal, a latch 8 for temporarily storing an output of the selector 7 and outputting the output to the RAM 4 as an output address and outputting to the subtracter 5 and the adder 6, And a selector 7 to which operation output signals 12 and 13 of the adder 5 and the adder 6 are input and which is switched to output either of them by a carry signal of the subtractor 5. Note that a clock signal is output from the clock output terminal 10 and used together with the data of the output terminal 9 in the subsequent processing.

In such a configuration, input data is input from the input terminal 1 and the input data is written to the dual port RAM 4. A clock signal synchronized with the input data is input from a clock input terminal 2, and the input clock generates an address signal by a counter 3 and is input to a write-side address terminal of the dual port RAM 4.

On the read side of the dual port RAM 4, the address signal currently supplied to the address terminal on the read side of the dual port RAM 4 is calculated by a constant determined by the number of stages and the depth set by the convolutional interleaver. The operation result is input to the subtracter 5 and the adder 6, and the operation result is input to the selector 7.

The selector 7 selects one of the subtractor 5 and the adder 6 based on the carry signal from the subtractor 5 and outputs the selected signal to the latch 8. The latch 8 outputs the address signal in synchronization with the input clock. Hold. The dual port RAM 4 outputs data corresponding to the address signal to the data output terminal 4.

Referring to the layout diagrams of FIGS. 2 and 3, which respectively show an example of an input data sequence and an output data sequence in the configuration of FIG. 1, an operation example of an interleaver having a depth of 3 and a number of stages of 3 is shown. The input data sequence in FIG. 2 is X (0), X (1), X (2), X (3),.
., X (26) in numerical order.

The output data sequence shown in FIG. 3 is a data sequence processed by the interleaver shown in FIG. 1, and the read order is changed, and Y (0), Y (19), Y (11), Y
(3), Y (22), Y (14),..., Y (8) are sequentially output. That is, even if a series of burst errors are included, the burst errors are dispersed and output, so that error correction can be performed reliably. Where X (0) and Y
(0),..., X (26) and Y (26) are common storage contents.

A practical interleaver has a depth of 12 and a number of stages of 17. The correction capability of the Reed-Solomon code at this time is limited by the number of bytes in one frame.
If there is error data exceeding the correction capability, the error data is output as it is. However, according to this embodiment, since burst errors are dispersed, burst error correction can be performed reliably.

According to this embodiment, a dual port ROM is provided as a delay medium,
Concerning addressing, it consists of only a simple adder,
Regarding the operation of the read address signal, if there is a burst error of continuous data due to two arithmetic units, a selector and a latch, this burst error is dispersed so that error correction can be performed reliably.

[0022]

As described above, according to the convolutional interleaver of the present invention, the convolutional interleaver is constituted by a dual-port RAM, a counter, two arithmetic units, a selector and a latch. When a change is needed, the dual port RAM is used as a delay medium, so that it can be dealt with only by changing the setting of the arithmetic unit.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating one embodiment of a convolutional interleaver according to the present invention.

FIG. 2 is a layout diagram showing an input data string.

FIG. 3 is a layout diagram showing an output data string according to one embodiment.

FIG. 4 is a block diagram illustrating an example of a conventional convolutional interleaver.

[Description of Signs] 1 input data terminal 2 input clock terminal 3 counter 4 dual port RAM 5 subtractor 6 adder 7 selector 8 latch 9 output data terminal 10 output clock terminal 23 serial / parallel converter 24 clock divider 25 parallel / Serial converter 28,29,30,31 Delay shift register

Claims (3)

[Claims] A counter for generating a write address according to an input clock; and input data written according to the write address;
A dual-port RAM from which output data is read in accordance with a read address; a subtractor that inputs and subtracts the read address, and outputs a calculation result and a carry signal; And a selector for selecting and outputting one of the outputs of the subtractor and the adder based on a carry signal from the subtractor, and holding the output of the selector in synchronization with the input clock. And a latch for outputting to the dual port RAM. 2. The convolutional interleaver according to claim 1, wherein the subtractor and the adder perform an operation using a constant determined by the number of stages and the depth, which are the settings of the convolutional interleaver. 3. The convolutional interleaver according to claim 1, wherein said convolutional interleaver has a depth of 12 and a number of stages of 17.