JPH10129039A - Pixel modulating apparatus and image forming apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a pixel modulating apparatus having inexpensive and stable pixel position control function and to drastically increase the printing speed of a highly detailed image in an image forming apparatus such as LBP or a digital copier. SOLUTION: In a pixel modulating apparatus outputting a pixel modulating signal necessary for controlling the position of a pixel on the basis of pixel data DV of a plurality of bits inputted from the outside and the pixel clock signal SCK synchronous to a predetermined horizontal synchronizing signal HD, a synchronizing signal generator 2 generates the pixel clock signal SCK synchronizing to the horizontal synchronizing signal HD. A pixel modulating processor 1 has a plurality of delay circuits and performs division control so as to divide the pixel cycle of the pixel clock signal SCK generated from the synchronizing signal generator 2 into four divided pixel clock signals and outputs a pixel modulating signal on the basis of the clock signals so as to delay the same.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LBP (laser beam printer) capable of printing a halftone image at high speed,
The present invention relates to an image forming apparatus such as a digital copying machine and a pixel modulation device used for the same.

[0002]

2. Description of the Related Art As a method of expressing a halftone image in an image forming apparatus such as an LBP or a digital copying machine, a pixel modulation circuit (pixel modulation device) is used to express one pixel in accordance with density data of a pixel of about 8 bits. Alternatively, there is a method in which pulse width modulation (PWM) is performed in units of n pixels to control the laser irradiation time.

FIG. 13 shows an LBP capable of printing a halftone image.
1 is a diagram illustrating a schematic configuration of an image forming apparatus such as a digital copying machine.

As shown in FIG. 13, an image forming apparatus includes a polygon mirror 23, an f-θ lens 24, a BD mirror 2
5, light receiving diode 26, photosensitive drum 27, semiconductor laser 29, photodiode 30, light quantity control unit 31, laser driver 32, pixel modulation circuit 33, blanking circuit 34, horizontal synchronization signal generation circuit 35, and pixel modulation data generation source 36 And is schematically configured.

Here, the photodiode 30 monitors the laser light output from the semiconductor laser 29 as a laser light source.

The light quantity control unit 31 controls an application current to the semiconductor laser 29 based on the monitored light quantity,
The control is performed so that the output from the photodiode 30 becomes a predetermined value.

Semiconductor laser 29 and photodiode 30
Are generally combined and configured as a laser chip 28.

The polygon mirror 23 has a semiconductor laser 29
The laser beam is irradiated on the photosensitive drum 27 by scanning the photosensitive drum 27 while rotating in the direction of the arrow in FIG. The laser-scanned image formed on the photosensitive drum 27 is transferred to a printing paper or the like.

The f-θ lens 24 focuses the polarized laser beam on the photosensitive drum 27 at a constant linear velocity.

The BD mirror 25 has a mechanically fixed positional relationship with the photosensitive drum 27. The reflected laser beam is input to the light receiving diode 26 and used to detect the information writing start position on the photosensitive drum 27. You.

The output of the light receiving diode 26 is input to a horizontal synchronizing signal generating circuit 35 to generate a horizontal synchronizing signal HD. The generated HD signal is supplied to the pixel modulation circuit 33 and the pixel modulation data source 36.

The blanking circuit 34 outputs a horizontal synchronizing signal H
The blanking signal HBL for turning on the semiconductor laser at the timing when the BD mirror 25 should detect the laser beam based on D is generated and supplied to the pixel modulation circuit 33.

The pixel modulation data DV (hereinafter, simply referred to as “pixel data”) generated from the pixel modulation data source 36 is generally 8-bit data, and is supplied to the pixel modulation circuit 33. The output signal of the pixel modulation circuit 33 is a laser driver 32 for controlling the drive of the semiconductor laser 29.
Supplied to

The pixel modulation circuit 33 generates a pixel clock signal SCK in synchronization with the horizontal synchronizing signal HD, and corrects the time base of the pixel modulation data DV based on the signal. Further, the pixel modulation circuit 33 generates a high-speed PWM signal based on the pixel clock signal SCK and the pixel modulation data DV,
It is possible to print a halftone image by controlling the amount of laser light in multiple stages. When the blanking signal HBL is generated, the semiconductor laser 29 is forcibly turned on and the BD
A horizontal synchronizing signal HD can be generated by always supplying a laser beam to the mirror 25.

As described above, the image forming apparatus such as an LBP and a digital copying machine capable of printing a halftone image described with reference to FIG. 13 is very demanded for color printing and a high printing speed.

For example, when performing color printing, four-color printing of Y (yellow), Cy (cyan), Mg (magenta), and Bk (black) is required. However, FIG.
In a configuration having only one photosensitive drum 27, printing one color image requires four times as long as monochrome printing. As an effective method of improving the speed of color printing to improve this, there are two methods, for example, a four-drum method and a two-beam method.

(I) Four-drum system In the case of the four-drum system, high-speed color printing can be performed on the printing paper 41 by using four photosensitive drums 37 to 40 as shown in FIG. Each of the photosensitive drums 37 to 40 has the same configuration as that of the photosensitive drum 27 shown in FIG. 13, and is expected to have a printing speed four times higher than that of the one-drum system.

(II) Two-beam system In the case of the two-beam system, a laser chip 28 having two semiconductor lasers 29 is used. In this case, the light spot of the laser light irradiated by each laser is as shown in FIG.

Normally, the positional relationship between the light spots SP1 and SP2 of the laser beam irradiated by each laser is larger than one pixel interval due to the configuration of the laser chip 28. Therefore, the laser chips 28 are arranged obliquely so that the light spot interval in the paper feed direction is one pixel interval as shown in FIG. Light spot SP
Laser chip 28 for irradiating SP1 and SP2 is shown in FIG.
, The pixel modulation data source 36
And the laser driver 32, so that the printing speed can be doubled without increasing the pixel clock frequency.

By the way, there are points to keep in mind in the above two methods for speeding up color printing. First, in the four-drum system, the pixel positions of the four colors formed on the photosensitive drums 37 to 40 are shifted due to variations in the positional accuracy of the BD mirrors arranged in pairs with the photosensitive drums 37 to 40 and drift due to the environment. Unacceptable color moiré (beat) occurs during printing.

On the other hand, even in the case of the two-beam method, an unacceptable pixel position shift occurs between the two laser scans due to variations in the inclined arrangement of the laser chip 28 and drift due to the environment (for example, the light spot S in FIG. 15).
A shift like a light spot with respect to P1). Therefore, pixel position control for correcting the pixel position deviation is required. It is said that this control error must be less than 1/4 of one pixel.

FIG. 16 shows a configuration example of the pixel modulation circuit 33 having such a pixel position control function.

The pixel modulation circuit 33 includes a crystal oscillation circuit (X
O) 42, a synchronizing signal generator 43 connected to the crystal oscillation circuit 42, a distributed constant delay line 44 connected to the synchronizing signal generator 43, and a high-speed connected to the distributed constant delay line 44 via the switch S8. A waveform shaping amplifier 45, a high-speed comparator CMP connected to the high-speed waveform shaping amplifier (AMP) 45 via a variable resistor VR1 and a capacitor C8.
6, comprising a high-speed D / A converter (DAC) 46 and a time-base correction circuit (FIFO) 47 connected in parallel between the switch S8 and the high-speed comparator CMP6, and an OR circuit 5 connected to the comparator CMP6. Is done.

In the pixel modulation circuit 33, the horizontal synchronizing signal HD and the reference clock of the output of the crystal oscillation circuit 42 are input to the synchronizing signal generator 43, and the synchronizing signal generator 43 outputs a pixel clock signal SCK synchronized with the horizontal synchronizing signal HD.

The pixel clock signal SCK is input to the distributed constant delay line 44, and a plurality of delay tap outputs are respectively input to the switch S8, and the delay tap output is selected so as to be at a desired pixel position by the pixel position setting signal. . The output of the switch S8 is input to the high-speed wave shaping amplifier 45, and a triangular wave signal is generated by the variable resistor VR1 and the capacitor C7, and is set to a desired peak value of the triangular wave signal by the variable resistor VR1. Further, a desired offset value of the triangular wave signal is set by the resistor R12 and the variable resistor VR2 via the large-capacity capacitor C8, and is input to the high-speed comparator CMP6.

On the other hand, the output of the switch S8 is the pixel data D
The time base correction circuit 47 to which V is input and the high-speed D
/ A converter 46.

The output of the high-speed D / A converter 46 is input to a high-speed comparator CMP6.
A high-speed PWM pixel modulation signal controlled by V is output and input to the OR circuit 5. Further, a blanking signal HBL is input to the OR circuit 5, and the semiconductor laser 29 is forcibly turned on fully during the blanking period. The output signal of the OR circuit 5 is input to the laser driver 32.

[0028]

However, the conventional pixel modulation circuit as shown in FIG. 16 has the following problems.

First, it is impossible to stably set the total delay time of the output of the delay tap used in the distributed constant delay line 44 to the pixel cycle because of variations and environmental fluctuations. Therefore, when the total delay time exceeds the pixel period, the pixel position correction control becomes very difficult.

Further, the distributed constant delay line 44 is expensive, and becomes more conspicuous as the frequency of the pixel clock signal becomes higher. Furthermore, if the total delay time of the delay tap output is increased, the distributed constant delay line 44 not only becomes more expensive, but also promotes the variation and fluctuation of the pixels and impairs the stability.

The present invention has been made in view of the above circumstances, and has as its object to provide a pixel modulation device and an image forming apparatus capable of performing stable pixel position correction control at low cost. I do.

[0032]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides an image forming apparatus based on a plurality of bits of externally input pixel data and a pixel clock signal synchronized with a predetermined horizontal synchronizing signal. A synchronizing signal generating means for generating a pixel clock signal synchronized with the horizontal synchronizing signal; and a pixel of the pixel clock signal generated by the synchronizing signal generating means. And a plurality of delay circuits that divide and control the period into at least two divisions and delay-output the pixel modulation signal based on the divided pixel clock signal.

Further, according to the present invention, a pixel modulation signal necessary for pixel position control is output based on the input multi-bit pixel data and a pixel clock signal synchronized with a predetermined horizontal synchronizing signal. In an image forming apparatus for forming an image on a photosensitive drum based on a modulation signal, a synchronizing signal generating means for generating a pixel clock signal synchronized with the horizontal synchronizing signal, and a pixel of the pixel clock signal generated by the synchronizing signal generating means A pixel modulation circuit including a plurality of delay circuits for controlling a period to be divided into at least two divisions and delaying and outputting the pixel modulation signal based on the divided pixel clock signal; and a pixel delayed and output by the pixel modulation circuit. At least one half which is driven and controlled based on a modulation signal and performs laser scanning output on the photosensitive drum according to the pixel data. And having a body laser element.

[0034]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows an example of a pixel modulation circuit (pixel modulation device) having a pixel position control function according to an embodiment of the present invention. This pixel modulation circuit is applied to, for example, the image forming apparatus shown in FIG.

In the pixel modulation circuit shown in FIG. 1, the horizontal synchronizing signal HD is input to one of the input terminals of the OR circuit OR1.

The output terminal of the OR circuit OR1 is connected to the pixel modulation processor 1 and the synchronization signal generator 2, and converts the input horizontal synchronization signal HD into the horizontal synchronization signal HD.
1 is output to the pixel modulation processor 1 and the synchronization signal generator 2.

The output terminal of the OR circuit OR2 is connected to the pixel modulation processor 1, and the input pixel modulation mode signal F
1 is output to the pixel modulation processor 1 as an F11 signal.

The synchronizing signal generator 2 is connected to the crystal oscillation circuit 3 and receives a reference clock signal generated by the crystal oscillation circuit 3 and having a clock cycle To. Further, the synchronization signal generator 2 is connected to the pixel modulation processor 1, generates a pixel clock signal SCK having a period To synchronized with the falling edge of the HD signal, and outputs the generated clock signal SCK to the pixel modulation processor 1. Further, the synchronization signal generator 2
Outputs a pixel clock signal SCK for driving a FIFO (not shown) for time base correction of the pixel data DV.

The pixel position setting circuit 4 receives the pixel position setting data P1 and P2, and outputs the data to the DFF circuit DF.
The output signal from F1 is input. The NQ output signal from the DFF circuit DFF4 is input to the pixel position setting circuit 4. Further, upper four bits (D8 to D5) of the pixel data DV are input to the pixel position setting circuit 4.

The pixel modulation processor 1 integrates the emission control function of a semiconductor laser such as high-speed PWM, which is the main function of the pixel modulation circuit, into a one-chip LSI.
The horizontal synchronization signal HD1 output from the OR circuit OR1 is input to the pixel modulation processor 1. Further, the lower 4 bits (D1 to D4) of the pixel data DV are input to the pixel modulation processor 1 and connected to the pixel position setting circuit 4, so that the upper 4 bits (D8) of the pixel data DV are output.
To D5) are input via the pixel position setting circuit 4.
Further, the pixel modulation processor 1 receives an OFF control signal F2 for shutting off the pixel modulation signal and turning off the light emission of the semiconductor laser, and an ON control signal F3 for similarly turning on the full light. The pixel modulation processor 1 has an OR circuit O
The output terminal of R2 is connected, and the F11 signal is input.

The counter 5 is connected to the pixel modulation processor 1 and the DFF circuit 2.
Is output as a clock signal to the R terminal of the DFF circuit 2.

The Q output terminal of the DFF circuit DFF2 is OR
It is connected to one of the input terminals of the circuit OR1 and the NAND circuit 1, and to the reset R terminal of the DFF circuit DFF4.

The clock terminal of the DFF circuit DFF4 has
An HD signal is input. Also, the N of the DFF circuit DFF4
Q output terminal is the inverted reset NR terminal of counter 5, O
The input terminal of the R circuit OR2 and the pixel position setting circuit 4 are connected.

The output terminal of NAND circuit NAND1 is D
The output signal is connected to the clock terminal of the FF circuit DFF3 and the delay circuit 6, and the output signal is fed back via the delay circuit 6 and is input to the clock of the DFF circuit DFF3.

An HD signal is input to the reset R terminal of the DFF circuit DFF3. Also, the Q of the DFF circuit DFF3
The output terminal is connected to the input terminal of the OR circuit OR3.

The HD signal is input to the OR circuit OR3, and the Q output signal of the DFF circuit DFF3 is input to the OR circuit OR3. The OR circuit OR3 outputs the output result to the reset R terminal of the DFF circuit DFF2.

The pixel clock signal SCK is input to the clock terminal of the DFF circuit DFF1. An HD signal is input to a reset R terminal of the DFF circuit DFF1,
The inverted HD signal is input to the data input terminal D via the inverter INV1. Further, the Q output terminal of the DFF circuit DFF1 is connected to the pixel position setting circuit 4 to output a Q output signal.

Next, the details of the pixel modulation processor 1 will be described with reference to FIGS. 2 and 3 are diagrams showing a detailed configuration of the pixel modulation processor 1. FIG.

The pixel modulation processor 1 includes a triangular wave signal generation unit 7, a D / A conversion unit 8, a serial modulation unit 9, an output control unit 10, a divide-by-2 circuit 11, and variable pulse delay circuits 12, 1.
3, 14, EXOR circuits XR1 and XR2 and a comparator CMP4.

The pixel clock signal SCK input to the pixel modulation processor 1 is input to a frequency divider 11, a D / A converter 8, a serial modulator 9, and an output controller 10. The pixel clock signal SCK input to the pixel modulation processor 1 is obtained by finally controlling the pixel position of the pixel clock signal SCK having the period To, and is a signal as shown in FIG. The pixel clock signal SCK is input to the frequency divider 11 and divided by two (see FIG. 8).
b) The clock duty information is deleted.

The output signal from the frequency divider 11 is input to a variable pulse delay circuit 12 whose operation is controlled to a pulse delay time of 1/4 To, which will be described later, and then a variable pulse delay circuit having exactly the same configuration. The signals are input to the circuits 13 and 14. Therefore, each 2/4 delayed by 1/4 To is added.
A divided clock signal is output. FIG. 8C shows the output of the variable pulse delay circuit 13.

The output signals of the frequency divider 11 and the variable pulse delay circuit 13 are input to an EXOR circuit XR1.

In the EXOR circuit XR1, when the variable pulse delay circuits 12, 13, and 14 are controlled as described above, the differential pixel whose duty is parallel and has no relation to the clock duty fluctuation of the pixel clock signal SCK at all. A new clock signal is generated and output to the triangular wave signal generator 7.

The triangular wave signal generator 7 includes resistors R1 to R6,
Transistors Q1-Q3, Q5-Q11, capacitor C
1, comparators CMP1 to CMP3, charge pump circuits 15 and 17, offset value control signal generation circuit (△ D
U circuit 16 and a peak value control signal generation circuit (△ PP circuit) 18. This triangular wave signal generator 7
Q11 = Q9 = Q10, Q1 = Q2 = Q3, Q5 = Q
6, Q7 = Q8,2R6 = R4 = R5, R1 = R2 = R
3 (where the equal sign for the transistor indicates that the emitter sizes are equal).

The transistor Q5 / B in the triangular wave signal generator 7 (/ B indicates a base. The same applies hereinafter).
Is supplied with a reference voltage Vr3 of a desired triangular wave signal. It is desirable that the reference voltage Vr3 be the center voltage of the desired triangular wave signal as shown in FIG.

The transistor Q11 in the triangular-wave signal generator 7 generates a triangular-wave signal charge control current 2I1.

Transistors Q1, Q2 and Q5, Q6
A discharge current control circuit composed of Q9, Q10 and resistors R4, R5, R1, R2 is a HF circuit generally used in LSI.
Even if a lateral PNP transistor having a low E is used, a discharge control current I1 that is 1/2 of the charge control current 2I1 can be generated accurately.

The transistors Q7 / B and Q8 / B have
The positive and negative phases of the differential pixel clock signal from the EXOR circuit XR1 are input. For this reason, + I1 is applied to the transistor Q8 / C (/ C indicates a collector, the same applies hereinafter) according to the level change of the differential pixel clock signal.
(During charging) and -I1 (during discharging)
Supplied from 1.

The comparator CMP1 is connected to the capacitor C1
6A, the rising and falling slopes have a good linearity and a well-balanced triangular wave signal is generated as shown in FIG.

Negative input of comparator CMP2 and CPM
The triangular wave signal output from the comparator CMP1 is input to the positive input terminal 3. In addition, the comparator CM
The positive input terminal of P2 and the negative input terminal of CPM3 respectively have a reference voltage Vr1 shown in FIG. 7A for defining the upper peak level of the desired triangular wave signal and a reference voltage V defining the lower peak level shown in FIG.
r2 has been input.

The comparator CMP2 uses the linearity of the slope of the generated triangular wave signal shown in FIG. 7B to output a pulse signal P10 having detected the upper and lower apex levels to the charge pump circuits 15, 17.

The comparator CMP3 uses the linearity of the slope of the generated triangular wave signal shown in FIG. 7C to output a pulse signal P90 having detected the upper and lower apex levels to the charge pump circuit 17.

The charge pump circuit 15 (CP 1) is connected to the offset value control circuit 16 and inputs an output signal to the offset value control circuit 16. An offset control signal △ DU output from the offset value control circuit 16 is input to the variable pulse delay circuits 12, 13, and 14. The offset control signal △ DU controls the amount of delay of the variable pulse delay circuits 12, 13, and 14, which will be described later in detail with reference to FIG.

FIG. 4 is a diagram showing a detailed configuration of the charge pump circuit 15.

The detailed configuration of the charge pump circuit 15 is shown in FIG.
The charge pump circuit 15 includes a capacitor C3 and a resistor R connected to the capacitor C3.
10 and a capacitor C4 connected to the resistor R10.
And a buffer BUF2 and a switch S5 connected between the capacitor C3 and the resistor R10. In the charge pump circuit 15, the comparator CMP2
An equilibrium state is established only when the negative pulse width of the output pulse signal P10 is 10%.

The charge pump circuit 17 (CP 2) is connected to the peak value control circuit 18 so as to input an output signal to the peak value control circuit 18. The peak value control signal $ PP output from the peak value control circuit 18 is input to the transistors Q9 / B, Q10 / B, and Q11 / B.

FIG. 5 is a diagram showing a detailed configuration of the charge pump circuit 17.

The charge pump circuit 17 includes a capacitor C
5, a resistor R11 connected to the capacitor C5,
A capacitor C6 connected to the resistor R11 and a buffer BUF connected between the capacitor C5 and the resistor R11.
2. It is configured to include switches S6 and S7. In the charge pump circuit 17, the control terminals of the switches S6 and S7 have vertex detection pulse signals P10 and P90 respectively.
Is supplied, thereby controlling the supply of the constant current I6. The other ends of the switches S6 and S7 have a constant current (1.
8) I6, capacitor C5 and resistor R11 for setting the loop conversion gain are connected. The resistance R11
Is a large capacity capacitor C externally via an IC lead pin.
6 decoupled.

Assuming that the reference voltages Vr1 and Vr2 are set as shown in FIG. 7A, each of which is shifted by 10% of the desired peak level from the upper and lower apex levels of the desired triangular wave signal. Considering that the slope linearity is good, the upper and lower vertex detection pulse signals P10, P9
The total value of the pulse width of 0 is 0.2 of the pixel clock period To.
Only at the time of, the charge pump circuit 17 is balanced. In other words, if the peak value control circuit 18 is configured so that the peak value control current I1 is reduced when the peak level of the generated triangular wave signal is higher than the desired value, the charge pump circuit 17 only operates when the peak level reaches the desired peak level. Becomes stable.

FIG. 6 shows the variable pulse delay circuits 12, 13,
FIG. 14 is a diagram showing a detailed configuration of the fourteenth embodiment.

The variable pulse delay circuits 12, 13, and 14
As shown in FIG. 6, the resistors R7 to R9 and the transistor Q
12 to Q22 and a capacitor C2. The relationship between the size and resistance value of each transistor in FIG.
Q16 = Q17, Q14 = Q15, Q12 = Q13, Q
18 = Q19, Q21 = Q22, R7 = R8, and the pulse delay amount Td is approximately indicated by the following equation.

Td = 2 · C2 · Vo / I3 where Vo = R7 · I2, and I3 is the signal △
This is the current controlled by the DU.

Now, as shown in FIG.
When d is smaller (larger) than 1/4 To (), the generated triangular wave signal falls (rises), so that the pulse width of the pulse signal P10 becomes smaller (larger) and the output of the charge pump 15 also falls (rises). At this time, if the offset value control circuit 16 is configured so that the offset control signal △ DU becomes smaller (larger), considering that the above-described peak value control loop controls the desired peak value, FIG. The desired triangular wave signal shown can be uniquely generated.
Also, the charge / discharge current balance for generating the triangular wave can be extremely improved by the LSI technology, so that the delay amount Td can be accurately controlled to ４Td.

The positive input terminal of the comparator CMP4
The desired triangular wave signal output from the comparator CMP1 is input. An analog pixel data signal of the D / A converter 8 driven by 8-bit pixel data DV is input to a negative input terminal of the comparator CMP4.

The D / A converter 8 includes a resistor array 19, a control current source array 20, a latch array 21, and a buffer BUF.
1, a resistor Rx, a current source Ix, and a comparator CMP5. The pixel data DV is supplied to the D / A converter 8
, The quantized current io passing through the latch array 21
The control current source switch array 20 is controlled to quantize the resistor r.
The current is supplied to the resistor array 19 of FIG. Resistor array 19
7, a reference voltage Vmin correlated with the reference voltages Vr1 and Vr2 for generating the triangular wave signal is input.
As shown in (a), when the pixel data DV changes from 00H to FFH, a voltage correlated with the triangular wave signal is output linearly from Vmin to Vmax.

At this time, it is assumed that Vx = Vmin-Vmax = 255 · ro · io.

Therefore, as shown in FIG. 7D, a PWM signal whose pulse width increases linearly with an increase in the pixel data DV is output as a pixel modulation signal for a halftone image to the output of the comparator CMP4. Is input to the switch S4.

Similar to the voltage Vmin, the reference voltage Vmax correlated with the triangular wave signal is input to the comparator CMP5, controls the current source Ix correlated with the reference control current io, and is connected to the voltage Vmin correlated with the quantization resistor ro. The current is supplied to the resistor Rx, and the voltage is supplied to the comparator CMP.
5 and is controlled to the voltage Vmax.

At this time, Vmin-Ix.Rx = Vmax, and if Vx = Ix.Rx, the pixel data DV = FFH regardless of the voltage Vmin, the D / A converter 8
Can be set to the voltage Vmax. Therefore, the minimum pulse width and the maximum pulse width can be set independently by the voltages Vmin and Vmax.

The pixel modulation signal circuit 9 is for a high-definition character image, and includes a latch array 22 and switches S1 to S3.
Is configured.

Latch array 22 of pixel modulation signal circuit 9
Are driven based on the pixel clock signal SCK, and the upper 4 bits (D8 to D5) of the pixel data DV
Is entered.

The switches S1 and S2 are controlled by the duty-reproduced pixel clock shown in FIG. 7D. Pixel data D8 and D5 are input to the switch S1, and D7 and D6 are input to the switch S2. Is entered.

The switch S3 is controlled by an EXOR circuit XR2 output signal that generates a clock signal delayed by 1/4 To with respect to the pixel clock of FIG.
Output signals from the switches S1 and S2 are input.

With the above configuration, the output of the switch S3 outputs the pixel data D8 to D
5 can be converted to parallel-serial at high speed. This means that the same pixel clock signal SCK enables four times higher definition, and a pixel modulation signal particularly suitable for a character image signal can be provided.

The output control unit 10 includes a DFF circuit 5, a DFF
The circuit includes a circuit 6, an AND circuit 1, an OR circuit 4, and a switch S4.

The switch S4 of the output control unit 10 is a DFF
It is controlled by the pixel modulation mode selection signal F11 that has passed through the circuit 5. Further, the output signal of the pixel modulation signal circuit 9 and the output signal of the comparator CMP4 are input to the switch S4. The output signal of the switch S4 is input to the input terminal of the AND circuit 1.

The output signal of the switch S 4 is input to one of the input terminals of the AND circuit 1, and the OFF control signal F 2 passed through the DFF circuit 6 is input to the other input terminal. Thereby, the pixel modulation signal can be forcibly cut off. The output signal of the AND circuit 1 is input to the OR circuit 4.

The horizontal synchronizing signal HD1 is input to the reset terminal R of the DFF circuit 6 and reset.

One of the input terminals of the OR circuit 4 is AND
An output signal of the circuit 1 is input, and an ON control signal F3 is input to another input terminal. OR circuit 4
Outputs a pixel modulation signal. Here, the ON control signal F
When the blanking signal HBL is input as 3, the semiconductor laser can be fully lit during the blanking period, and the horizontal synchronizing signal HD can be generated.

Next, the operation of pixel position control in the pixel modulation circuit of FIG. 1 will be described with reference to time charts of FIGS.

In the pixel modulation circuit according to the present embodiment, the first
To 4th pixel position setting can be performed. 9 to 1
2 is a time chart for explaining the first to fourth pixel position setting operations.

In these time charts,
(A) is the HD1 signal, (b) is the NQ output signal of the DFF circuit 4, (c) is the pixel clock signal SCK output from the synchronization signal generator 2, and (d) is the pixel data input to the pixel modulation processor 1. DV and (e) indicate pixel modulation signals output from the pixel modulation processor 1, respectively. These are the same for the first to fourth pixel position settings.

As shown in FIG. 9, since the HD signal is at the H level before time t1, the NQ output signal of the DFF circuit 4 is at the H level. The upper four bits D8 to D5 of the input pixel data DV correspond to the pixel position setting data P as shown in the table below.
1, P2, and converts the pixel data DV. Note that the "X" mark in the table indicates that it has nothing to do with the set value.

[0095]

[Table 1] At time t2 when the first pixel clock signal SCK is generated from time t1, the Q output of the DFF circuit 1 is
The level changes from L to H level. Before this timing and when P2 = 1, if the output D8 of the pixel position setting circuit 4 is set to L level, the pixel data is set as shown by the DV item in the above table. Are also captured in the first pixel clock cycle. The time (t2-t1) is determined by the synchronization signal generator 2 used.

(I) First Position Setting State As shown in FIG. 9B, at time t2, the output signal of the DFF circuit 4 is at the H level, so that the signal F11 goes to the H level. Therefore, the pixel modulation processor 1 has the input pixel data D
A signal is output in which the upper 4 bits (D8 to D5) of V are serialized by dividing the pixel clock cycle into four.

Therefore, a clock signal as shown in FIG. 9E is output from the pixel modulation processor 1 after a delay (t3-t2) due to the circuit operation.

At this time, the counter 5 is in the counter state, and changes the count output from L to H at time t4, for example, at the fourth rising edge.

At this time, the Q output of the DFF circuit 2 becomes L →
The level of the HD1 signal changes to H level as shown in FIG.
Level and the DFF as shown in FIG.
The NQ output of the circuit 4 is changed from H level to L level.

At this time, the output of the NAND circuit 1 immediately changes from H level to L level.
At time t5 when the feedback input of the ND circuit 1 becomes smaller than the threshold level, the output of the NAND circuit 1 is returned from the L level to the H level again. For this reason, at time t5, the DFF circuit 3 goes high and the Q output of the DFF circuit 2 goes from high to low, so that the HD1 signal in FIG.
It changes to L level.

From time t4 to time t5, the synchronizing signal generator 2 performs a reset operation as shown in FIG. 9 (c), resetting the pixel clock generation, and the pixel modulation processor 1 as shown in FIG. 9 (e). Reset operation is performed.

After time t4, the counter 5 stops operating until the next rising edge of the HD signal arrives, so that no pulse is generated from time t4 to t5.

At the falling edge of the HD1 signal at time t5, the synchronization signal generator 2 generates a newly synchronized pixel clock signal SCK after time t6.

The time (t6−t5) is equal to the time (t2−t5).
1) and is determined by the synchronization signal generator 2 used. After time t4, since the NQ output signal of the DFF circuit 4 is at the L level, the modulation mode control signal F1 is valid, so that the pixel modulation processor 1 starts predetermined pixel modulation for the pixel clock signal SCK starting from time t6. .
At this time, no additional synchronous reset pulse as generated between the times t4 and t5 is generated.

The time (t6−t1) is expressed as (t6−t1) = 2 · (t2−t1) · nTo · (t5
−t4) becomes a stable time. Here, n is the count value of the counter 5 and this value is not limited. Therefore, the pixel modulation also operates normally in synchronization with the horizontal synchronization signal HD.
In addition, the time (t5 to t4) may be set to a minute pulse width enough to guarantee the synchronous reset operation of the synchronous signal generator 2. For this reason, the delay circuit 6 can be practically deleted by utilizing an IC pin input / output delay.

(II) Second Position Setting State In this case, the pixel data D
The upper 4 bits of V are set to 6h, and the pixel modulation processor 1 responds to the pixel clock signal SCK at time t2.
Generates a clock signal delayed by 1/4 To as compared with the first pixel position setting state starting from time (t3 + 1 / 4To) as shown in FIG. 10 (e), and subsequent operation timings t4 to t6 are also shown in FIG. 1/4 To delay.
Therefore, in this setting state, it is possible to stably generate a pixel modulation signal delayed by 1/4 To as compared to the first pixel position setting state.

(III) Third Position Setting State (Operation of Third Position Setting State) In this case, the upper 4 bits of the pixel data DV are set to 3 by the pixel position setting circuit 4.
h, the pixel clock signal SC at time t2
11E, the pixel modulation processor 1 generates a clock signal delayed by To as compared with the first pixel position setting state starting from time (t3 + ／ To) as shown in FIG. t4 to t6 are also delayed by 1/2 To as shown in the figure. Therefore, in this setting state, it is possible to stably generate a pixel modulation signal delayed by 1/2 To as compared with the first pixel position setting state.

(IV) Fourth Position Setting State In this case, the pixel data D
The upper 4 bits of V are set to 1h only for the pixel clock signal SCK at time t2 as shown in FIG. 12D, and thereafter are set to 9h. With respect to the pixel clock signal SCK at time t2, the pixel modulation processor 1 delays the clock signal delayed by 3/4 To compared to the first pixel position setting state starting from time (t3 + 3 / 4To) as shown in FIG. Occurs, the subsequent operation timings t4 to t6
Is also delayed by 3/4 To as shown in FIG. Therefore, in this setting state, 3 / compared to the first pixel position setting state.
A pixel modulation signal delayed by 4 To can be generated stably.

As described above, according to the present embodiment, the pixel modulation circuit shown in FIG. 1 can stably generate a pixel modulation signal whose pixel position is controlled to 1/4 To accuracy.

Further, the position control accuracy can be further improved by increasing the number of variable pulse delay circuit groups in the pixel modulation processor 1. Although no pixel modulation signal output is obtained in the period (t5-t1), the count value n of the counter 5 is a main factor in this period, and this period is a very short time, for example, as shown in FIG. There is no problem in the image forming apparatus.

Further, since the logic circuit added to the pixel modulation circuit of FIG. 1 is very small, the present invention can be implemented at low cost.

[0112]

As described above, according to the present invention, it is possible to realize a pixel modulator having a stable pixel position control function at low cost, so that a high-definition image in an image forming apparatus such as an LBP and a digital copying machine can be realized. Can dramatically increase the speed of printing.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a configuration of a pixel modulation circuit embodying the present invention.

FIG. 2 is a configuration diagram showing a detailed configuration of a pixel modulation processor 1;

FIG. 3 is a configuration diagram illustrating a detailed configuration of a pixel modulation processor 1;

FIG. 4 is a configuration diagram showing a detailed configuration of a charge pump circuit 15;

FIG. 5 is a configuration diagram showing a detailed configuration of a charge pump circuit 17;

FIG. 6 is a configuration diagram showing a detailed configuration of a variable pulse delay circuit.

FIG. 7 is a first time chart showing a signal output operation in the pixel modulation processor 1.

FIG. 8 is a second time chart showing a signal output operation in the pixel modulation processor 1.

FIG. 9 is a time chart illustrating the operation of the pixel modulation circuit according to the present invention.

FIG. 10 is a time chart illustrating the operation of the pixel modulation circuit according to the present invention.

FIG. 11 is a time chart illustrating the operation of the pixel modulation circuit according to the present invention.

FIG. 12 is a time chart illustrating the operation of the pixel modulation circuit according to the present invention.

FIG. 13 is a diagram showing a schematic configuration of a conventional laser beam scanning type image forming apparatus.

FIG. 14 is an explanatory diagram of a four-drum type image forming apparatus.

FIG. 15 is a diagram illustrating a laser beam spot of the multi-beam image forming apparatus.

FIG. 16 is a diagram showing a conventional pixel modulation circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Pixel modulation processor 2, 43 Synchronous signal generator 3, 42 Crystal oscillation circuit 4 Pixel position setting circuit 5 Counter 6 Delay circuit 7 Triangular wave signal generation part 8 D / A conversion part 9 Serial modulation part 10 Output control part 11 Divide-by-2 Circuit 12, 13, 14 Variable pulse delay circuit 15, 17 Charge pump circuit 16 Offset value control signal generation circuit 18 Peak value control signal generation circuit 19 Resistor array 20 Control current source array 21, 22 Latch array 23 Polygon mirror 24 f-θ lens Reference Signs List 25 BD mirror 26 Light receiving diode 27, 37, 38, 39, 40 Photosensitive drum 28 Semiconductor laser chip 29 Semiconductor laser diode 30 Photodiode 31 Light intensity control circuit 32 Laser driver 33 Pixel modulation circuit 34 Blanking signal generation circuit 35 Horizontal synchronization signal Raw circuit 36 pixel modulation data generation source 41 paper 44 distributed constant delay line 45 fast waveform shaping amplifier 46 D / A converter

Claims (3)

[Claims] 1. A pixel modulation device for outputting a pixel modulation signal necessary for controlling a pixel position in an image forming apparatus based on a plurality of bits of externally input pixel data and a pixel clock signal synchronized with a predetermined horizontal synchronization signal. A synchronizing signal generating means for generating a pixel clock signal synchronized with the horizontal synchronizing signal; and controlling a pixel cycle of the pixel clock signal generated by the synchronizing signal generating means to be divided into at least two divisions. And a plurality of delay circuits for delaying and outputting the pixel modulation signal based on a signal. 2. The input multi-bit pixel data,
Based on a pixel clock signal synchronized with a predetermined horizontal synchronization signal, outputs a pixel modulation signal required for pixel position control,
In an image forming apparatus for forming an image on a photosensitive drum based on the pixel modulation signal, a synchronizing signal generating means for generating a pixel clock signal synchronized with the horizontal synchronizing signal, and a pixel clock signal generated by the synchronizing signal generating means A pixel modulation circuit including a plurality of delay circuits for controlling the pixel cycle of the pixel clock signal into at least two divisions and delaying and outputting the pixel modulation signal based on the divided pixel clock signal. An image forming apparatus, comprising: at least one semiconductor laser element that is driven and controlled based on the pixel modulation signal and that outputs a laser scan according to the pixel data on the photosensitive drum. 3. The image forming apparatus according to claim 2, wherein said photosensitive drum comprises a plurality of photosensitive drums for forming a color image.