JP4787797B2 - Semiconductor laser drive control circuit and image forming apparatus - Google Patents

Description

  One embodiment of the present invention relates to a signal generation circuit, a semiconductor laser drive control circuit including the signal generation circuit, and an image forming apparatus using an electrophotographic process such as a laser printer or a digital copying machine using the semiconductor laser as a writing light source. .

  FIG. 12 shows a schematic configuration example of a general image forming apparatus using an electrophotographic process. In the figure, the laser beam output from the semiconductor laser unit 2 by the rotation of the polygon mirror 1 is deflected and scanned by the polygon mirror 1, and the photosensitive member 4 is exposed through the fθ lens 3 to form an electrostatic latent image. To do. The semiconductor laser unit 2 controls the emission time of the semiconductor laser via the laser driving circuit 7 according to the image data generated by the image processing unit 5 and the image clock whose phase is set by the phase synchronization circuit 6. The electrostatic latent image on the photoconductor 4 is controlled. The phase synchronization circuit 6 sets the clock generated by the clock generation circuit 8 to a phase synchronized with the photodetector 9 that detects the light of the semiconductor laser deflected and scanned by the polygon mirror 1.

Examples of drive control circuits for semiconductor lasers used for optical writing in this type of image forming apparatus include, for example, JP-A-5-075199, JP-A-5-235446, and JP-A-9-321376. Etc. are shown. To summarize, a photoelectric negative feedback loop that controls the semiconductor laser at high speed is constructed by constantly comparing the light receiving current of the light receiving element that monitors the light output of the semiconductor laser and the light emission command current, and the light emission command. The semiconductor laser is modulated at high speed by adding a current proportional to the current to the semiconductor laser in addition to the output current of the photoelectric negative feedback loop. By doing so, it is possible to suppress the temperature characteristics, the droop characteristics and the like of the semiconductor laser and realize high-speed modulation.
JP-A-5-075199 JP-A-5-235446 JP-A-9-321376

  As shown in FIG. 12, the laser drive circuit 7, the phase synchronization circuit 6, and the clock generation circuit 8 are an image forming apparatus using a laser scanning optical system. This is indispensable in terms of accuracy. For this reason, several paths are required in the image forming apparatus at the same frequency as the image clock, causing an EMI problem of the image forming apparatus. At the same time, the number of parts increases, resulting in an increase in cost.

  In laser printers and the like, a method of achieving high speed and high density by recording simultaneously with light from a plurality of light sources as well as light from a single light source is adopted along with high speed and high density. It's getting on. In such a case, there are a case where a plurality of semiconductor lasers are used as a light source and a case where a semiconductor laser array is used. However, conventionally, since a light receiving element is common to all semiconductor lasers with respect to a semiconductor laser array, the above-mentioned JP-A-5-075199, JP-A-5-235446, JP-A-9-321376, etc. If the semiconductor laser array is used as a result, the semiconductor laser drive control method described in 1) cannot be used.

  For this reason, when using a plurality of light sources, it may be advantageous to use a plurality of semiconductor lasers as the light sources. However, in the case of the semiconductor laser drive control method disclosed in the above-mentioned publications and the like, the light receiving current with respect to the light input of the light receiving element decreases as the light output of the semiconductor laser decreases due to the characteristics of the light receiving element that monitors the light output of the semiconductor laser The linearity of the output characteristics will deteriorate significantly. For this reason, the control accuracy in the case of a low light output is deteriorated, and the light output may be larger than a predetermined light output. When this occurs, the laser printer or the like has an adverse effect such as background contamination.

  Further, since the light output is constantly controlled, the light output cannot be completely turned off even for the normal operation of the control system. This will produce offset light. In addition, a circuit for setting a drive current for adding the drive current to the semiconductor laser is required, which entails circuit scale restrictions when improving the function of a light modulation IC such as a laser printer.

  Therefore, the present invention provides a signal generation circuit that can be appropriately driven and controlled with a low-cost and small configuration regardless of the case where there are a plurality of light sources, for example, semiconductor lasers, and whether the connection is an anode connection or a cathode connection. An object of the present invention is to provide a semiconductor laser drive control circuit provided with a signal generation circuit and an image forming apparatus using the same.

  In addition, a semiconductor laser drive control circuit capable of setting a highly accurate light intensity that can be controlled less influenced by the response speed of a light receiving element that monitors the light output of a light source, for example, a semiconductor laser, and an image forming apparatus using the same. The purpose is to provide.

  Further, a signal generation circuit capable of setting a bias current without being affected by a response speed of a light source, for example, a bias current detection circuit of a semiconductor laser, a semiconductor laser drive control circuit including the signal generation circuit, and an image formation using the same An object is to provide an apparatus.

  It is another object of the present invention to provide a semiconductor laser drive control circuit capable of obtaining an image clock with fine steps without setting the oscillation frequency of the voltage controlled oscillation circuit included in the PLL circuit high, and an image forming apparatus using the same. Objective.

  It is another object of the present invention to provide a semiconductor laser drive control circuit capable of reducing the number of terminals as an IC and reducing the size and cost, and an image forming apparatus using the same.

  It is another object of the present invention to provide a semiconductor laser drive control circuit capable of omitting a circuit for obtaining a pulse width modulation signal and reducing the size and cost, and an image forming apparatus using the same.

  It is another object of the present invention to provide a semiconductor laser drive control circuit that can easily handle pixel density and an image forming apparatus using the same.

  It is another object of the present invention to provide a semiconductor laser drive control circuit that can realize semiconductor laser control modulation and image clock generation with a single IC, and can be reduced in size and cost, and an image forming apparatus using the same.

In order to achieve the above object, a semiconductor laser drive control circuit according to the first aspect of the present invention includes a first control hold circuit that controls the maximum light output of the light source and holds the control value;
A second control hold circuit that controls the bias current of the light source and holds the control value, and a signal generation circuit comprising:
The light sources are N (where N ≧ 2) semiconductor lasers,
A PLL circuit comprising a voltage controlled oscillation circuit, a frequency dividing circuit for dividing the output of the voltage controlled oscillation circuit, and a phase comparison circuit for comparing the phase of the output of the frequency dividing circuit and a reference frequency;
N image clock output circuits that divide the output of the voltage controlled oscillation circuit and output each image clock synchronized with each phase synchronization signal ,
N signal generation circuits are provided, and each of the semiconductor lasers is individually driven and controlled based on each image clock output from the image clock output circuit , and the signal generation circuit emits light to turn on the light source. A first timing generation circuit is provided that generates a control timing for controlling the operation of the first control hold circuit by a logical sum of a command signal and a delay signal obtained by delaying the light emission command signal .

  Therefore, it is possible to control a light source, for example, any anode-connected or cathode-connected semiconductor laser with a low-cost, small and simple configuration, and it is necessary to prepare a signal generation circuit for each anode-connected and cathode-connected semiconductor laser. There is no.

  Also, the size and cost can be reduced.

Furthermore , it is possible to control a light source such as an anode-connected or cathode-connected semiconductor laser with a low-cost, compact and simple configuration, and it is necessary to prepare a signal generation circuit for each anode-connected and cathode-connected semiconductor laser. There is no.

The semiconductor laser drive control circuit of the present invention includes a first control hold circuit that controls the maximum light output of the light source and holds the control value ;
A second control hold circuit that controls the bias current of the light source and holds the control value, and a signal generation circuit comprising:
The light sources are N (where N ≧ 2) semiconductor lasers,
A PLL circuit comprising a voltage controlled oscillation circuit, a frequency dividing circuit for dividing the output of the voltage controlled oscillation circuit, and a phase comparison circuit for comparing the phase of the output of the frequency dividing circuit and a reference frequency;
N image clock output circuits that divide the output of the voltage controlled oscillation circuit and output each image clock synchronized with each phase synchronization signal,
The signal generating circuit is provided N pieces, while each individually driving and controlling the semiconductor laser on the basis of the image clock of each output from the image clock output circuit, the signal generating circuit includes a light emitting to light the light source A second timing generation circuit for generating a control timing for controlling the operation of the second control hold circuit by a logical product of the command signal and a delay signal obtained by delaying the light emission command signal ;
What slave, with a simple configuration at a low and small, anode connection, be any semiconductor laser of the cathode connection is also controllable, the anode connection, necessary to prepare a semiconductor laser signal generating circuit for each of the cathode connection Absent. In addition, it is possible to perform control that is less affected by the response speed of the light receiving element that monitors the light output of the semiconductor laser, and to set the light intensity with high accuracy. Furthermore, the bias current can be set without being affected by the response speed of the bias current detection circuit of the semiconductor laser.

The semiconductor laser drive control circuit of the present invention includes a first control hold circuit that controls the maximum light output of the light source and holds the control value;
A second control hold circuit that controls the bias current of the light source and holds the control value, and a signal generation circuit comprising:
The light sources are N (where N ≧ 2) semiconductor lasers,
A PLL circuit comprising a voltage controlled oscillation circuit, a frequency dividing circuit for dividing the output of the voltage controlled oscillation circuit, and a phase comparison circuit for comparing the phase of the output of the frequency dividing circuit and a reference frequency;
N image clock output circuits that divide the output of the voltage controlled oscillation circuit and output each image clock synchronized with each phase synchronization signal ,
N signal generation circuits are provided, and each of the semiconductor lasers is individually driven and controlled based on each image clock output from the image clock output circuit, and the signal generation circuit emits light to turn on the light source. A first timing generation circuit for generating a control timing for controlling the operation of the first control hold circuit by a logical sum of a command signal and a delay signal obtained by delaying the light emission command signal; and a light emission command for lighting the light source A second timing generation circuit for generating a control timing for controlling the operation of the second control hold circuit by a logical product of the signal and a delay signal obtained by delaying the light emission command signal ;
Therefore, the size and cost can be reduced .
Also, an aspect of the present invention, in the semiconductor laser drive control circuit, the PLL circuit, the reference frequency F, the division ratio of the frequency divider N, and FVCO the output frequency of the voltage controlled oscillator FVCO = F × (N + 0.5).
Therefore, it is possible to obtain an image clock with fine steps without setting the oscillation frequency of the voltage controlled oscillation circuit included in the PLL circuit high.
In one embodiment of the present invention, in the semiconductor laser drive control circuit, the frequency dividing ratio N of the frequency dividing circuit can be set by serial data.
Therefore, the number of terminals as an IC can be reduced, and the size and cost can be reduced.
In one embodiment of the present invention, in the semiconductor laser drive control circuit, the PLL circuit, the N image clock output circuits, and the N signal generation circuits are incorporated in a single IC.
Therefore, the size and cost can be reduced.
In one embodiment of the present invention, in the semiconductor laser drive control circuit, the N image clock output circuits output a plurality of pulse signals having different phases, and input image data and the pulse signal A pulse width generation circuit for generating a pulse width modulation signal based on the pulse width modulation signal;
Therefore, a circuit for obtaining a pulse width modulation signal can be omitted, and the size and cost can be reduced.
In one embodiment of the present invention, in the semiconductor laser drive control circuit, the pulse width generation circuit can change a pulse width modulation pattern in accordance with mode setting.
Therefore, it becomes easy to deal with pixel density.
According to another aspect of the present invention, the semiconductor laser drive control circuit includes a voltage monitoring protection circuit that monitors a voltage of a power supply for the semiconductor laser in the IC.
Therefore, semiconductor laser control modulation and image clock generation can be realized by a single IC, and the size and cost can be reduced.
The image forming apparatus of the present invention includes N (where N ≧ 2) semiconductor lasers and the semiconductor laser drive control circuit.
Therefore, the advantage of using the semiconductor laser control circuit with respect to the image forming apparatus can be utilized to facilitate handling of the pixel density.

  According to the semiconductor laser drive control circuit of the first aspect of the present invention, the first control hold circuit that controls the maximum light output of the light source and holds the control value, and the bias current of the light source is controlled and controlled. And a second control hold circuit for holding a value, so that it is possible to control a light source such as an anode-connected or a cathode-connected semiconductor laser with an inexpensive, small and simple configuration. A signal generation circuit that does not need to be prepared for each cathode-connected semiconductor laser can be provided.

  According to the semiconductor laser drive control circuit of the first aspect of the present invention, the light source is set to N (where N ≧ 2) semiconductor lasers, and the voltage controlled oscillation circuit and the output of the voltage controlled oscillation circuit are divided. A PLL circuit composed of a frequency dividing circuit that performs a phase comparison between the output of the frequency dividing circuit and a reference frequency, and the output of the voltage controlled oscillation circuit is frequency-divided and synchronized with each phase synchronization signal. 4. The N image clock output circuits for outputting the respective image clocks, and the semiconductor lasers individually driven and controlled based on the respective image clocks output from the image clock output circuit. Therefore, it is possible to reduce the size and cost of the semiconductor laser drive control circuit for driving the N semiconductor lasers.

According to the invention, in the signal generation circuit, the operation of the first control hold circuit is controlled by a logical sum of a light emission command signal for turning on the light source and a delay signal obtained by delaying the light emission command signal. Since the first timing generation circuit for generating the control timing is provided, it is possible to control with less influence by the response speed of the light receiving element that monitors the light output of the light source, for example, the semiconductor laser, and to set the light intensity with high accuracy. it can.
According to the invention, in the signal generation circuit, the operation of the second control hold circuit is controlled by a logical product of a light emission command signal for turning on the light source and a delay signal obtained by delaying the light emission command signal. Since the second timing generation circuit for generating the control timing is provided, the bias current can be set without being affected by the response speed of the light source, for example, the bias current detection circuit of the semiconductor laser.
Further, according to the semiconductor laser drive control circuit of the present invention, the light source is a semiconductor laser and a signal generation circuit for driving and controlling the semiconductor laser is provided. Any semiconductor laser can be controlled, and there is no need to prepare a signal generation circuit for each anode-connected or cathode-connected semiconductor laser, and the effect of the response speed of the light-receiving element that monitors the optical output of the semiconductor laser. The bias current can be set without being influenced by the response speed of the semiconductor laser bias current detection circuit.

  Further, according to the present invention, in the semiconductor laser drive control circuit, the PLL circuit, the N image clock output circuits, and the N signal generation circuits are incorporated in a single IC. A semiconductor laser drive control circuit for driving individual semiconductor lasers can be efficiently reduced in size and cost.

  According to the invention, in the semiconductor laser drive control circuit, the PLL circuit has a reference frequency of F, a frequency division ratio of the frequency divider circuit of N, and an output frequency of the voltage controlled oscillator circuit of FVCO. FVCO = F × (N + 0.5), so that an image clock with fine steps can be obtained without setting the oscillation frequency of the voltage controlled oscillation circuit included in the PLL circuit high. .

  Further, according to the present invention, in the semiconductor laser drive control circuit, the frequency dividing ratio N of the frequency dividing circuit can be set by serial data, so the number of terminals as an IC can be reduced, and the size and cost can be reduced. Can be planned.

  According to the present invention, in the semiconductor laser drive control circuit, the N image clock output circuits output a plurality of pulse signals having different phases, and are based on input image data and the pulse signals. Since the pulse width generation circuit for generating the pulse width modulation signal is provided, a circuit for obtaining the pulse width modulation signal can be omitted, and the size and cost can be reduced.

  Further, according to the present invention, in the semiconductor laser drive control circuit, the pulse width generation circuit can change the pulse width modulation pattern according to the mode setting, so that the pixel density can be easily handled.

  According to the present invention, the semiconductor laser drive control circuit includes a voltage monitoring protection circuit for monitoring the voltage of the power supply to the semiconductor laser in the IC, so that the semiconductor laser control modulation and the image clock can be performed by a single IC. Generation can be realized, and the size and cost can be reduced.

  Further, according to the image forming apparatus of the present invention, since the semiconductor laser drive control circuit is provided with N (where N ≧ 2) semiconductor lasers, the semiconductor laser control circuit is used for the image forming apparatus. Taking advantage of this, it is possible to facilitate pixel density compatibility.

  An embodiment of the present invention will be described with reference to FIGS. Although this embodiment is not particularly illustrated, for example, similarly to the case shown in FIG. 12, a photoconductor that modulates and drives a semiconductor laser as a light source based on an image modulation signal and rotationally drives the light of the semiconductor laser. In contrast, the present invention is applied to an image forming apparatus that forms an electrostatic latent image by performing exposure scanning at a predetermined timing based on a synchronization signal detected by a synchronization detection sensor while performing deflection scanning by a scanning means such as a polygon mirror.

  FIG. 1 is a block diagram showing a configuration example of a semiconductor laser drive control circuit according to the present embodiment. In the present embodiment, it is assumed that the image forming apparatus uses two semiconductor lasers as light sources. The semiconductor laser drive control circuit of the present embodiment has a single IC11 configuration. In this IC 11, the Voltage-Reference 12 is a reference power supply circuit for the entire IC 11 and supplies a reference power to other circuit blocks as will be described later. A reference frequency externally input by a phase comparison circuit (Phase-Detector) 13, a voltage controlled oscillation circuit (VCO) 14, a clock driver (ClockDriver) 15, and an 11-bit programmable counter (11BIT-Programmable-Counter) 16 which is a frequency divider. A PLL circuit (PLL-Loop) 17 according to F-REF is configured.

  Here, the 11-bit programmable counter 16 performs a count operation with the serial data set by the higher 11 bits of the counter register (Counter-Register) 18, and outputs a load signal when the count value reaches a set value. Further, according to the lowest bit BIT LData0 of the counter register 18, when the LData0 is “1” at the timing of the Load signal of the 11-bit programmable counter 16, the clock driver 15 outputs an inverted output with respect to the output before the load signal is input.

  This timing diagram is shown in FIG. In FIG. 2, the CLK signal is an output clock of the voltage controlled oscillation circuit 14, the Load signal is the output of the 11-bit programmable counter 16, the VCLK signal is the output of the clock driver 15, and the 1/2 CLK signal is the internal signal of the clock driver 15. Yes, the Cload signal is a timing signal for loading the count value of the 11-bit programmable counter 16. The CLoad signal is output from the clock driver 15 to the 11-bit programmable counter 16 in the same manner as the VCLK signal. Further, the memory function for the state of the VCLK signal before the Load signal is input by the 1 / 2CLK signal is exhibited. The phase comparison circuit 13 compares the reference frequency F-REF and the phase of the rising edge of the Load signal, and if there is an error, outputs it to the PLLOUT terminal according to the phase difference. A lag lead filter (not shown) is added between the PLLOUT terminal and the PLLIN terminal, and as a result, the oscillation frequency (output frequency FVCO) of the voltage controlled oscillation circuit 14 is controlled. In this way, the PLL circuit 17 is formed by the phase comparison circuit 13, the voltage control oscillation circuit 14, the clock driver 15, and the 11-bit programmable counter 16.

As a result of the configuration, the output frequency FVCO of the voltage controlled oscillation circuit 14 is determined by the reference frequency F-REF and the count setting value (frequency division ratio N) of the 11-bit programmable counter 16.
FVCO = F-REF × N (when LData0 = 0)
FVCO = F-REF × (N + 0.5) (when LData0 = 1)
It is determined as follows. Here, the voltage controlled oscillation circuit 14 is configured in a differential symmetrical form so that the duty is 50%.

  With this configuration, the output frequency FVCO of the voltage controlled oscillation circuit 14 can be set not only to an integral multiple of the human power clock (reference frequency) F-REF but also to a non-integer multiple, and a lower voltage controlled oscillation circuit. A fine oscillation frequency can be obtained at 14 oscillation frequencies.

  Here, FIG. 3 shows a circuit configuration example of the counter register 18 and FIG. 4 shows an operation timing chart. That is, the counter register 18 is composed of twelve flip-flops 19 connected in series, and 11 bits of data from LData11 to LData1 of the highest bit BIT excluding LData0 of the lowest bit BIT are set as serial data for setting the division ratio. Output to the bit programmable counter 16. Therefore, the number of terminals as the IC 11 can be reduced, and the size and cost can be reduced.

  Next, an output clock of the voltage controlled oscillation circuit 14 is input to a P clock generator 20. The P clock generator 20 is in charge of internal voltage level shift and buffer operation. The output PVCLK of the P clock generator 20 is input to an ACK selector (ACKSelector) 21 and a BCK selector (BCKSelector) 22, and the first and second phases are respectively obtained from the first and second phase synchronization signals XADETP and XBDETP. The signals Areset, Breset, ACLK, and BCLK that are synchronized with the synchronization signals XADETP and XBDETP are output. The A clock driver (AClockDriver) 23 connected to the ACK selector 21 divides the signal ACLK by 4, and the frequency divider circuit is reset by the signal Areset. In this way, the output clock of the voltage controlled oscillation circuit 14 is divided by four. The same applies to the B clock driver (BClockDriver) 24 connected to the BCK selector 22. Since the inverted state of the output clock of the voltage controlled oscillation circuit 14 is also used for the first and second phase synchronization signals XADETP and XBDETP, the first and second image clock signals APCLK, synchronized with about 1/8 clock cycle. BPCLK is obtained. Here, a first image clock output circuit 25 is formed by the ACK selector 21 and the A clock driver 23, and a second image clock output circuit 26 is formed by the BCK selector 22 and the B clock driver 24.

  This timing diagram is shown in FIG. FIG. 5 shows a case where the signal ACLK has the same phase as the previous state. The same operation is performed when the signal ACLK is in reverse phase due to ADETP. The operation of the ACK selector 21 and the A clock driver 23 and the operation of the BCK selector 22 and the A clock driver 24 differ only in the input signals between the first and second phase synchronization signals XADETP and XBDETP. Are the same. In this way, by providing only one PLL circuit 17, a two-channel phase-synchronized clock can be obtained, and the phase-synchronized accuracy can be obtained with a clock that is 1/4 of the oscillation frequency of the voltage-controlled oscillator circuit 14. Is approximately 1/8 of the clock.

  The A clock driver 23 and the B clock driver 24 output pulses having the same frequency as the image clock output signals APCLK and BPCLK in four phases. An output example of the pulse waveform on the A clock driver 23 side is shown in FIG. Hereinafter, since the A channel and the B channel are the same, only the A channel will be described. The four pulses A0 to A3 output from the A clock driver 23 are shifted in phase by 1/8 clock, and input to the AP1 selector (AP1-Selector) 27 and the AP2 selector (AP2-Selector) 28. Here, the pulse A0 is in phase with the first image clock output signal APCLK. The external input data AD0... AD3 is taken in by the A latch circuit (ALatch) 29, becomes Adata0... Adata3, and is input to the AP1 selector 27 and the AP2 selector 28. The A2 latch circuit (AP2Latch) 30 outputs Adata0... Adata3 to the AP2 selector 28 with a half clock cycle delayed.

  The AP1 selector 27 and the AP2 selector 28 select and output normal / inverted pulses A0 to A3 as shown in FIGS. 7 and 8 according to the Mode setting signal.

  FIG. 7 shows a case where Mode = 0, in which each bit of the input data is regarded as a modulation signal corresponding to each pixel. Further, the case of FIG. 8 is a case of Mode = 1, which corresponds to a pulse that performs multi-level modulation according to each data. In FIGS. 7 and 8, the output pulse is shown in a simplified manner that the shaded portion is at the H level “1”.

Thus, the signals AP1 and AP2 selected by the AP1 selector 27 and the AP2 selector 28 are finally obtained.
AP1 / A0 + AP2 / A0
The logic of “/” is inverted, “·” is logical product AND, and “+” is logical sum OR), and a pulse width modulation signal is generated. A semiconductor laser described later is modulated by this pulse width modulation signal. This timing diagram is shown in FIG. In this way, the pulse width generation circuit 31 is configured by the A latch circuit 29, the A2 latch circuit 30, the AP1 selector 27, and the AP2 selector 28, which is a signal generation circuit for one (A channel side) semiconductor laser. Output to an ALD controller (ALD-Controller) 32.

  The same applies to the other (B channel side), and a pulse width generation circuit 37 is configured by the B latch circuit 33, the B2 latch circuit 34, the BP1 selector 35, and the BP2 selector 36, and a BLD controller (BLD controller) that is a signal generation circuit. -Controller) 38.

  Next, FIG. 10 shows a signal generation circuit example of the semiconductor laser 41 in the case of common cathode. This configuration is used in the ALD controller 32 and the BLD controller 38 in FIG. The light receiving element 42 that monitors the optical output of the semiconductor laser 41 is converted into a voltage by an externally variable variable resistor VR, and the terminal voltage is input to the first error amplifier 43. The first error amplifier 43 uses the reference voltage as a reference. It is compared with the voltage Reference Voltage. When the light emission command signal LDON for the common cathode transistor 44 connected to the semiconductor laser 41 is “1”, the first hold capacitor C1 is charged with a control voltage, and the voltage between the terminals of the semiconductor laser 41 is controlled by the output. As a result, the optical output of the semiconductor laser 41 is controlled to a desired value. When the light emission command signal LDON is “0”, the first hold capacitor C1 performs an operation of holding the control value. When the light emission command signal LDON is “0”, the voltage across the terminals of the current detection resistor RE flowing through the semiconductor laser 41 is input to the second error amplifier 45 and the second hold so that the bias current is obtained. Controlled via capacitor C2. In this way, when the light emission command signal LDON is “1”, the terminal voltage of the first hold capacitor C1 is changed. When the light emission command signal LDON is “0”, the voltage of the second hold capacitor C2 is changed. Applied between the two terminals.

  In this way, when the light emission command signal LDON is “1”, control is performed so that a predetermined light output is obtained, and when the light emission command signal LDON is “0”, a predetermined bias current flows through the semiconductor laser 41. Controlled. Here, a first control hold circuit 46 is formed by the first error amplifier 43 and the first hold capacitor C1, and a second control hold circuit 47 is formed by the second error amplifier 45 and the second hold capacitor C2. Is formed.

  In the present embodiment, the AND of the output of the delay circuit 48 and the light emission command signal LDON of about 100 ns with respect to the light emission command signal LDON and the light emission command signal LDON = 0 by the AND gate 49 as the second timing generation circuit. In this case, since the terminal voltage of the current detection resistor RE becomes the light emission command signal LDON = 0, the current detection is performed by taking time to stabilize. The required specifications for the high speed of the change in the terminal voltage of the resistor RE are greatly relaxed. Similarly, in the case of the light emission command signal LDON = 1, the delay pulse by the delay circuit 47 of 100 ns and the logical sum are taken by the NOR gate 50 as the first timing generation circuit, thereby taking the time of the voltage between the terminals of the light receiving element 42. It is configured not to be affected by the delay.

  Furthermore, in the above description, the control function enable / disable (Enable / Disable) based on the light emission command signal LDON has been described. However, in the present embodiment, the control function Enable / It is configured to have a disable function. By doing so, even when there is only one light receiving element 42 for detecting the light output of the semiconductor laser 41, it is possible to control by using this function.

  FIG. 11 shows a configuration example of a signal generation circuit when an anode-connected semiconductor laser 41 is used, and the operation is the same as that of the cathode connection shown in FIG. The difference is VLD when the reference voltage Reference Voltage and the reference potential of the bias current setting voltage are cathode-connected, and when the anode is connected, a voltage generation method based on GND and the first for controlling the semiconductor laser. It is only a connection to the error amplifier 43.

  With this configuration, it is possible to selectively use an anode-connected semiconductor laser and a cathode-connected semiconductor laser by adding a little to the same signal generation circuit.

  Further, the IC 11 shown in FIG. 1 includes a power supply voltage monitoring circuit (Protect) 51. The power supply voltage monitoring circuit 51 outputs VLDErr when the power supply voltage VLD of the semiconductor laser 41 is 1.5V lower than the power supply voltage Vcc supplied to the IC 11, and the drive current to the semiconductor laser 41 is 0. And a protection circuit for protecting the semiconductor laser 41 when the supply voltage of the IC 11 falls outside the predetermined voltage range.

  By incorporating such a power supply voltage monitoring circuit 51 in the IC 11, an external power supply voltage monitoring circuit for the semiconductor laser 41 can be omitted. The MALD and MBLD signals are signals that can turn on the semiconductor laser 41 independently of the internal pulse width modulation. By doing so, the semiconductor laser 41 can be modulated even when the pulse modulation function of the IC 11 is used.

  In the present embodiment, an example of application to the case where two semiconductor lasers are used as the light source is shown, but the number N of semiconductor lasers may be three or more. In that case, the number of signal generation circuits and the number of image clock output circuits as shown in FIGS. 10 and 11 may be increased to N in accordance with the number N of semiconductor lasers.

1 is a block circuit diagram showing a configuration example in an IC which is a semiconductor laser drive control circuit showing an embodiment of the present invention. FIG. It is a time chart which shows timings, such as a Load signal. It is a block diagram which shows the structural example of a counter register. It is a time chart which shows the operation timing. It is a time chart which shows the operation timing of an image clock signal. It is a time chart which shows the pulse waveform by the side of A clock driver. It is explanatory drawing which shows the combination pattern of the output example of AP1, AP2 at the time of Mode = 0. It is explanatory drawing which shows the combination pattern of the output example of AP1, AP2 at the time of Mode = 1. It is a time chart which shows the example of a semiconductor laser drive timing by a pulse width modulation signal. It is a circuit diagram which shows the structural example of the signal generation circuit for semiconductor lasers in the case of a cathode common semiconductor laser. It is a circuit diagram which shows the structural example of the signal generation circuit for semiconductor lasers in the case of a semiconductor laser of common anode. 1 is a configuration diagram showing an outline of an optical writing system in a general image forming apparatus.

Explanation of symbols

11 IC = Semiconductor laser drive control circuit
13 Phase comparison circuit
14 Voltage controlled oscillator
16 divider circuit
17 PLL circuit
25, 26 Image clock output circuit
31 Pulse width generation circuit
32 Signal generation circuit
37 Pulse width generator
38 Signal generation circuit
41 Semiconductor laser = light source
46 First control hold circuit
47 Second control hold circuit
49 Second timing generation circuit
50 First timing generation circuit
51 Power supply voltage monitoring circuit

Claims (10)

A first control hold circuit for controlling the maximum light output of the light source and holding the control value;
A second control hold circuit that controls the bias current of the light source and holds the control value, and a signal generation circuit comprising:
The light sources are N (where N ≧ 2) semiconductor lasers,
A PLL circuit comprising a voltage controlled oscillation circuit, a frequency dividing circuit for dividing the output of the voltage controlled oscillation circuit, and a phase comparison circuit for comparing the phase of the output of the frequency dividing circuit and a reference frequency;
N image clock output circuits that divide the output of the voltage controlled oscillation circuit and output each image clock synchronized with each phase synchronization signal ,
N signal generation circuits are provided, and each of the semiconductor lasers is individually driven and controlled based on each image clock output from the image clock output circuit , and the signal generation circuit emits light to turn on the light source. A semiconductor laser drive control circuit comprising a first timing generation circuit for generating a control timing for controlling the operation of the first control hold circuit by a logical sum of a command signal and a delay signal obtained by delaying the light emission command signal . A first control hold circuit for controlling the maximum light output of the light source and holding the control value;
A second control hold circuit that controls the bias current of the light source and holds the control value, and a signal generation circuit comprising:
The light sources are N (where N ≧ 2) semiconductor lasers,
A PLL circuit comprising a voltage controlled oscillation circuit, a frequency dividing circuit for dividing the output of the voltage controlled oscillation circuit, and a phase comparison circuit for comparing the phase of the output of the frequency dividing circuit and a reference frequency;
N image clock output circuits that divide the output of the voltage controlled oscillation circuit and output each image clock synchronized with each phase synchronization signal ,
N signal generation circuits are provided, and each of the semiconductor lasers is individually driven and controlled based on each image clock output from the image clock output circuit , and the signal generation circuit emits light to turn on the light source. A semiconductor laser drive control circuit comprising a second timing generation circuit that generates a control timing for controlling the operation of the second control hold circuit by a logical product of a command signal and a delay signal obtained by delaying the light emission command signal . A first control hold circuit for controlling the maximum light output of the light source and holding the control value;
A second control hold circuit that controls the bias current of the light source and holds the control value, and a signal generation circuit comprising:
The light sources are N (where N ≧ 2) semiconductor lasers,
A PLL circuit comprising a voltage controlled oscillation circuit, a frequency dividing circuit for dividing the output of the voltage controlled oscillation circuit, and a phase comparison circuit for comparing the phase of the output of the frequency dividing circuit and a reference frequency;
N image clock output circuits that divide the output of the voltage controlled oscillation circuit and output each image clock synchronized with each phase synchronization signal ,
N signal generation circuits are provided, and each of the semiconductor lasers is individually driven and controlled based on each image clock output from the image clock output circuit , and the signal generation circuit emits light to turn on the light source. A first timing generation circuit for generating a control timing for controlling the operation of the first control hold circuit by a logical sum of a command signal and a delay signal obtained by delaying the light emission command signal; and a light emission command for lighting the light source A semiconductor laser drive control circuit comprising a second timing generation circuit that generates a control timing for controlling the operation of the second control hold circuit by a logical product of a signal and a delay signal obtained by delaying the light emission command signal . In the PLL circuit, FVCO = F × (N + 0.5) where F is a reference frequency, N is a frequency dividing ratio of the frequency dividing circuit, and FVCO is an output frequency of the voltage controlled oscillation circuit.
4. The semiconductor laser drive control circuit according to claim 1, wherein the semiconductor laser drive control circuit is set to be 5. The semiconductor laser drive control circuit according to claim 4 , wherein the frequency division ratio N of the frequency divider circuit can be set by serial data. 6. The semiconductor laser drive control circuit according to claim 1, wherein the PLL circuit, the N image clock output circuits, and the N signal generation circuits are incorporated in a single IC. 2. The N image clock output circuits output a plurality of pulse signals having different phases, and have a pulse width generation circuit that generates a pulse width modulation signal based on input image data and the pulse signal. 7. The semiconductor laser drive control circuit according to any one of items 6 to 6 . 8. The semiconductor laser drive control circuit according to claim 7 , wherein the pulse width generation circuit can change a pulse width modulation pattern in accordance with mode setting. 7. The semiconductor laser drive control circuit according to claim 6 , further comprising a voltage monitoring protection circuit for monitoring a voltage of a power supply for the semiconductor laser in the IC. N (where N ≧ 2) semiconductor lasers;
An image forming apparatus comprising: the semiconductor laser drive control circuit according to claim 1.

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