JPH1012881A - Semiconductor device and manufacture thereof, and mis device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device wherein hot carrier effect is re laxed and ON resistance is reduced without using a special film forming device and restricting a direction of a drain which forms a side wall and an orientation of a transistor when MIS transistors are connected in series on the same active region of a substrate for formation. SOLUTION: In comparison with a width w1 of a side wall SW1 which is formed on the outside side wall of gate electrodes 3-1 and 3-n of outermost MIS transistors T-1 and T-n, a width w2 of the other side wall SW2 is formed narrowly. Therefore, in compartion with the width w1 of a lightly doped region LD1 in a source 6-1 and a drain 6-(n+1) on the outside of the outermost gate electrodes 3-1 and 3-n, the width w2 of a lightly doped region LD2 in sources and drains, 6-2-6-n, among gate electrodes is formed narrowly.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to an LDD (Lightly D
The present invention relates to a semiconductor device having an oped drain structure, a method of manufacturing the same, a MIS device, and a method of manufacturing the same.

[0002]

2. Description of the Related Art As the degree of integration of MOS integrated circuits increases, transistors become finer and gate lengths are generally less than sub-μm. In MOS transistors, as the gate length becomes shorter, the short channel (Sho
rt Channel) effect and Hot Carrier effect, and to cope with miniaturization, LDD (Lightly
Doped drain) structures are commonly used. FIG.
0 is a diagram showing a configuration example of a conventional semiconductor device having an LDD structure.

In the configuration of FIG. 10, reference numeral 51 denotes a p-type
Here, it is a silicon semiconductor substrate (or well) of the first conductivity type, and 52 is a thick field oxide film for element isolation. Reference numeral 53 denotes a gate electrode selectively formed at a predetermined position on the main surface of the semiconductor substrate 51 via a thin gate oxide film 54;
Side walls formed at both ends of the
Reference numeral 56 denotes an n-type (here, the second conductivity type) impurity diffusion region serving as a source / drain region diffused on the main surface of the substrate with the gate electrode 53 interposed therebetween.
Is formed of a relatively low-concentration n ⁻ region portion 56a at a portion near both ends and a relatively high-concentration n ⁺ region portion 56b at other portions.

That is, this semiconductor device is a miniaturized short channel MOS (Metal Oxide Semiconductor).
r) type field effect transistor. In order to improve the punch-through breakdown voltage, that is, in this case, the drain breakdown voltage of the device, a so-called LDD (Lightly Doped Drain) structure, That is, the structure is such that the impurity concentration in the drain diffusion region near the gate electrode is lower than the impurity concentration in other regions.

As described above, in the short-channel MOS field-effect transistor shown in FIG. 10, the n ^- region portion 56a of the drain region 56 due to the low-concentration impurity is formed near the end of the gate electrode 53. In the other portions, n ⁺ region portions 56b of the same high concentration impurity are used.
The LDD structure makes it possible to form a so-called offset gate, control the impurity concentration profile in the channel portion, and improve the punch-through breakdown voltage of the device.

Therefore, even in a semiconductor device having a structure in which a plurality of gate electrodes are arranged in parallel on the same substrate and a plurality of MIS transistors are connected in series (a multi-input gate type MIS device), The above-described advantages can be obtained by making the MIS transistor have the LDD structure as described above.

FIG. 11 is a diagram showing a configuration example of a semiconductor device in which a plurality of MIS transistors are connected in series on the same substrate, and in this case, each MIS transistor has the same LDD structure as the transistor of FIG. In this semiconductor device, a plurality of gate electrodes 53-
1-53-n and the outermost gate electrode 53-
, 56-n, 56- (n +
1) is formed, and the predetermined conductivity type regions 56-1 to 56-1 are formed.
− (N + 1) each function as a source and / or a drain, and the semiconductor device in FIG.
IS transistors V-1 to V-n are connected in series.

In this case, the transistor V-1 is formed by the source 56-1, the gate electrode 53-1 and the drain 56-2, and the transistor V-2 is formed by the source 56-2
And the gate electrode 53-2 and the drain 56-3, the predetermined conductivity type regions 56-2 to 56-n between the gate electrodes are shared as the drain and source of the adjacent transistor.

[0009] In the semiconductor device in FIG. 11, each of the predetermined conductivity type region 56-1~56- (n + 1) includes a low-concentration impurity regions LD _1, both side walls of each gate electrode 53-1 to 53-n It is formed by the high concentration impurity regions HD defined by the width w ₁ of the sidewall SW ₁ formed. That is, each of the transistors V-1 to V-n has L
It has a DD structure.

[0010] Here, in the semiconductor device in FIG. 11, the width of the sidewall SW ₁ is formed on both sidewalls of the gate electrodes 53-1 to 53-n are all a same width, the areas 56 - 1 to 56- (n + 1) low concentration impurity regions LD ₁
Width w ₁ of also, it is all made with the same width. In this case, since each lightly doped region LD ₁ having a predetermined width w ₁ is having a predetermined resistance value, a plurality of transistors V-1 to V-n are connected in series, each of the low-concentration impurity regions LD ₁ is a connected semiconductor device in series, the ratio of the resistance the low concentration impurity regions LD ₁ in the oN resistance of the semiconductor device is increased.

As described above, generally, in an LDD structure device, a high resistance in a low-concentration impurity region causes an increase in ON resistance. In particular, when transistors are connected in series, this increase in resistance is not significant. Become noticeable. That is, the ON resistance of the MIS device increases as the number of MIS transistors, that is, the number of gate electrodes increases.

In order to solve such a problem (ie, to reduce the ON resistance due to the low-concentration impurity region of the LDD structure), for example, a method as disclosed in Japanese Patent Application Laid-Open No. 2-76236 is used. As shown in FIG.
It is also conceivable to form a sidewall only on the drain side of each transistor.

In the structure shown in FIG. 12, since a sidewall is formed only on the drain side of the gate electrode and no sidewall is formed on the source side, a low-concentration impurity region is not formed on the source side. , The resistance of the low concentration impurity region can be reduced, and the ON resistance can be reduced.

[0014]

However, FIG.
In order to manufacture the device of
A film is formed obliquely by an anisotropic film forming method such as ECRCVD, and utilizing the fact that the film thickness on the side surface that becomes the shadow of the gate becomes thinner, reactive ion etching is used to etch back to the drain side. Only the sidewall must be formed, a special film forming device such as an ECRCVD device that performs film formation by tilting the substrate is required, and the direction of the drain forming the sidewall and the direction of the transistor are limited. Another problem arises.

According to the present invention, the MIS is formed on the same active region of the substrate.
In the case where transistors are connected in series, the hot carrier effect can be reduced without using a special film forming apparatus and without limiting the direction of the drain forming the sidewall or the direction of the transistor. , And ON
It is an object of the present invention to provide a semiconductor device capable of reducing resistance, a method of manufacturing the same, a MIS device, and a method of manufacturing the same.

[0016]

In order to achieve the above object, according to the first, second, third, fourth, fifth and sixth aspects of the invention, the gate of each MIS transistor is provided. Each low-concentration impurity region formed between the electrodes is formed narrower than the low-concentration impurity region outside the gate electrode of the outermost MIS transistor. Thereby, even when each MIS transistor has an LDD structure,
The ON resistance of the MIS transistors connected in series can be reduced.

According to the seventh aspect of the present invention, each MIS
An oxide film containing a predetermined conductivity type impurity is buried between the gate electrodes of the transistors, and the predetermined conductivity type impurity of the oxide film is solid-phase diffused into the substrate, so that a high-concentration impurity is formed between the gate electrodes of the MIS transistors. Since the impurity regions are formed, the width of the low-concentration impurity regions can be reduced between the gate electrodes, while the width of the high-concentration impurity regions can be increased, and the ON resistance of the MIS transistors connected in series can be reduced. . In particular, in the present invention, at least the first sidewall is formed of the silicon nitride film even when the predetermined conductivity type impurity of the oxide film containing the predetermined conductivity type impurity is solid-phase diffused into the substrate. This allows
Diffusion of impurities from the oxide film containing impurities to the gate can be suppressed.

Further, according to the present invention, the space (interval) between the gate electrodes is set to 0.4 μm or less,
An oxide film containing impurities for forming a high-concentration impurity region by solid-phase diffusion is left only in the space between the gate electrodes,
It can be left in open spaces.

According to a ninth aspect of the present invention, a first conductivity type channel MIS device has the structure of the semiconductor device according to any one of the first to eighth aspects.
Thereby, in the complementary MIS device, each MIS
Even when the transistor has an LDD structure, the ON resistance of the MIS transistor connected in series can be reduced.

According to the tenth and twelfth aspects of the present invention, after a plurality of gate electrodes are formed on the substrate, a low-concentration impurity of a predetermined conductivity type is implanted into the substrate to form a low-concentration impurity region. Next, a first sidewall is formed on both sides of each gate electrode, and a second sidewall is formed on the first sidewall formed outside the outermost gate electrode. A high-concentration impurity is implanted into the same active region of the substrate to form a high-concentration impurity region. Thus, the structure of the semiconductor device according to the first to fourth aspects can be realized, and the ON resistance of the MIS transistors connected in series can be reduced.

According to the eleventh and twelfth aspects of the present invention, after forming a plurality of gate electrodes on the substrate, a low-concentration impurity of a predetermined conductivity type is implanted into the substrate to form a low-concentration impurity region. Next, a sidewall is formed outside the outermost gate electrode, and thereafter, a high-concentration impurity of a predetermined conductivity type is implanted into the substrate to form a high-concentration impurity region. Thereby, the structure of the semiconductor device according to the fifth and sixth aspects can be realized, and the ON resistance of the MIS transistors connected in series can be reduced.

According to the thirteenth aspect of the present invention, the MIS device according to the ninth aspect can be manufactured.

[0023]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a configuration example of a semiconductor device according to the present invention. In the semiconductor device of FIG. 1, a plurality of gate electrodes 3-1 to 3-n are arranged on the same semiconductor substrate 1 via gate oxide films 2-1 to 2-n, and a plurality of gate electrodes 3-1 to 3-n are arranged. Between 3-n and outside the outermost gate electrodes 3-1 and 3-n, the substrate 1 has predetermined conductivity type regions 6-1, 6-2,... 6-n, 6- (n + 1). Are formed, and the predetermined conductivity type regions 6-1 to 6- (n + 1) function as a source and / or a drain, respectively, so that the semiconductor device of FIG. The MIS transistors T-1 to T-n are connected in series.

In this case, the transistor T-1 is formed by the source 6-1 and the gate electrode 3-1 and the drain 6-2, and the transistor T-2 is formed by the source 6-2, the gate electrode 3-2 and the drain 6-2. -3, and the predetermined conductivity type regions 6-2 to 6-6 between the gate electrodes.
n is commonly used as the drain and source of adjacent transistors.

In the semiconductor device of FIG. 1, the predetermined conductivity type region 6-6 functioning as a source and / or a drain is provided.
Each of 1 to 6- (n + 1) is formed by a low-concentration impurity region and a high-concentration impurity region defined by the width of a sidewall formed on both side walls of each of the gate electrodes 3-1 to 3-n. ing. That is, each of the MIS transistors T-1 to T-n is also the same as each of the MIS transistors V-
Similarly to 1 to Vn, it has an LDD structure.

[0026] However, in the semiconductor device of FIG. 1, the outermost of the MIS transistor T-1, T-n width w of the sidewall SW ₁ which are formed on the outside of the side walls of the gate electrode 3-1,3-n of compared to _1, the other side wall SW ₂ is formed smaller in width w _2, therefore, outside the source 6-1 of the outermost gate electrode 3-1,3-n,
Low concentration impurity region LD ₁ in drain 6- (n + 1)
Compared to the width w ₁ of the source, drain,
That is, the low-concentration impurity regions LD in 6-1 to 6-n
_2, the width w ₂ is reduced (the source and drain of the MIS transistor T-1 of the outermost, T-n are formed asymmetrically with respect to the gate electrode).

In other words, assuming that the distance d between the gate electrodes is the same in the semiconductor device of FIG. 1 and the semiconductor device of FIG. 11, the conventional semiconductor device of FIG. The width is (d−2w ₁ ), and in the semiconductor device of the present embodiment in FIG. 1, the width of the high-concentration impurity region HD is (d−2w ₂ ), and w ₁ > w ₂ . In the semiconductor device according to the first embodiment, compared to the related art,
The width of the high-concentration impurity region can be increased by (w ₁ −w ₂ ).

In the semiconductor device having such a configuration, the width w ₂ of the low-concentration impurity region is set at the source and drain between the gate electrodes of the adjacent MIS transistors T-1 to Tn.
Is small and the proportion of low-concentration impurity regions is small (because the width of high-concentration impurity regions between gates is widened if the gate spacing is constant). , Multiple MIs with LDD structure
Even when the S transistors are connected in series, the ON resistance can be reduced.

In this semiconductor device, a plurality of MISs
Since the transistors T-1 to T-n are connected in series, the drain voltage of each MIS transistor is divided and lowered, and therefore, the width of the low concentration impurity region in the source and drain between the gate electrodes is reduced. Is smaller, the hot carrier effect is reduced in the transistors T-2 to T-n other than the outermost transistors T-1 and T-n. Also in this case, the source side of the outermost transistors T-1, at the drain side of the transistor T-n, since there is a possibility that the hot carrier effect is generated, similarly to the conventional widths w ₁ of the sidewall SW ₁ increased to some extent, there is a need to some extent increase the width w ₁ of the low concentration impurity regions LD _1.

Although the sidewall SW ₂ is provided between the gate electrodes in the configuration example of FIG. 1, for example, as shown in FIG. 2, no sidewall is provided between the gate electrodes, and the source and the drain between the gate electrodes are provided. All of 6-1 to 6-n may be formed as high-concentration impurity regions HD. In other words, it is possible to form the low concentration impurity regions LD ₁ of a predetermined conductivity type only on the outside of the outermost gate electrode 3-1,3-n.

In the semiconductor device of FIG. 1 or FIG. 2, the high-concentration impurity region HD can actually be formed by burying an oxide film containing a second conductivity type impurity between gate electrodes. FIGS. 3 and 4 show the gate electrode 3-1 in the semiconductor device of FIGS. 1 and 2, respectively.
A state in which an oxide film 8 containing a predetermined conductivity type impurity is buried between .about.3-n is shown.

In this configuration, the gate electrodes 3-1 to 3-n
An oxide film 8 containing an impurity of a predetermined conductivity type is buried in a space therebetween, and the impurity of a predetermined conductivity type contained in the oxide film 8 is solid-phase diffused into the substrate 1 to thereby provide a high-concentration impurity region HD.
Can be formed. In this case, as described later, the distance d between the gate electrodes 3-1 to 3-n is set to 0.4 μm.
It is preferable to set the following.

The semiconductor device shown in FIG. 1 (FIG. 3) or FIG. 2 (FIG. 4) can be formed as an n-channel MIS device. In this case, the predetermined conductivity type impurity is an n-type impurity. Used. That is, the low concentration impurity region is formed as an n ⁻ region, and the high concentration impurity region is formed as an n ⁺ region.

In the semiconductor device of FIG. 1 (FIG. 3) or FIG. 2 (FIG. 4), each of the MIS transistors T-1 to T-
n may be formed directly on the substrate 1 (although the predetermined conductivity type (for example, n-type) regions 6-1 to 6-n may be formed directly on the substrate 1). Type (for example, n
It is also possible to form a region (well) of the opposite conductivity type (for example, p-type) to the region (well) and to form the region (well). In other words, each of the MIS transistors T-1 to T-n may be formed on the same active region of the substrate.

Next, an example of a manufacturing process of the semiconductor device of the present invention will be described. 5 (a) to 5 (c) and FIG. 6 (d) show FIG.
FIG. 4 is a diagram illustrating an example of a manufacturing process when the semiconductor device of FIG. 3 is manufactured as an n-channel device.

In this example of the process, first, a plurality of gate electrodes (3) are formed on the substrate 1 via a gate oxide film (2) at a predetermined interval d (preferably 0.4 μm or less as described later). (At an interval d) (FIG. 5A). Next, from the direction of arrow A (from the direction perpendicular to the surface of the substrate 1), an n ⁻ -type impurity (low-concentration impurity) is implanted into the substrate 1 to form a low-concentration impurity region LD (FIG. 5B).

Thereafter, first side walls 11 (SW ₂ ) having a thickness of w ₂ are formed on the side walls on both sides of each gate electrode (3), and then the outer side walls of the outermost gate electrode (3) are formed. the second sidewall 12 is formed on the first side wall 11 formed in, a sidewall SW ₁ thickness w ₁ together these (Fig. 5 (c)). As a result, the first sidewall 11 is provided on both sides of each gate electrode (3).
(SW ₂ ) is formed, and a second sidewall 12 is further formed on the first sidewall 11 (SW ₂ ) outside the outermost gate electrode. Note that at least the first side wall 11 (SW ₂ ) in contact with the gate electrode (3) is preferably a silicon nitride film.

Next, an oxide film 8 containing an n-type impurity is buried between the gate electrodes 3, and a predetermined conductivity type impurity contained in the oxide film 8 is solid-phase-diffused into the substrate 1, whereby By implanting n ⁺ -type impurities (high-concentration impurities), high-concentration impurities HD can be formed (FIG. 6D), and FIG. 1 (FIG. 3)
Can be manufactured.

The semiconductor device shown in FIG. 2 (FIG. 4) can also be manufactured by the same steps as described above except that no sidewall is provided between the gate electrodes (3).

As described above, in the above-described process example, when MIS transistors are connected in series on the same substrate and formed, no special film forming apparatus is used, and the direction of the drain for forming the sidewalls is reduced. Without limiting the direction of the transistor or the direction of the transistor, a semiconductor device capable of reducing the hot carrier effect and reducing the ON resistance can be manufactured.

In the structure of the semiconductor device shown in FIG. 1 (FIG. 3) or FIG. 2 (FIG. 4), the impurity is diffused from the source / drain impurity implantation conditions and the oxide film 8 containing the impurity in the above-described manufacturing process. Depending on the heat treatment and overall thermal history of the heat treatment, it can be designed in any way. That is, only the low concentration impurity region outside the outermost gate electrode is wider than the other low concentration impurity regions, or only the high concentration impurity region outside the outermost gate electrode is larger than the other high concentration impurity regions. Whether it is formed at a position farther from the gate electrode or whether the low-concentration impurity region exists only outside the outermost gate electrode can be designed in any way by impurity implantation, heat treatment and overall thermal history, Asymmetric structure M
A multi-input gate type LDD-MIS semiconductor device structure including IS can be realized.

In other words, in the semiconductor device of the present invention, only the low-concentration impurity region outside the outermost gate electrode can be regarded as being formed wider than the other low-concentration impurity regions. It can be considered that only the high-concentration impurity region HD outside the outermost gate electrode is formed at a position farther from the corresponding gate electrode than the other high-concentration impurity regions HD.

Further, the structure of the semiconductor device shown in FIG. 1 (FIG. 3) or FIG. 2 (FIG. 4) has a complementary M type device comprising a first conductivity type channel MIS device and a second conductivity type channel MIS device.
In an IS device, for example, the first conductivity type channel M
It can be applied to IS devices.

FIG. 7 is a diagram showing a configuration example of a complementary MIS device according to the present invention. Referring to FIG. 7, MIS device of this complementary includes a MIS device DV ₁ of a first conductivity type channel (e.g., n-channel), made from the MIS device DV ₂ Metropolitan of the second conductivity type channel (e.g., p-channel) I have.

[0045] In the example of FIG. 7, MIS device DV ₁ of a first conductivity type channel (n-channel) has become a structure of a semiconductor device of FIG. 1 (FIG. 3). In FIG. 7,
For convenience, the case where the number n of MIS transistors in one MIS device is 3 is shown. In addition, the MIS device DV _{1 of} the first conductivity type channel (n channel)
May have the structure of the semiconductor device of FIG. 2 (FIG. 4).

FIGS. 8 (a) to 8 (c) and FIGS. 9 (d) to 9 (f) are views showing an example of a manufacturing process of the complementary MIS device of FIG.

[0047] When fabricating a complementary MIS device of Figure 7, the p-well region 21 MIS device DV ₁ of a first conductivity type channel (n-channel) is formed, MIS of the second conductivity type channel (p-channel) a n-well region 22 the device DV ₂ is formed is formed on the substrate, p-well region 2
The 1 and n well regions 22 are separated from each other to form a gate oxide film. Incidentally, hereinafter, the entire area MIS device DV ₁ of n channel is formed is referred to as a n-channel transistor region, called the entire area MIS device DV ₂ of the p-channel is formed with p-channel transistor region.

Next, the polysilicon is deposited by CVD at 0.2
μm film is formed, a resist is applied thereon, the resist is patterned by photolithography to expose only the polysilicon on the p-channel transistor region, boron is implanted into the p-channel transistor region, and the resist is similarly formed. Is applied and the resist is patterned by photolithography to expose only the polysilicon on the n-channel transistor region, and arsenic is implanted into the n-channel transistor region. Then, a polycide WSi _x C
A film is formed to a thickness of about 0.2 μm by the VD method, and the NSG film is
A film is formed to a thickness of about 0.5 μm by a VD method, then a resist is applied, and the resist is lithographically formed to form a gate resist pattern.

Here, the gate resist pattern was formed such that the gate width was, for example, 0.3 μm and the space d between the gates was, for example, 0.4 μm or less.

Next, NS is performed by an oxide film ECR etching apparatus.
The G-film is etched to form a plurality of gate electrode structures (3) to each etched WSi _x and polysilicon polycide for ECR etching apparatus p-channel transistor region, n-channel transistor region. Thereafter, a resist mask is applied to the p-channel transistor region, and only the n-channel transistor region is implanted with a low-concentration impurity (n ^- impurity) for the LDD structure and a boron pocket is implanted for suppressing punch-through.

Next, an n-channel transistor region, p
Each gate electrode of each of the channel transistor regions
A first sidewall (11) of SiN _x is formed on the side wall of (3) (FIG. 8A). That is, a film of SiN _{x is formed} to a width w ₁ of 0.01 μm by a CVD method, and this is etched back to form a first sidewall (11).

Next, p ⁺
For implantation, the n-channel transistor region is masked with a resist, for example, boron of 5E15 cm ⁻² is implanted, and a 0.3 μm-thick phosphor glass (8) is formed by a CVD method.
(FIG. 8 (b)). Thereafter, etching back is sufficiently performed under a condition of a large RIE-Lag (microloading effect), for example, a condition of a gas containing CH ₂ F ₂ and CH ₄ having a large ratio of CH ₂ F ₂ . As a result, the phosphorus glass completely disappears in the open space portion, and the phosphorus glass (23) remains only between the gates in a space of 0.4 μm or less (FIG. 8C).

Next, the n-channel transistor region is masked with a resist (24), only the p-channel transistor region is etched back, and p ⁺ impurities are implanted.
The resist (24) is removed (FIG. 9D). This gives p
Phosphorus glass (8) existing in a narrow space of 0.4 μm or less of parallel gates on the channel transistor region side
Can be removed (FIG. 9E). Then, RTA (rapid therm
Al heat treatment is performed for a short time, and only heat treatment is left between the gate electrodes in the n-channel transistor region.
Phosphorus of the phosphorus glass (8) is diffused in the substrate (in the p-well region 21). Thereby, an n-type high-concentration impurity region (n ⁺ region) HD can be formed in the n-channel transistor region. Next, a high-temperature oxide film HTO is formed to a thickness of 0.14 μm, which is etched back to form a 0.01 μm-wide S formed outside the outermost gate electrodes of the n-channel transistor region and the p-channel transistor region.
In addition to the first sidewall (11) of iN _x, a second sidewall (1) of HTO having a width of 0.10 μm is further formed.
2) is formed. Thereby, a sidewall having a total width of 0.15 μm can be formed outside the outermost gate electrode (FIG. 9F).

Next, the p-channel transistor region is masked with a resist, and n ⁺
Impurities are implanted and 0.15 from the outermost gate electrode to the outside of the outermost gate electrode in the N-channel transistor region.
An n-type high-concentration impurity region (n ⁺ region) can be formed at a distance of μm. Hereinafter, an interlayer film is formed by a normal complementary MOS process, and wiring and passivation are performed.
Can be manufactured.

As described above, in the n-channel transistor region, the structure of the semiconductor device shown in FIG. 1 (FIG. 3) or FIG. 2 (FIG. 4) can be realized, and the ON resistance of the MIS transistors connected in series can be reduced. A MIS device can be provided.

In the above-described process example, in particular, after the n ⁻ implantation is completed and the sidewall is formed, the oxide film 8 containing impurities is formed.
Is formed, a resist mask is formed in the n-channel transistor region, and etch back is performed before p ⁺ implantation into the p-channel transistor region, and a resist mask is formed in the p-channel transistor region and n ^{+ is} implanted into the n-channel transistor region. Thus, the amount of etch back of oxide film 8 containing impurities in the p-channel transistor region can be increased, and removal of oxide film 8 can be ensured.

By changing the impurity of the oxide film 8 buried in the space between the gates to B (arsenic), this structure can be similarly applied to a p-channel transistor by a similar manufacturing method.

[0058]

Embodiments of the present invention will be described below.

(Example 1) In Example 1, the state of embedding of the phosphorus glass (oxide film 8) at the time of performing the step of FIG. Examined. Table 1 shows a space interval d between a plurality of gate electrodes.
Shows the state of embedding of phosphorus glass when is changed.

[0060]

[Table 1]

From Table 1, it can be seen that in the n-channel MIS device, when the space distance d between the gate electrodes is 0.5 μm, no phosphorus glass is buried, but the space distance is 0.4, 0.35, 0.3. , 0.25 μm, it can be seen that phosphorus glass was embedded. In addition, it was confirmed that no phosphorus glass was embedded in any of the p-channel MIS devices at any of the space intervals. Thereby, the distance d between the gate electrodes is 0.4 μm
It is preferred that:

(Embodiment 2) In Embodiment 2, a semiconductor device of the present invention using SiN _x for the first sidewall spacer
For comparison with the (device of the present invention), samples (conventional devices) in which the first sidewall spacer was formed of a high-temperature oxide film HTO were manufactured, and the characteristics of these samples, that is, the characteristics of each semiconductor device (sample) The threshold voltage _Vth of the transistor was compared between the case where only one gate electrode was provided (in the case of an isolated gate) and the case where there were a plurality of gate electrodes.

Table 2 shows the results of these comparisons (ie,
In each of the semiconductor devices (samples), there is shown a comparison result of the threshold voltage _Vth of the transistor between a case where there is only one gate electrode (in the case of an isolated gate) and a case where there are a plurality of gate electrodes.

[0064]

[Table 2]

As shown in Table 2, in the conventional sample using the HTO high-temperature oxide film as the first sidewall, the Vth (threshold voltage) of the transistor having the isolated gate and the Vth of the transistor having the plurality of parallel gates are different from each other. However, in the sample of the present invention using SiN _x for the first sidewall, the Vth of the isolated gate transistor
No difference between (threshold voltage) and Vth of transistors with multiple parallel gates, SiN _x sidewalls prevent diffusion of impurities from phosphorus glass to p-channel polycide gate polysilicon You can see that it is doing. From this, as the first sidewall, S
It can be seen that it is preferable to use iN _x .

Example 3 In Example 3, a MIS device was manufactured as the device of the present invention in accordance with the steps shown in FIGS. 8 (a) to 8 (c) and 9 (d) to 9 (e). At this time, a plurality of parallel gate electrodes as shown in FIGS. 8 and 9 are formed on the n-well (p-channel transistor region), and a TEG pattern for forming an isolated and a plurality of parallel gates on the n-well is used. . On a single p-well (n-channel transistor region), two gate electrodes
Devices having three, four, and four gate electrodes were respectively mounted with gate intervals (spaces) of 0.4, 0.35,.
The device was manufactured at 3,0.25 μm, and the characteristics of each device were evaluated. For comparison, a conventional MIS device having an LDD structure as shown in FIG. 11 was manufactured. Table 3 shows the conventional device as shown in FIG.
The gate width and the distance d between the gates are each 0.25 μm.
The comparison result of the ON current when the number n of gates was changed from one to four is shown.

[0067]

[Table 3]

From Table 3, it can be seen that in the isolated gate device (device having one gate), the ON current was 0.6 mA / μm in both devices, but in the case of two gates, The ON current is 0.3mA / μm
On the other hand, in the device of the present invention, 0.39 mA / μm
And 30% improvement. In the case of four gates, the device of the present invention showed an improvement of 50% or more. From this, it was found that the semiconductor device of the present invention can further reduce the ON resistance as compared with the conventional semiconductor device.

Further, the p-channel transistor is a surface channel transistor, and WSi is formed on p-type polysilicon.
The polycide obtained by laminating a _x using the gate electrode of the p-channel transistor, a polycide formed by laminating a WSi _x was prepared also dual polycide gate device used in the gate of the n-channel transistor on the n-type polysilicon. This device showed an effect of suppressing impurity diffusion into the p-type gate by the thin SiN sidewall.

[0070] Thus, in the present invention, since the transistor are connected in series, since the drain voltage drops, Hot Carrier effect transistors other than the outermost is relaxed, thus, n between adjacent gate ^- layer the narrowed by widening the n ⁺ layer, it can mitigate the hot carrier effect, and can reduce the overall ON resistance. That is, this space is 0.35 μm or less for sub-half μm or quarter μm or less.
μm or 0.25 μm, this space can be filled with an oxide film containing impurities, and the impurities contained in the oxide film can be removed from the substrate by a solid phase diffusion method that has been used in semiconductor devices for a long time. By solid phase diffusion to
A high concentration layer can be formed under the oxide film, and the ON resistance of these series-connected transistors can be reduced.

[0071]

As described above, according to the first, second, third, fourth, fifth, and sixth aspects of the present invention, between the gate electrodes of the MIS transistors. Each low-concentration impurity region to be formed is formed to be narrower than the low-concentration impurity region outside the gate electrode of the outermost MIS transistor.
Even when a DD structure is provided, the ON resistance of the MIS transistors connected in series can be reduced.

According to the seventh aspect of the present invention, each M
An oxide film containing a predetermined conductivity type impurity is buried between the gate electrodes of the IS transistors.
Since the high-concentration impurity regions are formed between the gate electrodes of the S transistors, the width of the low-concentration impurity regions is reduced between the gate electrodes, while the width of the high-concentration impurity regions is increased. Can be reduced. In particular, in the present invention, even when the predetermined conductivity type impurity of the oxide film containing the predetermined conductivity type impurity is solid-phase diffused into the substrate, at least the first sidewall is formed of the silicon nitride film. Diffusion of an impurity from an oxide film containing silicon to a gate can be suppressed.

According to the eighth aspect of the present invention, by setting the space (interval) between the gate electrodes to 0.4 μm or less, the oxidation including impurities for forming the high-concentration impurity region by solid-phase diffusion is performed. The film can be left only in the space between the gate electrodes and not in the open space.

According to the ninth aspect of the present invention, the first conductivity type channel MIS device has the structure of the semiconductor device according to any one of the first to eighth aspects. , Each complementary MIS device
Even when the transistor has an LDD structure, the ON resistance of the MIS transistor connected in series can be reduced.

According to the tenth and twelfth aspects of the present invention, after forming a plurality of gate electrodes on the substrate, a low-concentration impurity of a predetermined conductivity type is injected into the substrate to form a low-concentration impurity region. Then, a first sidewall is formed on both sides of each gate electrode, and a second sidewall is formed on the first sidewall formed outside the outermost gate electrode. A high-concentration impurity of a predetermined conductivity type is implanted into the same active region of the substrate to form a high-concentration impurity region, so that the structure of the semiconductor device according to any one of claims 1 to 4 can be realized. ON resistance can be reduced.

According to the eleventh and twelfth aspects of the present invention, after forming a plurality of gate electrodes on the substrate, a low-concentration impurity of a predetermined conductivity type is injected into the substrate to form a low-concentration impurity region. Then, a sidewall is formed outside the outermost gate electrode, and then a high-concentration impurity of a predetermined conductivity type is injected into the substrate to form a high-concentration impurity region. And the ON resistance of the MIS transistors connected in series can be reduced.

According to the thirteenth aspect of the present invention, the MIS device according to the ninth aspect can be manufactured.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration example of a semiconductor device according to the present invention.

FIG. 2 is a diagram showing another configuration example of the semiconductor device according to the present invention.

FIG. 3 is a diagram showing a modification of the semiconductor device of FIG. 1;

FIG. 4 is a diagram showing a modification of the semiconductor device of FIG. 2;

FIG. 5 is a diagram showing an example of a manufacturing process of the semiconductor device of FIGS. 1 and 3;

FIG. 6 is a diagram illustrating an example of a manufacturing process of the semiconductor device of FIGS. 1 and 3;

FIG. 7 is a diagram showing a configuration example of a complementary MIS device according to the present invention.

FIG. 8 is a diagram illustrating an example of a manufacturing process of the MIS device in FIG. 7;

FIG. 9 is a diagram illustrating an example of a manufacturing process of the MIS device in FIG. 7;

FIG. 10 is a diagram illustrating a configuration example of a conventional semiconductor device having an LDD structure.

11 is a diagram illustrating a configuration example of a semiconductor device in which a plurality of MIS transistors are connected in series to the same substrate, and in this case, each MIS transistor has the same LDD structure as the transistor in FIG.

FIG. 12 is a diagram illustrating a configuration example of a semiconductor device in which a plurality of MIS transistors are connected in series to the same substrate, and in this case, a sidewall is formed only on the drain side of each MIS transistor.

[Explanation of symbols]

Reference Signs List 1 semiconductor substrate 2 gate oxide film 3 gate electrode 6 predetermined conductivity type region (source and / or drain) 8 oxide film 11 (SW ₂ ) first sidewall 12 second sidewall LD low concentration impurity HD high concentration impurity region

Claims (13)

[Claims] In a semiconductor device having a structure in which a plurality of MIS transistors are formed in series on the same active region of a substrate, each MIS transistor has a source and a drain in a low-concentration impurity region of a predetermined conductivity type. And LDD formed by high-concentration impurity regions of a predetermined conductivity type
The source and the drain of the outermost MIS transistor are formed asymmetrically with respect to the gate electrode among a plurality of MIS transistors on the same active region and connected in series. A semiconductor device characterized by the above-mentioned. 2. The semiconductor device according to claim 1, wherein each of the low-concentration impurity regions formed between the gate electrodes of the MIS transistors has a width greater than that of the low-concentration impurity region outside the gate electrode of the outermost MIS transistor. A semiconductor device characterized by being narrowly formed. 3. The semiconductor device according to claim 1, wherein the distance between each high-concentration impurity region formed between the gate electrodes of each MIS transistor and the corresponding gate electrode is equal to the distance of the outermost MIS transistor. A semiconductor device formed to be smaller than a distance between a high-concentration impurity region outside a gate electrode and the gate electrode. 4. The semiconductor device according to claim 1, wherein a first sidewall is formed on both sides of a gate electrode of each MIS transistor, and an outermost MIS transistor is formed. Outside the gate electrode of the transistor, a second sidewall is further formed on the first sidewall, and at least the first sidewall is formed.
A side wall formed of a silicon nitride film. 5. In a semiconductor device having a structure in which a plurality of MIS transistors are formed in series on the same active region of a substrate, each MIS transistor has a source and a drain at least of a predetermined conductivity type high-concentration impurity region. A semiconductor device, wherein a predetermined conductivity type low-concentration impurity region is formed only outside the gate electrode of the outermost MIS transistor. 6. The semiconductor device according to claim 5, wherein a first sidewall is formed outside a gate electrode of the outermost MIS transistor, and a second sidewall is further formed on the first sidewall. A semiconductor device, wherein a sidewall is formed, and at least the first sidewall is formed of a silicon nitride film. 7. The semiconductor device according to claim 1, wherein an oxide film containing a predetermined conductivity type impurity is buried between gate electrodes of the MIS transistors. Wherein the high-concentration impurity region is formed between the gate electrodes of the respective MIS transistors by solid-phase diffusing the predetermined conductivity type impurity into the substrate. 8. The semiconductor device according to claim 1, wherein an interval between the gate electrodes is equal to or less than 0.1.
A semiconductor device having a thickness of 4 μm or less. 9. A complementary MIS comprising a first conductivity type channel MIS device and a second conductivity type channel MIS device.
9. A MIS device, wherein the first conductivity type channel MIS device has the structure of the semiconductor device according to claim 1.
device. 10. A plurality of MISs on the same active region of a substrate.
In a method for manufacturing a semiconductor device having a structure in which transistors are connected in series, after forming a plurality of gate electrodes on a substrate, a low-concentration impurity region of a predetermined conductivity type is injected into the substrate to form a low-concentration impurity region. Forming, then forming a first sidewall on both sides of each gate electrode, and further forming a second sidewall on the first sidewall formed outside the outermost gate electrode; Forming a high concentration impurity region by injecting a high concentration impurity of a predetermined conductivity type into a substrate. 11. A plurality of MISs on the same active region of a substrate.
In a method for manufacturing a semiconductor device having a structure in which transistors are connected in series, after forming a plurality of gate electrodes on a substrate, a low-concentration impurity region of a predetermined conductivity type is injected into the substrate to form a low-concentration impurity region. Forming a side wall outside the outermost gate electrode, and then implanting a high-concentration impurity of a predetermined conductivity type into the substrate to form a high-concentration impurity region. Production method. 12. The method for manufacturing a semiconductor device according to claim 10, wherein the high-concentration impurity of the predetermined conductivity type is an oxide film containing the predetermined conductivity type embedded between gate electrodes of each MIS transistor. A method of manufacturing a semiconductor device, wherein a predetermined conductivity type impurity of the oxide film is injected into a substrate by solid-phase diffusion into the substrate. 13. A complementary MI comprising a first conductivity type channel MIS device and a second conductivity type channel MIS device.
In the method of manufacturing the S device, the first conductivity type channel M
Injecting a low concentration first conductivity type impurity into the IS device region,
Next, a first sidewall is formed.
After an oxide film containing a conductive type impurity is formed and etched back, a mask is formed in the first conductive type channel MIS device region by lithography, and the second conductive type channel MIS is formed.
An MIS device characterized in that after exposing the device region and etching back the oxide film containing the first conductivity type impurity, a first conductivity type high concentration impurity is introduced into the second conductivity type channel MIS device region. Production method.