JPH1012690A - Semiconductor device having pattern for checking - Google Patents

Abstract

PROBLEM TO BE SOLVED: To monitor the electrical characteristic of a semiconductor device by providing a plurality of checking element areas having different sizes in an internal element area arranged in an internal transistor pattern and obtaining the same gate size from a transistor to be checked and internal transistor. SOLUTION: A gate pattern having a plurality of finished checking gate width sizes X11, X12, X13, and X14 is formed by forming a plurality of checking element areas having different lengths. The checking element area of the checking gate having the same width size as the finished gate width size of an internal gate 21 is selected from the gate pattern and used for checking the characteristics of a channel type transistor constituting an internal circuit. Therefore, the electrical characteristic of the channel-type transistor can be monitored with accuracy from a checking pattern by measuring the finished gate size of the internal gate 21 while a gate 1 is exposed after the gate pattern is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a check pattern in a semiconductor device, and more particularly to a check pattern in a semiconductor device for evaluating transistor characteristics of an internal circuit.

[0002]

2. Description of the Related Art Conventionally, a check pattern in a semiconductor device is usually a single transistor having a gate having the same design dimensions as an internal gate disposed in an internal transistor in an empty area of a circuit configuration at a corner of the semiconductor device. A check pattern for characteristics is formed, and the electric characteristics of the internal transistor of the semiconductor device are measured using the pattern.

FIG. 3 shows a conventional N-channel check transistor pattern.

In this conventional check pattern, a gate 1 is arranged on a check element region 10 of a substrate surrounded by an element isolation region 3 such as a field oxide film formed by a selective oxidation method, and the check element regions 10 on both sides thereof are arranged. N-type diffusion layers 2 and 2 are provided therein, electrode pads 6 and 6 are respectively connected to the N-type diffusion layers through contacts 5, and an electrode pad 7 is connected to gate 1 through contacts 4.

A check element region 10 forming a pair of N-type diffusion layers 2 serving as a source and a drain and a channel region below the gate 1 has a length L5 and a width W.

[0006] One straight pattern gate 1 is a gate of an internal transistor constituting an integrated circuit.
That is, the design dimensions are the same as those of the internal gate.

The reason why the electrical characteristics of internal transistors are measured using a check transistor pattern as shown in FIG. 3 is that tens of thousands of transistors such as a gate array have been developed due to recent progress in miniaturization of LSIs and improvement in the degree of integration. Since the provision of a pattern for measuring transistor characteristics in an internal circuit composed of several million gates reduces the degree of integration, a pattern mainly based on the circuit configuration is usually arranged in the internal circuit. The patterns for evaluating the characteristics were not arranged. Therefore, the characteristics of a single transistor characteristic check pattern are measured in an empty area of the circuit configuration.

FIG. 4 shows a model diagram of internal circuit elements of a CMOS gate array.

In a CMOS gate array, a diffusion layer can be formed in both an N-type and a P-type diffusion layer depending on the type of impurity to be ion-implanted. In a CMOS gate array, both types are usually formed.

Normally, in an internal transistor of a CMOS gate array, a plurality of N-channel type internal device regions 20 and a plurality of P-channel type internal device regions 30 are regulated via an element isolation region 3 such as a field oxide film by a selective oxidation method. Are arranged in a way.

The N-channel internal element region 20 has a width W6,
A plurality of straight pattern internal gates 21 are arranged on this region having a planar shape with a length L6, and N and N serving as a source and a drain are formed on both sides of the internal gate 21 and at the location of the internal element region 20 between the internal gates 21. A mold diffusion layer 22 is formed. That is, the internal element region 20 of the substrate is N
Type diffusion layer 22 and a channel region below the internal gate 21. To obtain a desired circuit configuration, the internal gate 21
Is connected to an electrode wiring (not shown) such as aluminum through a contact 4, and the N-type diffusion layer 22 is connected to an electrode wiring (not shown) such as aluminum through a contact 5.

Similarly, the P-channel type internal element region 30 has a planar shape of a width W7 and a length L7, and a plurality of straight-pattern internal gates 31 are arranged on this region. A P-type diffusion layer 32 serving as a source and a drain is formed in a portion of the internal element region 30 between the gates 31. That is, the internal element region 30 of the substrate is composed of a P-type diffusion layer 32 and a channel region below the internal gate 31. To obtain a desired circuit configuration, the internal gate 31 is connected to an electrode wiring (not shown) of aluminum or the like through a contact. The N-type diffusion layer 32 is connected to an electrode wiring (not shown) of aluminum or the like through a contact.

Incidentally, in order to avoid the drawing being complicated,
Only some of the contacts 4 and 5 are shown.

In order to check the characteristics of, for example, an N-channel transistor of a CMOS gate array as shown in FIG. 4, an N-channel check transistor pattern as shown in FIG. 3 has conventionally been used.

However, with the miniaturization of LSIs and the enlargement of chips, when the gate size reaches about 0.5 μm, the gate size of the gate 1 in the check pattern and the internal gate 21 of the internal transistor have the same design size. Also, the dimensional difference between the finished gate dimensions after the gate patterning of the two has become remarkable.

The following reasons are considered as the cause. First, the gate 1 disposed on the check element region 10 (width W, length L5) and the internal gate disposed on the N-channel type internal element region 20 (width W6, length L6) in the conventional check pattern. When patterning the gates 21 at the same time, the widths and lengths of the device regions 10 and 20 in which the gates 1 and 21 are arranged are different from each other, resulting in a difference in the resist film thickness applied on the gates. When working under gate etching conditions, a dimensional difference occurs in the finished gate dimensions.

The check pattern is a single transistor pattern disposed in an empty area of a circuit configuration such as a corner portion of a semiconductor device, and the gate 1 is a base pattern having no gate pattern around. However, the internal gates 21 and 31 arranged in the internal transistors are dense patterns in which the patterns are very tight.

Therefore, when patterning the two, a difference occurs in the resist film thickness applied on the gate, and when working under the same exposure conditions and gate etching conditions, a dimensional difference occurs in the finished gate dimensions.

The electrical characteristics of the transistor depend on the finished gate dimensions. When there is a difference between the completed gate dimensions of the gate 1 and the internal gate 21 on the check pattern, the electrical properties of the two show different characteristics. I will.

On the other hand, as another prior art, Japanese Patent Application Laid-Open No. 56-138936 discloses a check pattern as shown in FIG. 5 for evaluating variations in semiconductor elements in a semiconductor device.

In FIG. 5, in manufacturing a semiconductor device,
Impurity diffusion layers 61, 62, 63, 64 as resistance elements
Pattern 5 in which the surface areas of dielectric films used as masks for the formation of the impurities are different from each other on the surface of the semiconductor device when the semiconductor device 55 is selectively formed on semiconductor substrate 55.
1, 52, 53 and 54. In this conventional technique, for example, by measuring element resistance values of these resistance elements, a correlation between a resistance difference between the resistance elements and an oxide film area (dielectric film area) can be quantitatively known. It is intended to provide more precise control of the diffusion layer. FIG. 5A is a plan view, and FIG.
It is sectional drawing of the BB part of (A).

[0022]

As described above, the prior art shown in FIG. 3 has a drawback that the same finished dimensions cannot be obtained for the internal transistor and the check transistor, despite the same gate design dimensions.

The electrical characteristics of transistors in a semiconductor device depend on the completed dimensions of the gate. If the same completed dimensions cannot be obtained for the internal transistor and the check transistor, there is also a difference in the electrical characteristics of each transistor. Occurs.

Therefore, even if the electrical characteristics measured with the check transistor pattern are within the standard, it cannot be determined whether the electrical characteristics of the internal transistor satisfy the standard, and the characteristics of the internal transistor cannot be determined. It could not be monitored accurately.

In the prior art shown in FIG. 5, the surface area of the dielectric film surrounding the impurity diffusion layer is formed in different patterns. However, the purpose of the technique in FIG. This is to know the correlation between each resistance value with respect to the size, and has nothing to do with trying to obtain the same gate size for the check transistor and the internal transistor.

An object of the present invention is to obtain the same gate size for a check transistor and an internal transistor and measure the electrical characteristics of the check transistor to accurately monitor the electrical characteristics of the internal transistor. An object of the present invention is to provide a semiconductor device having a check pattern that can be used.

[0027]

A feature of the present invention is that, in a check pattern of a semiconductor device in which an internal transistor pattern and a check pattern are formed on the same substrate, an internal element region arranged in the internal transistor pattern is provided. A plurality of check element regions of variable size are arranged around the size, a gate is arranged so as to connect the plurality of check element regions, and an electrode pad is formed from the gate portion and each check element region through a contact. In a semiconductor device having a check pattern having a drawn-out structure. Here, the plurality of check element regions in the check pattern may have a constant width in a direction parallel to the arranged gate pattern and different lengths in a vertical direction. Further, the check pattern may have the same gate pattern as the gate pattern of the internal transistor.

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

A first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a plan view of an N-channel check transistor pattern in the semiconductor device according to the first embodiment of the present invention.

As shown in FIG. 1, in the check transistor pattern of the present invention, first, an element isolation region 3 such as a field oxide film is selectively grown on a semiconductor substrate by a selective oxidation method. , 30 at the same time as being surrounded by element isolation region 3 and
Are formed, the first, second, third and fourth check element regions 11, 12, 13, 14 are formed.

The first, second, third, and fourth check element regions 11, 12, 13, and 14 have a constant width W in a direction parallel to a gate pattern 1 to be arranged later, and a width in a vertical direction. , The length L centered on the length L6 in the N-channel type internal element region 20 of the internal transistor shown in FIG.
1, L2, L3, and L4.

At this time, the width W of the check element region is a standardized value for evaluating the transistor characteristics, and the width W6 of the internal element region 20 arranged in the internal transistor is determined.
And may be different.

Next, the design width dimension value is the same as that of the internal gate 21 shown in FIG. 4 (X4) so that the first, second, third, and fourth check element regions 11, 12, 13, and 14 are connected. Is formed in one straight pattern at the same time when the internal gate 21 is formed. afterwards,
When the N-type diffusion layer 22 serving as a source and a drain is formed at the location of the internal element region 20, the first, second, third, and fourth check element regions 11, 12, 13, and 14 are also provided under the gate 1. N-type diffusion layers 2 serving as a source and a drain are formed on both sides of each channel region.

Then, an electrode pad 7 connected to the gate 1 through the gate contact 4 and an electrode pad 6 connected to each N-type diffusion layer 2 through the contact 5 are formed. In FIG. 1, the illustration of the electrode pads 6 for the first to third check element regions 11, 12, 13 is omitted.

In the first embodiment, the first, second, third and fourth check element regions 11, 12, 1
Since the lengths L1, L2, L3, and L4 are different from each other in the elements 3 and 14, due to the influence of the step with the element isolation region 3 and the like,
When the pattern of the gate 1 is formed, a difference occurs in the resist film thickness applied on the gate.

Therefore, when working under the same exposure conditions and etching conditions, the respective completed gate dimensions X11, X12, X13 on the first, second, third and fourth check element regions 11, 12, 13, and 14 are obtained. , X14.

In the check pattern of the present invention, for example, the length L6 in the N-channel internal element region 20 disposed on the internal transistor and the length L3 in the third check element region 13 of the check pattern are the same length. And diffusion layer lengths L1, L in the other first, second and fourth check element regions 11, 12, 14.
2, L4 are changed at intervals of ± 30 to 50 μm with respect to the length L3, and the first, second, third, and fourth regions having different region lengths.
Check element regions 11, 12, 13, and 14 are arranged in advance.

As a result, the completed gate dimension X4F of the internal gate 21 and the third pattern of the check pattern are obtained.
The completed gate dimension X13 of the gate 1 on the check element region 13 is a gate pattern on the same region layer length, and the completed gate width dimensions of both are the same or equivalent.

However, simply arranging the check element regions in the check pattern with the same length of the internal element regions arranged by the internal transistors does not result in the same finished gate size of both, resulting in a dimensional difference. .

This is because, as described above, the width W6 of the N-channel type internal element region 20 in the internal circuit is different from the width W of the check element region in the check transistor, or the internal circuit and the check transistor have different widths in the semiconductor device. This is because the arrangement position of the gate (the central part or the peripheral part) is different or the coarse density of the gate pattern is different.

In the above example, even if the completed gate size X13 of the internal gate 21 and the gate 1 on the third check element region 13 are not the same, the first, second, and fourth check patterns are used. Any one of the gates 1 on the check element regions 11, 12, 14
Thus, the same finished gate dimensions as the internal gate 21 can be obtained.

Therefore, by forming a plurality of check element regions having different lengths in the check pattern of the present invention, a plurality of completed check gate widths X1 are formed.
A gate pattern having 1, X12, X13, and X14 is formed, and a check element region of a check gate having the same width as the completed gate width X4F of the internal gate 21 is checked from among them. Used for

Therefore, the gate 1 after the gate pattern is formed
Is exposed, the internal gate 2 as shown in FIG.
The finished gate dimension X4F of No. 1 is measured. Next, the completed gate dimensions X11, X12, X13, X14 on the first, second, third, and fourth check element regions 11, 12, 13, and 14 on the check pattern are measured, and the internal gate 21 is measured. Finished gate dimensions X4F
Find one that has the same dimensions as.

After completion of the diffusion process, the internal gate 21
By performing electrical measurement using a check pattern having the same completed gate dimension X4F as the completed gate dimension, the transistor characteristics of the internal element can be accurately monitored.

For example, when the gate 1 on the second check element region 12 has the same gate dimension as the final gate dimension X4F of the internal gate 21, the gate 1 of FIG. The electrode pads 6 and 6 connected to the N-type diffusion layers 2 and 2 on both sides of the gate 1 in the second check element region 12 through the contact 5 are used as a source electrode and a drain electrode, respectively. The transistor characteristics on the region 12 can be measured, and these characteristics can be the transistor characteristics of the internal element.

According to the method of manufacturing a check pattern of the present invention, the check pattern of the present invention can be obtained by exactly the same manufacturing method as in the related art, only by changing the mask of the diffusion layer pattern and the gate pattern arranged in the check pattern. Can be done.

Further, even when the completed gate dimensions X11 to X14 of the check pattern of the present invention cannot be the same as the completed gate dimensions X4F of the internal gate 21, even when the completed gate dimensions of the check pattern are measured. For the completed gate dimension X4F of the internal gate 21, the completed gate dimension X11
~ X14, the nearest finished gate dimension can be found, so that a transistor having a gate having a size close to the completed gate dimension of the internal transistor among the completed gate dimensions X11 to X14 is electrically connected to the transistor. Obtaining the electrical characteristics makes it possible to easily monitor the electrical characteristics of the internal transistor.

Although the first embodiment has been described with reference to the N-channel type check transistor pattern, the type of the diffusion layer in the check pattern of the present invention is either N-type or P-type diffusion layer depending on the type of the impurity to be ion-implanted. It is needless to say that the present invention can be applied to an N-channel check transistor pattern and a P-channel check transistor pattern.

Next, a second embodiment of the present invention will be described.
This will be described with reference to FIGS. FIG. 2 shows a second embodiment of the present invention.
FIG. 10 is a plan view of an N-channel type check transistor pattern according to the embodiment. In FIG. 2, the same or similar parts as those in FIG.
Duplicate description will be omitted as much as possible.

The difference from the first embodiment is that the first to fourth check element regions 1 in the check pattern are different.
Internal element region 20 arranged in an internal transistor in one of the check element regions among 1, 12, 13, and 14
Has the same length L6 and the same width W6, and has a length L1
Only the length L4 is variable around the length L6 of the region arranged by the internal transistors.
Is that a plurality of straight pattern gates 1 and 1 are arranged so as to extend over the check element regions 11, 12, 13 and 14.

In the second embodiment, the gate design dimensions X2 and X4 are set to the same value in the check pattern and the internal transistor pattern, and the space design widths Y2 and Y4 between the gates are the same. By setting the value to a value, the same gate pattern is provided on each element region of the check pattern and the internal transistor pattern.

In the second embodiment, the check pattern and the internal transistor pattern are provided with the same gate pattern on the element regions having the same length and the same width. Is small, and the finished gate size difference is small.

Therefore, by providing a plurality of check element region patterns having different region lengths as in the second embodiment, the completed gate dimensions of the internal circuit can be accurately obtained by the gates of the check pattern.

[0054]

As described above, in the check pattern of the present invention, the electrical characteristics are measured using the check transistor pattern having the same completed gate width as that of the internal gate. Therefore, there is an effect that the electrical characteristics of the internal transistor can be accurately monitored by the check pattern of the present invention.

[Brief description of the drawings]

FIG. 1 is a plan view showing an N-channel type check transistor pattern according to a first embodiment of the present invention.

FIG. 2 is a plan view showing an N-channel type check transistor pattern according to a second embodiment of the present invention.

FIG. 3 is a plan view showing an N-channel type check transistor pattern according to the related art.

FIG. 4 is a plan view showing an internal element pattern of a CMOS gate array.

5A and 5B are diagrams showing another conventional technique, in which FIG. 5A is a plan view, and FIG. 5B is a cross-sectional view taken along the line BB of FIG. 5A.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 check pattern gate 2 check pattern N-type diffusion layer 3 element isolation region 4, 5 contact 6, 7 electrode pad 10 check element region 11 first check element region 12 second check element region 13 third Check element area 14 Fourth check element area 20 N-channel internal element area 21 Gate of N-channel internal element 22 N-type diffusion layer of N-channel internal element 30 P-channel internal element area 31 P-channel internal element area Gate 32 P-type diffusion layer of P-channel type internal element 51, 52, 53, 54 Mask pattern 55 Semiconductor substrate 61, 62, 63, 64 Impurity diffusion layer X11 Finished gate dimension on first check element region X12 Second Finished gate dimension on check element area X13 Third check element area Finished gate dimension on top X14 Finished gate dimension on fourth check element region X2 Gate design dimension of check pattern X4 Gate width design dimension of internal transistor pattern X4F Finished gate width dimension of internal gate Y2 Space between gates of check pattern Design dimension Y4 Space design dimension between gates of internal transistor pattern L1 Length of first check element area L2 Length of second check element area L3 Length of third check element area L4 Fourth check element area L5 Length of check element region L6 Length of N-channel internal element region L7 Length of P-channel type internal element region W Width of check element region W6 Width of N-channel type internal element region and check element region W7 Width of P-channel type internal element region

Claims (3)

[Claims] 1. A semiconductor device according to claim 1, wherein said internal transistor pattern and said check pattern are formed on the same substrate. A plurality of check element regions are arranged and provided, a gate is arranged so as to extend over the plurality of check element regions, and an electrode pad is drawn out from the gate portion and each check element region through a contact. A semiconductor device having a check pattern. 2. The method according to claim 1, wherein the plurality of check element regions in the check pattern have a constant width in a direction parallel to the arranged gate pattern and a different length in a direction perpendicular to the gate pattern. The semiconductor device according to claim 1, wherein: 3. The semiconductor device according to claim 1, wherein the check pattern has the same gate pattern as a gate pattern of the internal transistor.