JPH10126214A - Filter circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a full differential type filter circuit which does not require a DC feedback by mutually combining and connecting an odd number of integrating circuits which are more than three and constituting a full differential type filter of even order. SOLUTION: Integrating circuits 11 to 13 are equipped with Gm circuits Gm1+, Gm1- to Gm3+, and Gm3- which input and output complete differential signals. Integrating capacitors C1 to C3 are connected to their outputs. An input Vin is inputted to the input of the Gm circuit Gm1+. Both the ends of the integrating capacitor C1 are connected to the input of the Gm circuit Gm2+. Both the ends of the integrating circuit C2 are connected to the input of the Gm circuit Gm3+. Both the ends of the integrating capacitor C3 are connected to an output Vout and also connected to the Gm circuit Gm1- to Gm3- of the integrating circuit 11 to 13. Thus, the integrating circuits 11 to 13 are constituted in an even number of stages to realize a distortion-free filter circuit which requires on DC feedback.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a basic filter circuit for performing analog signal processing in a MOS semiconductor integrated circuit.

[0002]

2. Description of the Related Art In recent years, with the increase in digital equipment and the advance in digital signal processing technology, C
MOS integrated circuits have become a dominant part of the semiconductor market.

[0003] However, since the input and output of video and audio are analog, it is easier to process them in analog. Even if they are processed digitally, A / D and D / A conversion, filter processing before and after that, and clock processing are performed. An analog circuit is required for an oscillator or the like for generation. Bipolar is suitable for analog circuits, and CMOS has been considered unsuitable except for some circuits such as analog switches and sample and hold circuits. However, the cost of the bipolar and BiCMOS processes is slightly higher, and there is a strong demand for one-chip integration of digital and analog circuits in CMOS, and circuit development for performing analog signal processing in CMOS has become active.

There is an "active filter" as an important function that is frequently used in analog signal processing and greatly affects the total performance. Conventionally, a CMOS analog active filter has mainly been a filter based on discrete time processing such as a switched capacitor filter (SCF) and a sample data filter. These have the advantage that the frequency characteristics are accurately determined by the clock, and the accuracy is high because they are hardly affected by the device variation caused by the manufacturing process. A continuous time filter is required before and after because of the presence of aliasing. 2. Since it requires a band that is many times the frequency handled by the operational amplifier and the sample hold (S / H), it cannot be used for a high-frequency filter that is higher than the video band. 3. The circuit scale is large and not economical. The drawback is that you can't make a simple and cheap filter that can be used up to high frequencies. This is a problem due to the discrete-time filter, and is difficult to solve. Therefore, recently, an attempt to develop a continuous-time CMOS filter with good performance has begun.

[0005] The most popular continuous time filter is a multi-stage secondary filter called a "biquad circuit" in which two integrating circuits each composed of a transconductance (Gm) circuit and a capacitor are combined. A technique of obtaining filter characteristics is used. In bipolar, transconductance (voltage-current conversion characteristics) is linearized using a resistor or a gain cell. However, since the gm (transconductance) value of the element is small in the CMOS, if the same method is used, a large number of elements having a large size are required, and the economic efficiency is extremely low. Therefore, a transconductance characteristic is obtained by voltage-current conversion using a differential pair transistor directly connected to the source.

However, the characteristic of the source voltage versus the drain current of the MOS transistor is a square characteristic, and the integral characteristic of the current versus the voltage of the capacitor is linear. When the integrated output is taken out as a single, a large second-order distortion occurs. Therefore, it is necessary to cancel the second-order distortion by treating both the input and the output as completely differential signals. In such full differential processing, the DC voltage of the output is usually not determined as it is, so that a separate bias circuit for determining DC (operating point) is required. For this reason, generally, a method is employed in which a DC voltage of an output is detected and DC bias is applied to a bias of an input section of the Gm circuit. This is called DC feedback (or common mode feedback or the like).

FIG. 9 shows a conventional example of a biquad circuit having such a DC feedback. The range enclosed by the broken line in this circuit represents the integration circuits 91 and 92, the output terminals of which are composed of two common Gm circuits and the integration capacitor connected to the output terminal. G on the left of each of the integrating circuits 91 and 92
The m circuits Gm1 + and Gm2 +
Gm circuits Gm1- and Gm2- below correspond to a negative input (feedback input) in the single configuration. As described above, the two integrating circuits 91 and 92 are cascaded to form an LPF or the like.

The DC feedback 1 and the DC feedback 2 monitor the output of each integration circuit and control the bias current of the input section of the Gm circuit, so that the output D
The C voltage is set to a certain set voltage. By changing the input position of the signal or the extraction position of the output signal, a secondary BPF or HPF other than the LPF can be produced.

[0009] The integrating circuit constituting the filter of FIG.
FIG. 10 shows an example of a specific circuit realized by the MOS process. The Gm circuit that realizes the transconductance characteristic uses a source-coupled differential pair. Gm1 +, Gm2
The portion corresponding to + is a differential circuit composed of M1, M2 and I1, and the portion corresponding to Gm1- and Gm2- is a differential circuit composed of M3, M4 and I2. These current outputs add at the output point. The output is differentially extracted by biasing with two current sources connected to GND. Each of these current sources must have an exactly (I1 + I2) / 2 relationship with respect to the bias currents I1 and I2 of the differential input. If this relationship is slightly out of order, the DC impedance of the output terminal of the integrating circuit is very high, and the output DC current is unbalanced due to imbalance between the upper and lower current sources.
The voltage fluctuates greatly and becomes unstable and undefined.

"DC feedback" is a countermeasure circuit for this purpose, which fixes the DC potential of the output to a certain value and stabilizes it. The other end of the resistor whose one end is connected to the output end in FIG. 10 is connected to the target voltage Vref.
Is compared with the operational amplifier. The output signal is 2
If the two resistances are equal, the midpoint is the DC of the output signal.
The potential can be taken out. This is compared with Vref, and if it is higher, the current of the current source is controlled so as to increase, and the common mode voltage of the output is reduced. Conversely, if it is lower than Vref, the current of the current source is controlled to decrease, and the common mode voltage of the output is increased. In this way, control is performed so that the common-mode potential of the output signal becomes equal to Vref. This circuit biases the DC voltage of the differential output of each of the integrating circuits constituting the filter to Vref, respectively, but causes an increase in the number of elements.
This is because the operational amplifier itself requires a considerable number of elements, and in addition, it is necessary to provide a buffer as shown in the figure so that the presence of the resistor that detects the midpoint voltage does not affect the high impedance integrated output terminal. is there. Moreover,
Since this DC feedback circuit is required for each integration circuit, the whole filter occupies a considerable area.

For example, in the circuit shown in FIG. 10, the inside of the left dotted line, which is an essential part of the integration circuit, is composed of four MOS transistors, four current sources and one capacitor.
The DC feedback circuit for bias setting is about 20 to 30 elements, whereas the
/ 3. Since the filter is simply designed by combining the integrators for the order, the DC feedback occupies about ／ of the entire filter. As described above, the necessity of using the direct-current feedback causes an increase in the cost of the fully differential filter, which hinders the realization of an inexpensive filter circuit.

[0012]

As described above, Gm
In order to realize a continuous-time filter using an integrating circuit composed of a circuit and a capacitor in CMOS, it is indispensable to remove the second-order distortion which is likely to occur in principle by using a fully differential type. Because of the DC bias setting,
DC feedback is required for each integration circuit. Since this circuit requires a considerable number of elements, the overall circuit scale is significantly increased, leading to an increase in cost.

An object of the present invention is to provide a fully differential filter circuit that does not require DC feedback.

[0014]

In order to solve the above-mentioned problems, the present invention provides one or two pairs of differential input terminals and one pair of differential input terminals.
An integration circuit is configured by a transconductance circuit having a pair of differential output terminals and configured by a field effect transistor, and a capacitor connected to the differential output terminal. , Whereby an odd-order fully differential filter is formed.

By the means described above, the number of stages of the integrating circuit is set to an odd number to make the common-mode feedback loop a negative feedback. In this case, each field-effect transistor is self-biased to a current value determined by the current source on the drain side in the common-mode negative feedback operation of the feedback loop, so that a dedicated bias circuit is not required. Accordingly, the number of elements constituting the filter circuit can be significantly reduced, and a cost-effective CMOS filter can be realized.

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a circuit configuration diagram for explaining a first embodiment of the present invention. In this embodiment, a three-stage integrator circuit LP
The F configuration is characterized in that each of the integrating circuits is a fully differential circuit in which both the input and the output are fully differential signals, and the number of stages of the integrating circuit is an odd number. The point is that the use of the odd-numbered stages eliminates the need for DC feedback required for a fully differential circuit.

Numerals 11 to 13 denote integrating circuits, and the triangle symbols of the integrating circuits 11 to 13 each represent a Gm circuit having a differential input and a differential output. The integrating circuit 11 has a Gm circuit Gm1 whose input and output are both fully differential signals.
+, Gm1-, and each output is connected to an integrating capacitor C1. The input Vi is input to the input of the Gm circuit Gm2 +.
Enter n. The integrating circuit 12 includes Gm circuits Gm2 + and Gm2- whose inputs and outputs are both fully differential signals, and each output is connected to an integrating capacitor C2.
Both ends of the capacitor C1 are connected to the input of the Gm circuit Gm1 +. The integrating circuit 13 includes Gm circuits Gm3 + and Gm3- whose inputs and outputs are both fully differential signals, and each output is connected to an integrating capacitor C3. Both ends of the capacitor C2 are connected to the input of the Gm circuit Gm3 +. Both ends of the integrating capacitor C3 are connected to the output Vou.
t, and to the Gm circuits Gm1- to Gm3- of the integration circuits 11 to 13, respectively.

Gm1 + Gm3 + corresponds to a + input in the single configuration, and Gm1- to Gm3- correspond to a-input (feedback input) in the single configuration.

Here, the transfer function between the input and output of this circuit is obtained assuming that the gm value of each Gm circuit is Gm1 +, Gm1-: gm1 Gm2 +, Gm2-: gm2 Gm3 +, Gm3-: gm3. become.

[0020]

(Equation 1) As is apparent from this equation, in the case of the circuit of this embodiment, since the zero point of the transfer function exists three times at the infinite frequency, the third-order LPF characteristic as shown in FIG. Become.

As described above, in this embodiment, since the integrating circuit having the fully differential configuration is constituted by the odd number of stages,
Since a distortion-free filter circuit that does not require feedback can be realized, a high-order filter circuit can be configured on a small scale at low cost.

FIG. 2 shows a specific circuit diagram of the integration circuits 11 to 13 in FIG. That is, the first transconductance circuit Gmi + connects the source directly to the power supply Vcc.
Source-coupled differential MOS transistors M1,
The differential signal of the preceding stage is input to the gate.
The second transconductance circuit Gmi- is composed of source-coupled differential MOS transistors M3 and M4 whose sources are directly connected to the power supply Vcc, and a gate receives a feedback differential signal. The first and second transconductance circuits Gmi + and Gmi− connect drain terminals having the same polarity to each other, and output positive and negative terminals (positive: Ai, negative: Bi).
An integrating capacitor Ci is connected between the two terminals, and both ends thereof are set as differential output terminals Vout + (Ai) and Vout- (Bi). Both terminals are biased by the current source Vb.

In order to check the operation of this circuit, the voltage-current conversion characteristics of the MOS transistors M1 and M2 are calculated. Here, it is assumed that the input signal is a fully differential signal, and it is assumed that MOS transistors M1 and M2 have the same characteristics and are both biased in the saturation mode region.

If the output resistance and the substrate bias effect are neglected, the drain current I of the MOS transistors M1 and M2 is
1, I2 are represented as follows.

M1: I1 = (β1 / 2) (VGS1-Vth1) 2 (1) M2: I2 = (β1 / 2) (VGS2-Vth1) 2 (2) where β = μCoxW / L = μ (Εox / tox) W
/ L, μ is the electron mobility in the device, εox is the dielectric constant of the gate oxide film, tox is the gate oxide film pressure, W is the gate width, and L is the gate length.

If the difference current between the drain currents I1 and I2 of the MOS transistors M1 and M2 is output, the output is (1)
From (2), I1−I2 = (β1 / 2) (VGS1 + VGS2-2Vth1) (VGS1−VGS2) = (β1 / 2) (VGS1 + VGS2-2Vth1) Vin. The DC voltage of the input signal with respect to the power supply Vcc is Vb
Then, the input is a fully differential signal. In this case, the source terminals of the MOS transistors M1 and M2 are connected to the power supply Vcc and fixed, so that VGS1 + VGS2 = 2Vb.

Therefore, I1−I2 = β1 (VB−Vth1) Vin (3), and the transconductance Gm from the differential input voltage to the differential output current of this circuit is as follows: Gm = Iout / Vin = (I1- I2) / Vin = β1 (VB−Vth1) (4) Equation (4) does not include a term dependent on the input signal Vin, and causes “Vin” that causes second-order distortion.
Item 2 ”is not included. If the element pair (M1 = M2) is completely taken, Gm is ideally determined mainly by the W / L ratio of the element. Therefore, as long as the output is obtained differentially, the gm value is constant without depending on the input. The variation of Vth1 can be adjusted by adjusting the input bias voltage Vb.
It can be seen from equation (4) that the value can be positively changed.

As described above, the transconductance circuit is operated as a common-source fully differential operation by
A second-order distortion problem that is likely to occur in a CMOS analog circuit can be solved, and a transconductance characteristic with good linearity can be obtained. Furthermore, since it is not necessary to place a current source at the differential source connection point, the power supply voltage can be used effectively by that voltage, and there is an advantage that the voltage is reduced.

The circuit shown in FIG. 2 is an example in which the PMOS is used for the differential transistor. However, the integration circuit can be configured in exactly the same manner even when the power supply and GND are reversed and the NMOS is used for the differential transistor. The same effect can be obtained.

In the transconductance circuit of FIG. 2, the source is directly connected to the ground point, and the source is not biased by connecting the source to a current source as in a general differential circuit. Cannot be removed. In fact, by using this in reverse, the DC feedback in the filter circuit of FIG. 1 is not required. That is, the differential circuit composed of the MOS transistors M1 and M2 has a high inversion gain with respect to the common-mode voltage between the input and the output since each source is fixed by the power supply. That is, when both the input gate voltages rise, the output drain voltages both fall greatly. vice versa,
When both the gate voltages, which are the inputs, decrease, the drain voltage of the output both greatly increases. The same applies to the differential circuit formed by the MOS transistors M3 and M4, which also has a high inversion gain with respect to the input common-mode voltage.

Therefore, when the circuit of FIG. 1 is viewed from the viewpoint of transmission of the common mode voltage, the following is obtained. Gm2 + → Gm3 + → Gm1- → Gm2 governs the feedback operation of the entire circuit.
This is the outermost loop that returns along the + path. Considering the transmission of the common-mode voltage starting from the outputs A1 and B1 of the integration circuit 11, the inversion is performed by Gm2 +, Gm3 +, and Gm1-, and 3
Since it inverts once and returns, the loop becomes negative feedback. The two points Ai and Bi of the integration circuits 11 to 13 have a voltage of GN.
The operation is performed so as to settle to a voltage determined by the current value of the bias current source on the D side.

For example, all the MOS transistors constituting the integration circuit have the same shape, and G
Assuming that the bias current values on the ND side are all equal, the operation is performed so that all the voltages of the outputs Ai (i = 1 to 3) and Bi (i = 1 to 3) of each stage become equal. This voltage is I
Assuming that I and I2 are half the current value of each current source, they are equal to the value of VGS obtained by substituting these values into equations (1) and (2). However, for the input only, it is necessary to predict the convergence voltage in advance and apply a common-mode voltage close thereto to the input Vin. In this case, each field effect transistor is self-biased to a current value determined by the current source on the drain side, and does not require a dedicated DC feedback circuit.

As described above, in this embodiment, the number of elements can be significantly reduced, and the cost-effective CM
An OS filter can be realized. In this embodiment, a filter constituted by three stages of integration circuits 11 to 13 has been described. However, if the number of stages of integration circuits is odd, transmission of the outermost loop of the common-mode voltage is always negative feedback. Obviously. Therefore, considering the expansion, if a filter having an odd number of stages of the integration circuit is formed by using an integration circuit as shown in FIG. 2 as a component, the DC feedback can be performed similarly to the embodiment of FIG. This can be achieved with an inexpensive and small-scale circuit that is not required.

Next, a second embodiment of the present invention will be described with reference to the circuit diagram of FIG. This embodiment is also a filter circuit composed of three stages of integration circuits 11 to 13, but is different from the embodiment of FIG.
+ Is removed, and the integrating capacitor of the integrating circuit 11 is separated into capacitors C11 and C12 at the positions of A1 and B1,
The differential signal Vi is applied from the other ends of the capacitors C11 and C12.
The difference is that n is input.

In this way, the DC from the input to the output
The transmission disappears, and it can be easily inferred that the BPF characteristic is exhibited. In the case of input from this position, the zero point of the transfer function exists independently at the zero frequency and double at the infinite frequency, so that the BPF having a steep high-frequency slope as shown in FIG. Characteristics.

Since the in-phase transmission loop is exactly the same as that of the embodiment shown in FIG. 1, a stable self-bias is created by the action of the in-phase negative feedback loop, and the point that a dedicated DC feedback circuit is not required is the same. However, compared with the example of FIG.
The current value of the current source of the first integration circuit may be smaller by the amount of removing the circuit Gm1 +.
If the same assumption as in the previous example that all the transistors have the same shape is made, all the voltages of the outputs Ai (i = 1 to 3) and Bi (i = 1 to 3) of each stage are made equal. In this case, a current value that is half the current source of the integration circuits 12 and 13 is sufficient.

FIG. 4 is a circuit diagram for explaining a third embodiment of the present invention. This embodiment is also a filter circuit composed of a three-stage integrating circuit, but differs from the embodiment of FIG. 3 in that the input position is changed from the output terminal of the integrating circuit 11 to the output terminal of the integrating circuit 12 and the integration is performed. The capacitor C2 is separated at the positions of A2 and B2 to form capacitors C21 and C22, and the configuration of a portion for inputting the differential signal Vin from the other end of the capacitor is different.

When input is made from the positions of A2 and B2 via the capacitors C21 and C22, the zero point of the transfer function exists twice at the zero frequency and independently at the infinite frequency. B whose steep slope on the low frequency side as shown in
It becomes PF characteristics. Since the in-phase transmission loop is exactly the same as that of the embodiment shown in FIG. 3, a stable self-bias is created by the action of the in-phase negative feedback loop, and the point that a dedicated DC feedback circuit is not required is the same.

FIG. 5 is a circuit diagram for explaining a fourth embodiment of the present invention. This embodiment is also a filter circuit constituted by a three-stage integrating circuit, but is different from the embodiment of FIG.
The output terminal 1 is changed to the output terminal of the integrating circuit 13, and the integrating capacitor C3 is separated at the positions A3 and B3 into capacitors C31 and C32, and a differential signal is input from the other end of the capacitor.

When input is made from the positions of A3 and B3 via the capacitors C31 and C32, the zero point of the transfer function exists three times at the zero frequency, so that the third-order HPF as shown in FIG. Characteristics. Since the in-phase transmission loop is exactly the same as that of the embodiment shown in FIG. 3, a stable self-bias is created by the action of the in-phase negative feedback loop, and the point that a dedicated DC feedback circuit is not required is the same.

The filter output of each of the above-described first to fourth embodiments is obtained from the output of the integration circuit 13, but is obtained from the other integration output to obtain a filter circuit having another frequency characteristic. It is also possible to use Thus, the tertiary filter circuit of the present invention can obtain various filter characteristics by changing the input position and the output position of the signal.

Accordingly, it is possible to arbitrarily connect various characteristics of the third-order filter to produce an arbitrary higher-order filter. In that case, the advantage of the present invention of a small and inexpensive filter circuit can be further utilized.

FIG. 7 shows the whole circuit of FIG. 1 written at the element level. This is obtained by replacing the integrating circuit within the dotted line of the circuit of FIG. 1 with the circuit of FIG. 2, and further replacing the current source with a cascode connection of NMOS transistors. This current source supplies the reference current Io by turning it back with a current mirror made of M5 and M6. As described above, the gate of each PMOS transistor is self-biased by the NMOS current value due to the negative feedback operation of the common mode voltage. This voltage depends on the current value as can be seen from equations (1) and (2).

The PMOS transistors in FIG. 7 have the same shape, and the current mirror ratio of the NMOS current source is 1: 1.
And In this case, in each PMOS transistor,
Since the bias current becomes Io / 2, I1 = Io / 2 is substituted into equation (1), and Io = β1 (VGS1−Vth1) 2 (5) Since the DC voltage Vb of the input signal with respect to the power supply is VGS1 when there is no signal, this equation naturally holds for the operating point Vb.

(Equation 2) Becomes Substituting this into equation (4),

(Equation 3) It turns out that. That is, the gm value of each Gm circuit changes in proportion to the square root of the bias current Io. When the current sources are controlled collectively as in the circuit of FIG. 7, each bias current can be changed while keeping their ratio constant. This means that the frequency characteristics of the filter circuit are similarly changed along the frequency axis while the shape of the frequency characteristics is maintained.

In general, in a semiconductor integrated circuit, a characteristic variation of a filter due to a variation in a manufacturing process appears as a similar movement along a frequency axis. This is because the variation of the similarity movement is mainly caused by the absolute value variation of the element, which is large in the semiconductor integrated circuit, and the relative variation of the element which affects the form of the frequency characteristic is very small in the semiconductor. Therefore, the control of the frequency characteristic by the bias current Io is suitable for correcting the shift of the frequency characteristic due to the manufacturing variation of the semiconductor, and it is possible to correct most of the variation.

In the circuit of FIG. 7, the capacitance values of the capacitors C1, C2, and C3 are set to 8 pF, 4 pF, and 2 pF, respectively, and the current values of the bias current source Io are 25 μA and 50 μF.
FIG. 8 shows changes in the LPF characteristics when A, 75 μA, and 100 μA were changed. From this result, it can be seen that the filter characteristic changes in a similar manner along the frequency axis in proportion to the square root of the bias current according to the equation (7). By changing the bias current in this manner, adjustment for correcting manufacturing variations in filter characteristics can be easily performed.

[0047]

As described above, according to the filter circuit of the present invention, a distortion-free filter circuit can be formed without the need for DC feedback by being configured with an odd number of stages of integrating circuits having a fully differential configuration. Therefore, a high-order filter circuit can be realized on a small scale at low cost.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram for explaining a first embodiment of the present invention.

FIG. 2 is a circuit diagram for describing a specific configuration example of the integration circuit in FIG. 1;

FIG. 3 is a circuit configuration diagram for explaining a second embodiment of the present invention.

FIG. 4 is a circuit configuration diagram for explaining a third embodiment of the present invention.

FIG. 5 is a circuit configuration diagram for explaining a fourth embodiment of the present invention.

FIG. 6 is an explanatory diagram for describing frequency characteristics according to each embodiment of the present invention.

FIG. 7 is a circuit diagram in which the circuit configuration of FIG. 1 is configured at an element level.

FIG. 8 is an explanatory diagram for describing adjustment of frequency characteristics of the circuit in FIG. 7;

FIG. 9 is a circuit configuration diagram for describing a conventional example of a biquad circuit having DC feedback.

FIG. 10 is a diagram showing an integration circuit constituting the filter of FIG.
FIG. 3 is a circuit diagram for describing a circuit example realized by an OS process.

[Explanation of symbols]

11 to 13: integrating circuit, Gm1 + to Gm3 +, Gm1-
Gm3--Gm circuit, C1-C3 ... integration capacitors.

Claims (8)

[Claims] 1. An integrated circuit comprising: a transconductance circuit having one or two pairs of differential input terminals and a pair of differential output terminals and constituted by a field effect transistor; and a capacitor connected to the differential output terminal. A filter circuit comprising: a circuit; and combining odd numbers of three or more integrating circuits and connecting them together to form an odd-order fully differential filter. 2. An arbitrary filter characteristic is realized by cascade-connecting a plurality of unit filter circuits each including three integration circuits.
The filter circuit as described. 3. The transconductance circuit according to claim 1,
A pair or two pairs of field effect transistors and a pair of current sources, the sources of the paired field effect transistors are connected to a common constant voltage terminal, and the gate terminal of the pair is an input terminal of the integration circuit. The pair of drain terminals are connected to the pair of current sources, respectively, and this is used as an output terminal pair of the integrating circuit. The capacitor has one end connected to the drain terminal of the pair and the other end connected. A pair of capacitors connected to either a point or the input terminal pair, or a capacitor connected between the drain terminals of the pair, or
2. The filter circuit according to claim 1, comprising a combination of a pair of capacitors and said one capacitor. 4. The frequency characteristic of the filter is proportionally controlled by collectively controlling the current values of all the current sources of the transconductance circuit constituting the filter circuit while maintaining a constant current ratio. The filter circuit according to claim 3, wherein: 5. A source terminal of each of the first and second pair of field effect transistors is connected to a common first reference potential point,
Each of the gate terminals of the first pair of field-effect transistors is a first input terminal pair, and each of the gate terminals of the second pair of field-effect transistors is a second input terminal pair. Each drain terminal of the effect transistor pair is connected to a current source to form an output terminal pair, and between the output terminals of the output terminal pair or between the respective output terminals of the output terminal pair and the second reference potential point. A capacitor is connected to at least one of the first to third integrating circuits, and an output terminal pair of the first integrating circuit is connected to a first input terminal pair of the second integrating circuit. Connecting the output terminal pair of the second integration circuit to the first input terminal pair of the third integration circuit, and connecting the output terminal pair of the third integration circuit to the first to third output terminals. To the second input terminal pair of the integrating circuit A differential input signal is supplied to a first input terminal of the first integration circuit, and a differential output signal is extracted from any one of the output terminal pairs of the first to third integration circuits. A filter circuit characterized by realizing frequency selection characteristics. 6. A first transconductance circuit having a differential output terminal pair and a differential input terminal pair connected to a differential output, the first transconductance circuit including a field effect transistor, and one end of the differential output terminal pair. A first integrating circuit comprising a capacitor having the other end connected to each of the differential inputs; and a differential input terminal pair connected to the differential output terminal pair of the first transconductance circuit. And a third transconductance circuit having a differential input terminal pair connected to the differential output, and a third transconductance circuit composed of a field effect transistor, and a second transconductance circuit composed of a field effect transistor. A capacitor connected between at least one of the output terminals of the differential output terminal pair or between each output terminal of the output terminal pair and the reference potential point. A second transconductance circuit having a differential input terminal pair connected to a differential output terminal pair of the second transconductance circuit, and a fourth transconductance circuit formed of a field effect transistor. A fifth transconductance circuit having a differential input terminal pair connected to the dynamic output and comprising a field effect transistor; and between the output terminals of the differential output terminal pair of the fourth and fifth transconductance circuits or the output A third integrating circuit comprising a capacitor connected to at least one of the output terminals of the terminal pair and a reference potential point. 7. A first transconductance circuit having a differential output terminal pair and a differential input terminal pair connected to a differential output, and comprising a field effect transistor, and a terminal between the differential output terminal pair and A first integrating circuit comprising a capacitor connected to at least one of the output terminal of the pair of output terminals and a reference potential point; and a differential input to a differential output terminal pair of the first transconductance circuit. A second transconductance circuit connected to a pair of terminals and formed of a field effect transistor; a third transconductance circuit connected to a differential input terminal pair to the differential output and formed of a field effect transistor; Each of the differential output terminal pairs of the second and third transconductance circuits is connected to a capacitor having the other end connected to each of the differential inputs. A second integrator circuit, a fourth transconductance circuit having a differential input terminal pair connected to a differential output terminal pair of the second transconductance circuit, and a fourth transconductance circuit constituted by a field effect transistor; A fifth transconductance circuit connected to a differential input terminal pair and configured by a field effect transistor; and a fifth transconductance circuit between the output terminals of the differential output terminal pairs or the output terminal pair of the fourth and fifth transconductance circuits. A filter circuit comprising: a third integration circuit including a capacitor connected to at least one of the output terminals and a reference potential point. 8. A first transconductance circuit having a differential output terminal pair and a differential input terminal pair connected to a differential output, the first transconductance circuit including a field effect transistor, and a terminal between the differential output terminal pair or A first integrating circuit comprising a capacitor connected to at least one of the output terminal of the pair of output terminals and a reference potential point; and a differential input to a differential output terminal pair of the first transconductance circuit. A second transconductance circuit connected to a pair of terminals and configured with a field effect transistor; a third transconductance circuit connected to a differential input terminal pair with the differential output and configured with a field effect transistor; Between the output terminals of the differential output terminal pairs of the second and third transconductance circuits or between the respective output terminals of the output terminal pairs and the reference potential And a second integrating circuit comprising a capacitor connected to at least one of the first and second input terminals; and 4, a fifth transconductance circuit having a differential input terminal pair connected to the differential output and formed of a field effect transistor, and one end connected to the differential of the fourth and fifth transconductance circuits. A filter circuit comprising: a third integration circuit including, for each output terminal pair, a capacitor having the other end connected to each of the differential inputs.