JPH0794978A - Operational amplifier - Google Patents

Operational amplifier

Info

Publication number
JPH0794978A
JPH0794978A JP5232757A JP23275793A JPH0794978A JP H0794978 A JPH0794978 A JP H0794978A JP 5232757 A JP5232757 A JP 5232757A JP 23275793 A JP23275793 A JP 23275793A JP H0794978 A JPH0794978 A JP H0794978A
Authority
JP
Japan
Prior art keywords
terminal
constant current
transistor
current source
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5232757A
Other languages
Japanese (ja)
Other versions
JP3250884B2 (en
Inventor
Katsushi Nakamura
勝史 中村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP23275793A priority Critical patent/JP3250884B2/en
Publication of JPH0794978A publication Critical patent/JPH0794978A/en
Application granted granted Critical
Publication of JP3250884B2 publication Critical patent/JP3250884B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE:To obtain an operational amplifier having high band and high gain, capable of obtaining high output amplitude by low power supply voltage and simplified at its circuit constitution by improving mirror phase compensation in a two-stage type operational amplifier so as to improve a mirror feedback loop band. CONSTITUTION:Analog voltage inputted from an input terminal 1 is converted into a current signal by an input transformer conductance amplifier 10 and the current signal is outputted to a terminal 2. The current signal is allowed to flow into a transistor (TR) M7 whose impedance is lower than that of a constant current source constituted of TRs M3, M16 and converted into a voltage signal by the impedance of the terminal 4, the voltage signal is amplified by a source ground circuit constiuted of a TR M5 and a constant current source 8 and the amplified signal is outputted to an output terminal 5. Phase compensation is executed by feeding back an output signal from a terminal 5 to the terminal 4 through a phase compensating capacitor CC and the TRs M16, M7. Thereby the capacitance of the capacitor CC is equivalently increased on the terminal 4.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、演算増幅器に関し、特
に、例えば、AD変換器、DA変換器、スイッチド・キ
ャパシタ・フィルタ、サンプル・ホ−ルド回路、アクテ
ィブ・フィルタなどの、演算増幅器に高利得、高帯域に
加えて低電源電圧での高出力振幅を要求される用途に適
した、演算増幅器に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to operational amplifiers, and more particularly to operational amplifiers such as AD converters, DA converters, switched capacitor filters, sample-hold circuits, active filters, etc. The present invention relates to an operational amplifier suitable for applications requiring high gain, high band, and high output amplitude at low power supply voltage.

【0002】[0002]

【従来の技術】演算増幅器の構成としては、一般に、1
段の増幅器を有する1段型と、2段の増幅器を縦続する
2段型がある。
2. Description of the Related Art Generally, the structure of an operational amplifier is 1
There are a single-stage type having a two-stage amplifier and a two-stage type in which two-stage amplifiers are cascaded.

【0003】1段構成で高利得が要求される場合、通
常、利得を上げる手段としてカスコ−ド回路を有し、そ
の詳細については、P. R. Gray他著、John Wiley & Son
s 1984年第2版発行、「Analysis and Design of Analo
g Integrated Circuits」に述べられている。この構成
では、高インピ−ダンス端子は出力だけであるため、位
相補償は適当な容量を出力端子に接続することにより達
成される。しかし、カスコ−ド回路のために、増幅器の
出力振幅は大幅に制限されてしまい、特に、低電源電圧
で高出力振幅を達成するのは極めて困難である。
When a high gain is required in a one-stage configuration, a Cascade circuit is usually used as a means for increasing the gain. For details, see PR Gray et al., John Wiley & Son.
s 2nd edition, 1984, "Analysis and Design of Analo
g Integrated Circuits ”. In this configuration, the high impedance terminal is the only output, so phase compensation is achieved by connecting an appropriate capacitance to the output terminal. However, the output amplitude of the amplifier is significantly limited due to the cascode circuit, and it is extremely difficult to achieve a high output amplitude especially at a low power supply voltage.

【0004】2段型構成で高利得が要求される場合、そ
れぞれの増幅段には、通常、前記1段型構成ほどの利得
は必要ないので、利得を上げるためのカスコ−ド回路は
必要とされない。したがって、低電源電圧で高出力振幅
が可能になる。しかし、2段型構成の場合、二つの高イ
ンピ−ダンス端子(第2段の入力と第2段の出力)が存
在する結果、極が二つ存在するので、ミラ−位相補償を
施して、極分離を行なわなければならない。その詳細に
ついては、同じく前掲文献に述べられている。
When a high gain is required in the two-stage type configuration, each amplification stage usually does not require the gain as much as the one-stage type configuration, and therefore a cascade circuit for increasing the gain is required. Not done. Therefore, a high output amplitude is possible with a low power supply voltage. However, in the case of the two-stage configuration, there are two poles as a result of the presence of the two high impedance terminals (the second stage input and the second stage output). Pole separation must be done. The details are also described in the above-mentioned literature.

【0005】図3に、上記ミラ−位相補償を施した2段
型演算増幅器の構成の概要を示す。ミラ−位相補償は、
第2段の反転増幅器の出力を、容量を介して、該増幅器
の入力へ帰還することによって行なわれる。この帰還容
量は、第2段増幅器の利得に起因するミラー効果によ
り、第1段増幅器の出力端子に、等価的に増大されて現
れ、それにより極分離が実現される。また、抵抗を帰還
容量と直列に接続することにより、ゼロを除去すること
ができる。
FIG. 3 shows an outline of the configuration of the two-stage operational amplifier which has been subjected to the mirror phase compensation. Mira-phase compensation is
This is done by feeding back the output of the second stage inverting amplifier via a capacitor to the input of the amplifier. This feedback capacitance appears equivalently increased at the output terminal of the first-stage amplifier due to the Miller effect caused by the gain of the second-stage amplifier, thereby realizing pole separation. In addition, the zero can be removed by connecting the resistor in series with the feedback capacitance.

【0006】[0006]

【発明が解決しようとする課題】前述したように、カス
コ−ド回路を有する1段型演算増幅器は、位相補償が比
較的に簡単であり、高利得、高帯域を要求する用途に適
しているが、その反面、低電源電圧での高出力振幅は達
成し難く、他方、従来の2段型演算増幅器は、出力振幅
を制限するカスコ−ド回路を必要としないので、低電源
電圧でも高出力振幅を達成することが可能であるが、ミ
ラ−位相補償を施さなければならない。ミラー位相補償
の難点は、第2の極が、比較的大きい帰還容量と第2段
出力の負荷容量により、低い周波数のところに制限され
てしまい、その結果、帯域を1段型構成で可能なほどに
は伸ばせない点にある。
As described above, the one-stage operational amplifier having the cascade circuit is relatively simple in phase compensation and is suitable for applications requiring high gain and high bandwidth. However, on the other hand, it is difficult to achieve a high output amplitude at a low power supply voltage. On the other hand, the conventional two-stage operational amplifier does not need a cascade circuit for limiting the output amplitude, so that a high output power is obtained even at a low power supply voltage. It is possible to achieve amplitude, but Miller-phase compensation must be applied. The drawback of the mirror phase compensation is that the second pole is limited to a low frequency by the relatively large feedback capacitance and the load capacitance of the second stage output, and as a result, the band is possible with the one-stage configuration. The point is that it cannot be stretched as much.

【0007】本発明の目的は、上記のような従来の1段
型構成と2段型構成の欠点がなく、それらの長所を併せ
持ち、すなわち、高帯域、高利得で、かつ、低電源電圧
で高出力振幅が得られ、しかも、回路構成が簡単な演算
増幅器を、提供することにある。
The object of the present invention is that it does not have the drawbacks of the conventional one-stage type configuration and the two-stage type configuration as described above, and has the advantages of both, namely, high bandwidth, high gain, and low power supply voltage. It is an object of the present invention to provide an operational amplifier which can obtain a high output amplitude and has a simple circuit configuration.

【0008】[0008]

【課題を解決するための手段】本発明は、2段型の演算
増幅器におけるミラ−位相補償を改善して、ミラ−帰還
のル−プ帯域を高めることにより、前記の目的を達成す
るものである。すなわち、本発明の演算増幅器は、トラ
ンスコンダクタンス・アンプと、前記トランスコンダク
タンス・アンプの出力端子に少なくとも第1のトランジ
スタを介して接続された第1の定電流源と、前記出力端
子に少なくとも第2のトランジスタを介して接続された
第2の定電流源とを有する増幅回路、前記第2のトラン
ジスタと第2の定電流源との接続点に入力端子が接続さ
れた出力段増幅回路、及び前記第1のトランジスタと第
1の定電流源との接続点と前記出力段増幅回路の出力端
子の間に接続された容量素子を備える。
SUMMARY OF THE INVENTION The present invention achieves the above object by improving the mirror phase compensation in a two-stage operational amplifier and increasing the loop band of the mirror feedback. is there. That is, the operational amplifier of the present invention includes a transconductance amplifier, a first constant current source connected to an output terminal of the transconductance amplifier through at least a first transistor, and at least a second terminal connected to the output terminal. An amplifier circuit having a second constant current source connected via a transistor, an output stage amplifier circuit having an input terminal connected to a connection point between the second transistor and the second constant current source, and A capacitive element is connected between a connection point between the first transistor and the first constant current source and an output terminal of the output stage amplifier circuit.

【0009】トランスコンダクタンス・アンプを入出力
完全差動型とし、その1対の出力端子のそれぞれを前記
と同様な回路に接続すれば、入出力完全差動型の演算増
幅器が得られる。
If the transconductance amplifier is of the input / output fully differential type and each of the pair of output terminals is connected to a circuit similar to the above, an input / output fully differential type operational amplifier can be obtained.

【0010】[0010]

【作用】本発明に係る演算増幅器においては、ミラ−位
相補償のル−プ帯域が、前記第1のトランジスタから第
2のトランジスタまでの利得の分だけ高くなるので、第
2の極周波数がこの利得の分だけ高くなり、したがっ
て、安定性の得られる周波数帯域がそれだけ高くなる。
こうして、従来の2段型演算増幅器の欠点であった帶域
の制限が大幅に緩和されるので、前掲目的が達成され
る。
In the operational amplifier according to the present invention, the loop band of the mirror phase compensation is increased by the gain from the first transistor to the second transistor, so that the second pole frequency is The gain is higher, and thus the frequency band in which stability is obtained is higher.
In this way, the limitation on the area, which has been a drawback of the conventional two-stage operational amplifier, is greatly relaxed, and the above-mentioned object is achieved.

【0011】[0011]

【実施例】以下、本発明の一実施例を、図面を参照しな
がら詳細に説明する。図1は、本発明による演算増幅器
の一実施例を示す回路図であり、それは、CMOS加工
技術を用いて実現しうる。図において、M3、M7及び
M16はPMOSトランジスタ、M5はNMOSトラン
ジスタ、1は入力端子、2〜4は増幅器の内部の端子、
5は出力端子、6(VDD)は電圧源端子、7はグウラ
ンド端子、8及び9は定電流源、10は入力トランスコ
ンダクタンス・アンプ、CCは位相補償用容量、CLは
出力端子における負荷容量、VB1、VB2及びVB3
はバイアス電源を、それぞれ表わす。バイアス電源VB
1、VB2及びVB3は、それぞれトランジスタM3、
M16及びM7を、飽和領域にバイアスする。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a circuit diagram showing an embodiment of an operational amplifier according to the present invention, which can be realized by using CMOS processing technology. In the figure, M3, M7 and M16 are PMOS transistors, M5 is an NMOS transistor, 1 is an input terminal, 2 to 4 are internal terminals of the amplifier,
5 is an output terminal, 6 (VDD) is a voltage source terminal, 7 is a Guland terminal, 8 and 9 are constant current sources, 10 is an input transconductance amplifier, CC is a phase compensation capacitance, CL is a load capacitance at the output terminal, VB1, VB2 and VB3
Denote bias power supplies, respectively. Bias power supply VB
1, VB2 and VB3 are transistors M3,
Bias M16 and M7 in the saturation region.

【0012】次に、この演算増幅器の動作を説明する。
入力端子1から入力されたアナログ電圧は、入力トラン
スコンダクタンス・アンプ10により電流信号に変換さ
れ、端子2に出力される。この電流信号は、トランジス
タM3及びM16で構成される定電流源に比べてインピ
ーダンスが低いトランジスタM7に流れ、端子4におけ
るインピ−ダンスにより電圧信号に変換され、そして、
トランジスタM5と定電流源8で構成されるソ−ス接地
回路により増幅されて、出力端子5に出力される。
Next, the operation of this operational amplifier will be described.
The analog voltage input from the input terminal 1 is converted into a current signal by the input transconductance amplifier 10 and output to the terminal 2. This current signal flows through the transistor M7, which has a lower impedance than the constant current source composed of the transistors M3 and M16, is converted into a voltage signal by the impedance at the terminal 4, and
The signal is amplified by the source ground circuit composed of the transistor M5 and the constant current source 8 and output to the output terminal 5.

【0013】この増幅器は二つの増幅段から構成されて
いるため、安定性を得るには位相補償を行なう必要があ
る。従来の位相補償は、端子5と4の間に容量・抵抗回
路を設けたものに相当する。本実施例における位相補償
は、端子5の出力信号を、位相補償用容量CCとトラン
ジスタM16及びM7を介して、端子4に帰還すること
によって行なわれる。したがって、本実施例における位
相補償用容量CCは、トランジスタM5と定電流源8で
構成されるソ−ス接地回路の利得により、端子4におい
て等価的に増大される。その結果、増幅器の第1と第2
の極は極分離されて、安定な周波数特性が得られる。こ
の位相補償では、従来のミラー位相補償と異なり、端子
4から出力端子5へフィ-ドフォワ-ド・パスがないた
め、ゼロはできず、したがって、帰還路に抵抗を挿入す
る必要はない。
Since this amplifier is composed of two amplification stages, it is necessary to perform phase compensation in order to obtain stability. The conventional phase compensation corresponds to the one in which a capacitance / resistance circuit is provided between the terminals 5 and 4. The phase compensation in the present embodiment is performed by feeding back the output signal of the terminal 5 to the terminal 4 via the phase compensating capacitor CC and the transistors M16 and M7. Therefore, the phase compensating capacitor CC in this embodiment is equivalently increased at the terminal 4 by the gain of the source ground circuit composed of the transistor M5 and the constant current source 8. As a result, the first and second amplifiers
The poles of are separated, and stable frequency characteristics are obtained. In this phase compensation, unlike the conventional mirror phase compensation, since there is no feedforward path from the terminal 4 to the output terminal 5, zero cannot be made, and therefore, it is not necessary to insert a resistor in the feedback path.

【0014】上記実施例の位相補償では、ミラ−帰還の
ル−プ帯域が、従来の回路と比較して、端子3から端子
4までの電圧利得、すなわち、トランジスタM16及び
M7と定電流源9で構成されるゲ−ト接地回路の利得の
分だけ、高くなり、したがって、第二の極周波数が、従
来の回路におけるよりも、上記ゲ−ト接地回路の利得の
分だけ高くなる。すなわち、安定性の得られる周波数帯
域が、従来の回路よりも、上記ゲ−ト接地回路の利得の
分だけ高くなるのである。
In the phase compensation of the above embodiment, the loop band of the mirror feedback is compared with the conventional circuit, and the voltage gain from the terminal 3 to the terminal 4, that is, the transistors M16 and M7 and the constant current source 9 are provided. And the second pole frequency becomes higher than that in the conventional circuit by the gain of the gate ground circuit. That is, the frequency band in which the stability is obtained is higher than that of the conventional circuit by the gain of the gate ground circuit.

【0015】図2は、本発明の第2の実施例を示し、こ
れは、図1に示されたのと同じ位相補償回路を有する入
出力完全差動型の演算増幅器である。M1、M2、M
5、M8、M9、M12〜M15及びM18はNMOS
トランジスタ、M3、M4、M6、M7、M10、M1
1、M16及びM17はPMOSトランジスタ、CC1
及びCC2は位相補償用容量、VIN+及びVIN−は
入力端子対、VO+及びVO−は出力端子対、VDD及
びVSSは電源端子、VCF1、VCF2、VBN1、
VBN2、及びVBP1〜VBP3はバイアス電源端子
を、それぞれ表わす。トランジスタM1、M2、M18
及びM13は、差動型の入力トランスコンダクタンス・
アンプを構成する。
FIG. 2 shows a second embodiment of the present invention, which is an input / output fully differential type operational amplifier having the same phase compensation circuit as shown in FIG. M1, M2, M
5, M8, M9, M12 to M15 and M18 are NMOS
Transistor, M3, M4, M6, M7, M10, M1
1, M16 and M17 are PMOS transistors, CC1
And CC2 are phase compensation capacitors, VIN + and VIN− are input terminal pairs, VO + and VO− are output terminal pairs, VDD and VSS are power supply terminals, VCF1, VCF2, VBN1,
VBN2 and VBP1 to VBP3 represent bias power supply terminals, respectively. Transistors M1, M2, M18
And M13 are differential input transconductance
Configure an amplifier.

【0016】トランジスタM3、M16、M7及びM5
は、図1で同じ符号を付されたトランジスタに対応し、
トランジスタM6は同じく定電流源8に対応し、トラン
ジスタM8及びM14は同じく定電流源9に対応する。
これと同等な回路が、トランジスタM4、M17、M1
1、M12、M15、M10及びM9により構成されて
いる。上記のように構成された本実施例の動作は、第1
の実施例の動作から容易に類推できるので、説明を省略
する。
Transistors M3, M16, M7 and M5
Corresponds to the transistor with the same reference numeral in FIG.
The transistor M6 also corresponds to the constant current source 8, and the transistors M8 and M14 also correspond to the constant current source 9.
A circuit equivalent to this is the transistor M4, M17, M1.
1, M12, M15, M10 and M9. The operation of the present embodiment configured as described above is
Since it can be easily inferred from the operation of the above embodiment, the description thereof will be omitted.

【0017】図4は、本発明による演算増幅器の周波数
特性をコンピュータ・シミュレーションにより求めた結
果を示す。□印を結ぶグラフは利得を表わし、○印を結
ぶグラフは位相を表わす。この図から明らかなように、
第2の極は約200MHzで生じており、これは、従来の
2段型演算増幅器の第2の極が約数十MHzで生じるのと
比較して、帯域が大幅に拡張されたことを示している。
FIG. 4 shows results obtained by computer simulation of frequency characteristics of the operational amplifier according to the present invention. The graph connecting the □ marks represents the gain, and the graph connecting the ○ marks represents the phase. As you can see from this figure,
The second pole occurs at about 200 MHz, which indicates that the band has been extended significantly compared to the second pole of a conventional two-stage operational amplifier at about tens of MHz. ing.

【0018】なお、上記各実施例は本発明の一例を示し
たものであり、本発明はこれらに限定されるものでない
ことは言うまでもない。例えば、上記実施例はFETを
用いて構成されているが、他の素子も用いることができ
るし、また、上記実施例はCMOS加工技術による回路
であるが、他の加工技術、例えばBiCMOS加工技術
による回路でもできる。回路構成においても、種々の変
形が可能であり、例えば、図1において、トランジスタ
M16と端子3の間、及び/又はトランジスタM7と端
子4の間に、更に別のトランジスタが挿入されてもよ
い。
It is needless to say that the above-mentioned embodiments are examples of the present invention, and the present invention is not limited to these. For example, although the above-mentioned embodiment is configured by using the FET, other elements can be used, and the above-mentioned embodiment is a circuit by the CMOS processing technology, but other processing technology, for example, BiCMOS processing technology. You can also use the circuit by. Various modifications are possible in the circuit configuration as well, and for example, in FIG. 1, another transistor may be inserted between the transistor M16 and the terminal 3 and / or between the transistor M7 and the terminal 4.

【0019】[0019]

【発明の効果】以上、詳細に説明したように、本発明に
よれば、2段型の演算増幅器に必要とされるミラ−位相
補償のル−プ帯域を拡張することにより、安定な周波数
帯域を広げて、高帯域、高利得で、かつ、低電源電圧で
高出力振幅が得られる演算増幅器を、回路構成をさほど
複雑化せずに実現できるという、顕著な効果を奏するも
のである。
As described above in detail, according to the present invention, a stable frequency band can be obtained by expanding the loop band of the mirror phase compensation required for the two-stage operational amplifier. It is possible to realize an operational amplifier which can obtain a high output amplitude with a wide band, a high gain, and a low power supply voltage without considerably complicating the circuit configuration, which is a remarkable effect.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第一の実施例としての演算増幅器を示
す回路図。
FIG. 1 is a circuit diagram showing an operational amplifier as a first embodiment of the present invention.

【図2】本発明の第二の実施例としての完全差動型演算
増幅器を示す回路図。
FIG. 2 is a circuit diagram showing a fully differential operational amplifier according to a second embodiment of the present invention.

【図3】従来のミラ−位相補償を用いた2段型演算増幅
器を示す回路図。
FIG. 3 is a circuit diagram showing a conventional two-stage operational amplifier using a mirror phase compensation.

【図4】本発明による演算増幅器の周波数特性を示すグ
ラフ。
FIG. 4 is a graph showing frequency characteristics of an operational amplifier according to the present invention.

【符号の説明】[Explanation of symbols]

4:第1段増幅回路の出力端子 5:第2段増幅回路としてのトランジスタ 10:入力トランスコンダクタンス・アンプ CC:位相補償用容量 M16、M7:位相補償用容量と第1段増幅回路の出力
端子の間に設けられたトランジスタ
4: Output terminal of first-stage amplifier circuit 5: Transistor as second-stage amplifier circuit 10: Input transconductance amplifier CC: Phase compensation capacitance M16, M7: Phase compensation capacitance and output terminal of first-stage amplification circuit Transistor provided between

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】トランスコンダクタンス・アンプと、前記
トランスコンダクタンス・アンプの出力端子に少なくと
も第1のトランジスタを介して接続された第1の定電流
源と、前記出力端子に少なくとも第2のトランジスタを
介して接続された第2の定電流源とを有する増幅回路、
前記第2のトランジスタと第2の定電流源との接続点に
入力端子が接続された出力段増幅回路、及び前記第1の
トランジスタと第1の定電流源との接続点と前記出力段
増幅回路の出力端子の間に接続された容量素子を備える
ことを特徴とする演算増幅器。
1. A transconductance amplifier, a first constant current source connected to an output terminal of the transconductance amplifier via at least a first transistor, and an output terminal via at least a second transistor. An amplifier circuit having a second constant current source connected in parallel,
An output stage amplification circuit having an input terminal connected to a connection point between the second transistor and a second constant current source, and a connection point between the first transistor and the first constant current source and the output stage amplification An operational amplifier comprising a capacitive element connected between output terminals of a circuit.
【請求項2】第1及び第2の入力端子と第1及び第2の
出力端子を有する入出力完全差動型のトランスコンダク
タンス・アンプと、前記第1の出力端子に少なくとも第
1のトランジスタを介して接続された第1の定電流源
と、前記第1の出力端子に少なくとも第2のトランジス
タを介して接続された第2の定電流源と、前記第2の出
力端子に少なくとも第3のトランジスタを介して接続さ
れた第3の定電流源と、前記第2の出力端子に少なくと
も第4のトランジスタを介して接続された第4の定電流
源とを有する増幅回路、前記第2のトランジスタと第2
の定電流源との接続点に入力端子が接続された第1の出
力段増幅回路、前記第4のトランジスタと第4の定電流
源との接続点に入力端子が接続された第2の出力段増幅
回路、前記第1のトランジスタと第1の定電流源との接
続点と前記第1の出力段増幅回路の出力端子の間に接続
された第1の容量素子、及び前記第3のトランジスタと
第3の定電流源との接続点と前記第2の出力段増幅回路
の出力端子の間に接続された第2の容量素子を備えるこ
とを特徴とする演算増幅器。
2. An input / output fully differential transconductance amplifier having first and second input terminals and first and second output terminals, and at least a first transistor at the first output terminal. A first constant current source connected to the first output terminal, a second constant current source connected to the first output terminal via at least a second transistor, and a second constant current source connected to the second output terminal at least a third An amplifier circuit having a third constant current source connected via a transistor and a fourth constant current source connected to the second output terminal via at least a fourth transistor, the second transistor And the second
A first output stage amplifier circuit having an input terminal connected to a connection point with the constant current source, and a second output having an input terminal connected to a connection point between the fourth transistor and the fourth constant current source Stage amplifier circuit, a first capacitive element connected between a connection point of the first transistor and a first constant current source and an output terminal of the first output stage amplifier circuit, and the third transistor And a third constant current source, and a second capacitance element connected between the connection point of the third constant current source and the output terminal of the second output stage amplifier circuit.
JP23275793A 1993-09-20 1993-09-20 Operational amplifier Expired - Lifetime JP3250884B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23275793A JP3250884B2 (en) 1993-09-20 1993-09-20 Operational amplifier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23275793A JP3250884B2 (en) 1993-09-20 1993-09-20 Operational amplifier

Publications (2)

Publication Number Publication Date
JPH0794978A true JPH0794978A (en) 1995-04-07
JP3250884B2 JP3250884B2 (en) 2002-01-28

Family

ID=16944282

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23275793A Expired - Lifetime JP3250884B2 (en) 1993-09-20 1993-09-20 Operational amplifier

Country Status (1)

Country Link
JP (1) JP3250884B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2815196A1 (en) * 2000-10-06 2002-04-12 St Microelectronics Sa Integrated error amplifier comprising operational amplifier with active load and resistive-capacitive network, for provision of analogue control signal
JP2010056860A (en) * 2008-08-28 2010-03-11 Icom Inc Low noise amplifier
CN114189217A (en) * 2021-12-17 2022-03-15 中船重工安谱(湖北)仪器有限公司 High-gain pulse current amplifying circuit

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2815196A1 (en) * 2000-10-06 2002-04-12 St Microelectronics Sa Integrated error amplifier comprising operational amplifier with active load and resistive-capacitive network, for provision of analogue control signal
EP1199798A2 (en) * 2000-10-06 2002-04-24 STMicroelectronics S.A. Integrated error amplifier
US6650179B2 (en) 2000-10-06 2003-11-18 Stmicroelectronics S.A. Integrated error amplifier
EP1199798A3 (en) * 2000-10-06 2004-06-23 STMicroelectronics S.A. Integrated error amplifier
JP2010056860A (en) * 2008-08-28 2010-03-11 Icom Inc Low noise amplifier
CN114189217A (en) * 2021-12-17 2022-03-15 中船重工安谱(湖北)仪器有限公司 High-gain pulse current amplifying circuit

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