JPH1012561A - Semiconductor treating apparatus - Google Patents
Semiconductor treating apparatusInfo
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- JPH1012561A JPH1012561A JP16269396A JP16269396A JPH1012561A JP H1012561 A JPH1012561 A JP H1012561A JP 16269396 A JP16269396 A JP 16269396A JP 16269396 A JP16269396 A JP 16269396A JP H1012561 A JPH1012561 A JP H1012561A
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- Prior art keywords
- wafer
- reactor
- reaction furnace
- processing
- wafers
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- Chemical Vapour Deposition (AREA)
- Drying Of Semiconductors (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は半導体処理装置に関
する。[0001] The present invention relates to a semiconductor processing apparatus.
【0002】[0002]
【従来の技術】現在、酸化,アニール,熱CVD装置な
どの半導体熱処理プロセスでは、一度に複数のウエハを
処理するバッチ式装置(縦型拡散装置,縦型CVD装
置)が主として使用されている。しかし、半導体素子の
高集積化に対応して、数nm程度の非常に薄い酸化膜や
浅い拡散層の形成,自然酸化膜の防止技術が必須になっ
ており、これらの要求に対応するためには数分以下の短
時間処理に適し、クラスタユニット化やウエハの大口径
化への対応も容易な一度に一枚のウエハを処理する枚葉
式装置あるいは一度に数枚程度のウエハを処理する疑似
枚葉式装置が有利になっている。また、バッチ式装置と
枚葉式の他の装置(エッチング装置やスパッタ装置な
ど)とが混在したラインは、素子を短時間で製作するこ
とが困難で、枚葉式の熱処理装置が不可欠になってきて
いる。2. Description of the Related Art At present, in a semiconductor heat treatment process such as oxidation, annealing, and thermal CVD, a batch type apparatus (vertical diffusion apparatus, vertical CVD apparatus) for processing a plurality of wafers at once is mainly used. However, in order to cope with high integration of semiconductor devices, formation of very thin oxide film or shallow diffusion layer of about several nm and prevention technology of natural oxide film are indispensable. Is suitable for short-time processing of several minutes or less, and can easily deal with cluster units and large-diameter wafers. It processes one wafer at a time or processes several wafers at a time. Pseudo-single-wafer devices are advantageous. Also, in a line in which a batch-type apparatus and other single-wafer-type apparatuses (such as an etching apparatus and a sputtering apparatus) are mixed, it is difficult to manufacture an element in a short time, and a single-wafer-type heat treatment apparatus is indispensable. Is coming.
【0003】枚葉式熱処理装置ではウエハに施す処理を
ウエハ全面にわたって均一にするための一例としてウエ
ハを回転させるという手段がある。例えば電子材料19
95年3月号pp.67−70にあるように、支持台に
載せたウエハを支持台ごと回転させるものである。これ
は、ウエハを回転させずにガスは装置に対して平均的に
ある一方向に流していれば流れの上流と下流とでウエハ
の処理される程度が異なるが、ウエハを回転させること
によって、上流と下流の差を打ち消し、ウエハに施す処
理を均一にするというものである。In a single-wafer heat treatment apparatus, there is a means for rotating a wafer as an example to make the processing performed on the wafer uniform over the entire surface of the wafer. For example, electronic material 19
March 1995 pp. As shown in 67-70, the wafer placed on the support is rotated together with the support. This is because if the gas is flowing in one direction on average to the apparatus without rotating the wafer, the degree of processing of the wafer is different between upstream and downstream of the flow, but by rotating the wafer, The difference between the upstream and the downstream is canceled out, and the processing performed on the wafer is made uniform.
【0004】[0004]
【発明が解決しようとする課題】反応炉内に回転機構な
どの駆動部を有する半導体処理装置は、駆動部のない装
置に比べ発塵は多い。ところがウエハに施す処理のウエ
ハ全面に対する均一性という観点からは、ウエハを回転
させるという方法はその効果が顕著である。また、均一
性を得るためにウエハの回転機構を設けると、一度に処
理できるウエハの枚数が一枚に限定されやすく、一定時
間に処理できる枚数が低下する。A semiconductor processing apparatus having a drive unit such as a rotating mechanism in a reaction furnace generates more dust than a device without a drive unit. However, from the viewpoint of the uniformity of the processing performed on the wafer over the entire surface of the wafer, the method of rotating the wafer has a remarkable effect. Further, if a wafer rotation mechanism is provided to obtain uniformity, the number of wafers that can be processed at one time tends to be limited to one, and the number of wafers that can be processed in a given time is reduced.
【0005】回転機構を設けると一度に処理できるウエ
ハが一枚に限定されやすくなるのは以下のような理由に
よる。ここでは半導体素子を短時間で製造するという目
的で達成することを念頭に置いているので、処理時間の
かかるバッチ式の装置は対象としない。一回の処理が短
時間の枚葉式装置で、ウエハを所定の温度に加熱するに
はランプが用いられることが多い。ランプを用いた加熱
では、反応炉は石英などの透明材料からなり、ランプの
光を効率よくウエハまで到達させることが大切である。
そのため、ランプによって加熱されるのはウエハ及びウ
エハの支持台のみであり、透明な材料からなる反応炉の
壁はほとんど加熱されない。支持台上のウエハは上部か
ら加熱され、下部には回転機構があるとする。ここで二
枚以上のウエハを積層するようにおくと、一枚のウエハ
によって他のウエハにランプの光が到達しなくなり、ラ
ンプによって均一な加熱が不可能となる。また、別な加
熱方法として、反応炉全体を加熱するという方法もあ
る。これは、反応炉を断熱材で覆い、熱の散逸をできる
だけなくした状態で、反応炉を抵抗線に電流を流すこと
などによって加熱するものである。ところが、この方式
でも複数枚のウエハを同時に処理し、さらにそれらを回
転させようとすると、断熱材の一部に切り欠きが入り、
そこから熱が散逸するので、ウエハ全面を均一に加熱す
るのが困難になる。従って、一度に複数枚のウエハを処
理するにはウエハの回転をなくす必要がある。The reason that the provision of the rotation mechanism tends to limit the number of wafers that can be processed at one time to one wafer is as follows. Here, since it is intended to achieve the purpose of manufacturing a semiconductor element in a short time, a batch-type apparatus requiring a long processing time is not targeted. In a single-wafer processing apparatus in which one process is performed in a short time, a lamp is often used to heat a wafer to a predetermined temperature. In heating using a lamp, it is important that the reaction furnace is made of a transparent material such as quartz and that the light of the lamp efficiently reaches the wafer.
Therefore, only the wafer and the wafer support are heated by the lamp, and the walls of the reactor made of a transparent material are hardly heated. It is assumed that the wafer on the support is heated from the upper part and the lower part has a rotating mechanism. Here, if two or more wafers are stacked, the light of the lamp does not reach one wafer by one wafer, and uniform heating by the lamp becomes impossible. As another heating method, there is a method of heating the entire reaction furnace. In this method, the reaction furnace is covered with a heat insulating material so that the heat is dissipated as little as possible, and the reaction furnace is heated by flowing an electric current through a resistance wire. However, even with this method, when processing a plurality of wafers at the same time and trying to rotate them further, a part of the heat insulating material is cut out,
Since heat is dissipated therefrom, it becomes difficult to uniformly heat the entire surface of the wafer. Therefore, in order to process a plurality of wafers at once, it is necessary to eliminate the rotation of the wafers.
【0006】本発明の目的は主として枚葉式装置でウエ
ハに施す処理がウエハ全面にわたって均一で、発塵が少
なく、かつ一定時間に処理数枚数の多い半導体処理装
置,半導体処理方法を提供することにある。An object of the present invention is to provide a semiconductor processing apparatus and a semiconductor processing method in which processing performed on a wafer by a single-wafer apparatus is uniform over the entire surface of the wafer, generates less dust, and increases the number of processed wafers in a given time. It is in.
【0007】[0007]
【課題を解決するための手段】上記の課題は、ウエハを
反応炉で処理したのちに、ウエハを取り出し、別の反応
炉に挿入し、そこで前記処理とほぼ同様の処理を施すこ
とによって解決できる。このとき最初の処理に用いた反
応炉内の平均的なガスの流れの方向に対するウエハの向
きと次の処理に用いた反応炉内の平均的なガスの流れの
方向に対するウエハの向きが異なっていることが重要で
ある。また、ウエハを反応炉で処理したのちに、ウエハ
を取り出し、そこでウエハの向きを変え、もとの反応炉
に挿入し、そこで前記処理とほぼ同様の処理を施すこと
によっても解決できる。また、反応炉内にウエハの回転
機構を設けないので一度に複数枚のウエハを処理するこ
とも可能で、一定時間で処理できるウエハの枚数を増加
させることができる。The above object can be attained by processing a wafer in a reactor, removing the wafer, inserting the wafer into another reactor, and performing substantially the same processing as described above. . At this time, the direction of the wafer with respect to the average gas flow direction in the reactor used for the first process and the direction of the wafer with respect to the average gas flow direction in the reactor used for the next process are different. Is important. Alternatively, the problem can be solved by processing the wafer in a reaction furnace, taking out the wafer, changing the orientation of the wafer there, inserting the wafer into the original reaction furnace, and performing substantially the same processing as described above. Further, since a wafer rotation mechanism is not provided in the reaction furnace, a plurality of wafers can be processed at one time, and the number of wafers that can be processed in a given time can be increased.
【0008】[0008]
【発明の実施の形態】以下、本発明の実施例を図を用い
て説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.
【0009】図1は本発明の一実施例である。ウエハ1
はカセット単位でカセット室2に入れられ、カセット室
から反応炉3あるいは反応炉4で処理できる枚数に応じ
てウエハ搬送装置5によって搬送され、反応炉3に挿入
される。ウエハ1の向きは、オリフラがウエハ搬送装置
5から最も遠くなるようにする。反応炉3では、圧力を
所定の圧力に保ち、またウエハ1を所定の温度に加熱
し、ウエハ搬送装置5に近い方から遠い方に向けて反応
性のガスを所定量流すことによって、ウエハ1に処理を
施す。この処理を終えた後に、ウエハ搬送装置5によっ
てウエハ1を反応炉3から取り出し、反応炉4に挿入す
る。ウエハ1の向きは、オリフラがウエハ搬送装置5か
ら最も近くなるようにする。反応炉4でも反応炉3での
圧力,温度条件にほぼ等しい条件を保ったまま、ウエハ
搬送装置5に近い方から遠い方に向けて反応性のガスを
反応炉3の流量とほぼ同流量流すことによって、再びウ
エハ1に処理を施す。ウエハ1に対する処理を終え、ウ
エハ1を本装置から取り出す前には、ウエハ1を冷却室
6あるいは7に入れて、その温度を適当に下げてやる必
要がある場合もある。冷却室はウエハの処理速度に応じ
て容量や個数を決定すればよく、冷却室の個数と反応炉
の個数とは必ずしも一致していなくてもよい。FIG. 1 shows an embodiment of the present invention. Wafer 1
Are transferred into the cassette chamber 2 in cassette units, are transferred from the cassette chamber by the wafer transfer device 5 according to the number of sheets that can be processed in the reaction furnace 3 or the reaction furnace 4, and are inserted into the reaction furnace 3. The orientation of the wafer 1 is set so that the orientation flat is farthest from the wafer transfer device 5. In the reaction furnace 3, the wafer 1 is maintained at a predetermined pressure, the wafer 1 is heated to a predetermined temperature, and a predetermined amount of reactive gas is flowed from a portion closer to the wafer transfer device 5 to a portion farther from the wafer transfer device 5. Process. After finishing this process, the wafer 1 is taken out of the reaction furnace 3 by the wafer transfer device 5 and inserted into the reaction furnace 4. The orientation of the wafer 1 is set so that the orientation flat is closest to the wafer transfer device 5. In the reaction furnace 4, a reactive gas flows at a flow rate substantially the same as the flow rate of the reaction furnace 3 from a position closer to the wafer transfer device 5 to a position farther from the wafer transfer device 5 while maintaining conditions substantially equal to pressure and temperature conditions in the reaction furnace 3. Thus, the wafer 1 is processed again. Before the processing of the wafer 1 is completed and before the wafer 1 is taken out of the present apparatus, it may be necessary to put the wafer 1 in the cooling chamber 6 or 7 and to lower its temperature appropriately. The capacity and number of cooling chambers may be determined according to the processing speed of the wafer, and the number of cooling chambers and the number of reaction furnaces do not necessarily have to match.
【0010】ウエハ1への処理の均一性に関しては、以
下のように考えられる。ウエハ1のオリフラは反応炉3
での処理ではウエハ1の最も下流に位置しているのに対
し、反応炉4での処理ではウエハ1の最も上流に位置し
ていることになり、実質的に上流と下流の影響が相殺さ
れることになる。上記処理をCVDと考え、ウエハ上の
CVD膜の成長速度g(x)が原料ガスの濃度C(x)
に比例するとき、ウエハ上のCVD膜の成長速度の均一
性qは以下のように考えられる。ここでウエハ1は完全
な円であるとし、流れは一次元で近似できるとし、流れ
に平行な方向(x方向)の成長速度の分布のみを考慮す
ることにする。xの原点はウエハ1の最も上流の位置と
する。平均流速をuとすると時刻tはt=x/uと変換
でき、g(x)∝C(x)=C(0)exp(−kx/u)
である。kは単位時間当たりに原料が消滅する速度であ
る。均一性qをq=(gの最大値−gの最小値)/(g
の最大値+gの最小値)で定義すると、単に反応炉3で
のみ処理したときの均一性q1 はThe uniformity of processing on the wafer 1 is considered as follows. The orientation flat of wafer 1 is
Is located at the most downstream side of the wafer 1 in the processing in the above, whereas the processing in the reaction furnace 4 is located at the most upstream side of the wafer 1, and the effects of the upstream and the downstream are substantially offset. Will be. Considering the above process as CVD, the growth rate g (x) of the CVD film on the wafer is determined by the concentration C (x) of the source gas.
When it is proportional to, the uniformity q of the growth rate of the CVD film on the wafer can be considered as follows. Here, it is assumed that the wafer 1 is a perfect circle, the flow can be approximated in one dimension, and only the growth rate distribution in a direction parallel to the flow (x direction) is considered. The origin of x is set at the most upstream position of the wafer 1. Assuming that the average flow velocity is u, time t can be converted to t = x / u, and g (x) ∝C (x) = C (0) exp (−kx / u)
It is. k is the rate at which the raw material disappears per unit time. The uniformity q is defined as q = (maximum value of g−minimum value of g) / (g
Is defined as (maximum value of g + minimum value of g), the uniformity q 1 when treated only in the reactor 3 is
【0011】[0011]
【数1】 q1=(1−exp(−kd/u))/(1+exp(−kd/u)) …(数1) である。ここで、dはウエハの直径である。一方、本実
施例によれば、均一性q2 はQ 1 = (1−exp (−kd / u)) / (1 + exp (−kd / u)) (Equation 1) Here, d is the diameter of the wafer. On the other hand, according to the present embodiment, the uniformity q 2 is
【0012】[0012]
【数2】 q2=(1+exp(−kd/u)−exp(−kd/2u))/(1+exp(-kd/u)+exp(−kd/2u)) =((1−exp(−kd/2u)/(1+exp(−kd/2u))2 …(数2) である。このとき、比較のためq1 とq2 の比をとる
と、## EQU2 ## q 2 = (1 + exp (−kd / u) −exp (−kd / 2u)) / (1 + exp (−kd / u) + exp (−kd / 2u)) = ((1−exp (−kd / 2u) / (1 + exp (−kd / 2u)) 2 (Equation 2) At this time, if a ratio of q 1 and q 2 is taken for comparison,
【0013】[0013]
【数3】 q1/q2=(1+exp(−kd/2u))3/(1+exp(−kd/u))/(1−exp(−kd/2u)) =(1+exp(−kd/2u))2/(1+exp(−kd/u))*(1+exp(−kd/2u)) /(1−exp(−kd/2u)) …(数3) となる。0<k<∞,u>0の条件では## EQU3 ## q 1 / q 2 = (1 + exp (−kd / 2u)) 3 / (1 + exp (−kd / u)) / (1−exp (−kd / 2u)) = (1 + exp (−kd / 2u) )) 2 / (1 + exp (−kd / u)) * (1 + exp (−kd / 2u)) / (1−exp (−kd / 2u)) (Equation 3) Under the condition of 0 <k <∞, u> 0,
【0014】[0014]
【数4】 q1/q2>1 …(数4) であり、本発明によりウエハに対する処理の均一性が増
すことがわかる。Q 1 / q 2 > 1 (Equation 4) It can be seen that the present invention increases the uniformity of processing on the wafer.
【0015】次に本発明の他の実施例を示す。この実施
例では、反応炉3で所定の処理をした後に、ウエハ搬送
装置5によってウエハ1を反応炉3の外に出し、そこで
ウエハ1の向きを変え再び反応炉3に挿入し、前述の処
理とほぼ同様の処理をするというもので、反応炉がひと
つでもウエハ1への処理を均一にすることができる。Next, another embodiment of the present invention will be described. In this embodiment, after a predetermined process is performed in the reaction furnace 3, the wafer 1 is taken out of the reaction furnace 3 by the wafer transfer device 5, and the direction of the wafer 1 is changed and inserted into the reaction furnace 3 again. The processing is substantially the same as that described above, and the processing of the wafer 1 can be made uniform even with a single reactor.
【0016】第一の実施例でも第二の実施例でも、反応
炉での処理,ウエハの取り出し,反応炉外でのウエハの
向きの変更,ウエハの反応炉への挿入を複数回繰り返す
ことも可能で、ウエハの向きを少しづつ変えることで、
実質的にウエハを反応炉内で回転させるのと同様の効果
を得ることも可能である。In both the first embodiment and the second embodiment, the processing in the reactor, the removal of the wafer, the change of the orientation of the wafer outside the reactor, and the insertion of the wafer into the reactor may be repeated a plurality of times. It is possible, by changing the direction of the wafer little by little,
It is also possible to obtain substantially the same effect as rotating a wafer in a reaction furnace.
【0017】このとき、ウエハを反応炉内で回転させる
のと、ウエハを反応炉外で回転させるのとでは、発塵の
程度が大きく異なる。通常反応炉では、反応性のガスを
導入し、ウエハを処理するので、反応炉内ではウエハ以
外の部分もウエハとほぼ同等の環境にさらされている。
すなわち、ウエハに膜を成長させる場合には、反応炉内
のウエハ以外の部分にも膜が成長しており、従って、ウ
エハを回転させる機構にも膜が成長する。この回転機構
に膜が付着した状態でウエハを回転させると、付着した
膜がはがれ、発塵の原因となる。At this time, the degree of dust generation differs greatly between rotating the wafer inside the reaction furnace and rotating the wafer outside the reaction furnace. Usually, in a reaction furnace, a reactive gas is introduced to process a wafer, so that parts other than the wafer are exposed to an environment substantially equal to that of the wafer in the reaction furnace.
That is, when a film is grown on a wafer, the film also grows on a portion other than the wafer in the reaction furnace, and therefore, the film grows on a mechanism for rotating the wafer. If the wafer is rotated with the film adhered to the rotation mechanism, the adhered film is peeled off, causing dust.
【0018】ところが、本発明では回転機構があるのは
反応炉の外であり、そこは反応炉でウエハを処理してい
るときには、反応炉とはゲートバルブなどで分離されて
いる。従って、本発明によれば、少なくとも反応炉での
ウエハの処理と反応炉内の回転機構とが絡む塵埃を発生
することがない。In the present invention, however, the rotation mechanism is provided outside the reaction furnace, and is separated from the reaction furnace by a gate valve or the like when processing the wafer in the reaction furnace. Therefore, according to the present invention, there is no generation of dust involved in at least the processing of the wafer in the reaction furnace and the rotating mechanism in the reaction furnace.
【0019】図1に示した半導体処理装置では、反応炉
は二つしか具備されていないが、それ以上の反応炉を用
いて同様の効果を得ることもできる。また、図1で異な
るウエハに対して反応炉3における処理と反応炉4にお
ける処理をほぼ同時に行うことにより、さらには、ウエ
ハの待ち時間が最小になるようにウエハ搬送と処理のシ
ーケンスを考慮することにより、反応炉の効率的な利用
も可能となる。Although the semiconductor processing apparatus shown in FIG. 1 has only two reactors, the same effect can be obtained by using more reactors. Also, in FIG. 1, the processing in the reaction furnace 3 and the processing in the reaction furnace 4 are performed almost simultaneously on different wafers, and further, the sequence of the wafer transfer and the processing is considered so that the waiting time of the wafer is minimized. As a result, efficient use of the reactor becomes possible.
【0020】また、上述した実施例ではウエハの回転機
構が反応炉3あるいは反応炉4内に存在しないので、反
応炉3あるいは反応炉4では一度に二枚のウエハを処理
することも可能である。このときの反応炉3の断面図の
一例を図2に示す。反応炉3の中にウエハは二枚は水平
に積層するようにウエハ支持台8に置かれる。ウエハ1
は上下に位置するヒータ9によって加熱される。また、
反応炉3及びヒータ9は断熱材10によって覆われてお
り、二枚のウエハを均一に加熱するようになっている。
このとき、上側のウエハから反応炉内壁までの距離と下
側のウエハから上側のウエハまでの距離はほぼ等しくな
るようにしている。これは上側のウエハと下側のウエハ
とに施す処理を均一にするためである。また、反応炉3
に同時に入れるウエハは最大二枚とする。それは短時間
でウエハを均一に加熱するには、三枚以上のウエハを入
れることはできない。ウエハは熱輻射によって加熱され
るので、上下のウエハはそれぞれ反応炉3の上下の壁か
らの熱輻射を受ける。もし、三枚以上のウエハをほぼ水
平に積層するようにおいた場合、中心に位置するウエハ
は反応炉の壁からの熱輻射は受けにくく、短時間で均一
な温度にすることはできないためである。In the above-described embodiment, since the wafer rotating mechanism does not exist in the reaction furnace 3 or the reaction furnace 4, the reaction furnace 3 or the reaction furnace 4 can process two wafers at a time. . FIG. 2 shows an example of a sectional view of the reaction furnace 3 at this time. In the reaction furnace 3, two wafers are placed on a wafer support 8 so as to be stacked horizontally. Wafer 1
Are heated by heaters 9 located above and below. Also,
The reactor 3 and the heater 9 are covered with a heat insulating material 10 so as to heat two wafers uniformly.
At this time, the distance from the upper wafer to the inner wall of the reaction furnace and the distance from the lower wafer to the upper wafer are substantially equal. This is to make the processes performed on the upper wafer and the lower wafer uniform. Also, the reactor 3
The maximum number of wafers that can be simultaneously loaded in a wafer is two. In order to heat the wafer uniformly in a short time, it is not possible to insert three or more wafers. Since the wafers are heated by the heat radiation, the upper and lower wafers receive the heat radiation from the upper and lower walls of the reaction furnace 3 respectively. If three or more wafers are stacked almost horizontally, the centrally located wafer is less likely to receive heat radiation from the walls of the reaction furnace, and cannot have a uniform temperature in a short time. .
【0021】以上、発明はCVDを例にとって説明した
が、本発明は適用がCVDに限られるものではなく、エ
ピタキシャル成長,酸化,エッチング処理などに対して
も適用可能である。Although the present invention has been described with reference to the CVD, the present invention is not limited to the CVD but can be applied to epitaxial growth, oxidation, etching, and the like.
【0022】[0022]
【発明の効果】本発明によれば、反応炉の中にウエハの
回転機構を設けることなく、一度に二枚のウエハの処理
をウエハ全面で均一にすることができる。また、反応炉
の中にウエハの回転機構がないので、ウエハの処理に起
因する発塵を低減することができる。According to the present invention, the processing of two wafers at a time can be made uniform over the entire surface of the wafer without providing a wafer rotating mechanism in the reactor. Further, since there is no wafer rotating mechanism in the reaction furnace, dust generation due to wafer processing can be reduced.
【図1】本発明の一実施例の半導体処理装置の説明図。FIG. 1 is an explanatory diagram of a semiconductor processing apparatus according to one embodiment of the present invention.
【図2】本発明の一実施例の反応炉の断面図。FIG. 2 is a sectional view of a reactor according to one embodiment of the present invention.
1…ウエハ、2…カセット室、3…反応炉、4…他の反
応炉、5…ウエハ搬送装置、6…冷却室、7…他の冷却
室。DESCRIPTION OF SYMBOLS 1 ... Wafer, 2 ... Cassette chamber, 3 ... Reaction furnace, 4 ... Other reaction furnace, 5 ... Wafer transfer device, 6 ... Cooling room, 7 ... Other cooling room.
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 H01L 21/68 H01L 21/302 B ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 6 Identification code Agency reference number FI Technical display location H01L 21/68 H01L 21/302 B
Claims (1)
を処理する半導体処理装置において、第一反応炉で前記
ウエハに処理を施した後、前記ウエハを前記第一反応炉
から取り出し、前記第一反応炉と第二反応炉とでは前記
ウエハの向きと平均的なガスの流れの関係が異なるよう
に前記第一反応炉,前記第二反応炉の外で前記ウエハの
向きを調整し、前記ウエハを前記第二反応炉に入れ、前
記処理とほぼ同一の処理を施すことを特徴とする半導体
処理装置。1. A semiconductor processing apparatus having a plurality of reactors for processing wafers in said reactor, wherein said wafers are processed in a first reactor and then taken out of said first reactor. The direction of the wafer is adjusted outside the first and second reactors so that the relationship between the direction of the wafer and the average gas flow differs between the first and second reactors. Then, the semiconductor processing apparatus is characterized in that the wafer is placed in the second reaction furnace and subjected to substantially the same processing as the above processing.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16269396A JPH1012561A (en) | 1996-06-24 | 1996-06-24 | Semiconductor treating apparatus |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16269396A JPH1012561A (en) | 1996-06-24 | 1996-06-24 | Semiconductor treating apparatus |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH1012561A true JPH1012561A (en) | 1998-01-16 |
Family
ID=15759511
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16269396A Pending JPH1012561A (en) | 1996-06-24 | 1996-06-24 | Semiconductor treating apparatus |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH1012561A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008124191A (en) * | 2006-11-10 | 2008-05-29 | Hitachi High-Technologies Corp | Vacuum processing apparatus |
-
1996
- 1996-06-24 JP JP16269396A patent/JPH1012561A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008124191A (en) * | 2006-11-10 | 2008-05-29 | Hitachi High-Technologies Corp | Vacuum processing apparatus |
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