JPH10125601A - Field effect transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a field effect transistor which exhibits good stain characteristic high-frequency amplification. SOLUTION: A field effect transistor comprises a GaAs substrate 11 on which a buffer layer 12 made of an undope-GaAds layer, a first n-InGaAs layer 13a in which composition ratio of In is 0.2, a second n-InGaAs layer 13b in which composition ratio of In is 0.02, a contact layer 15 made of an n+-type GaAs layer, a gate electrode 16, a source electrode 17 and a strain electrode 18 are provided. An operating layer comprises the first n-INGaAs layer 13a and the second n-InGaAs layer 13b through which operating current flows. Since the second n-InGaAs layer 13b which exhibits a high crystallizability is formed on the first n-IGaAs layer 13a, a field effect transistor can be manufactured with good reproducibility, exerting extremely low strain characteristics. in which IP2 is 67.2dBm and IP3 is 35dBm.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device using a compound semiconductor, and more particularly to a field effect transistor used in a microwave band and characterized by low distortion.

[0002]

2. Description of the Related Art Conventionally, a field effect transistor using a compound semiconductor material such as GaAs exhibits excellent amplifying and oscillating effects in an ultra-high frequency range from microwaves to millimeter waves. Widely used in applications dealing with Recently, the market is expected to expand further in the future due to the spread of satellite broadcasting and mobile phones.

[0003] As a field effect transistor using such a compound semiconductor, conventionally, for example, Reference 1 (GaAs / InGaA)
Study of low distortion and low noise broadband amplifier using s MESFET 19
The one disclosed in 1993 IEICE Spring Lecture Book C-529) is known.

FIG. 10 shows n
-InGaAs / n-GaAs pseudomorphic MES
It is sectional drawing which represented the structure of FET in the figure. 10, 51 is a semi-insulating GaAs substrate, 52 is an Undope-GaAs layer as a buffer layer, and 53 is n-type as an operating layer.
The InGaAs layer 54 also has n-Ga as an operation layer.
As layer 55, n ⁺ -type GaAs as contact layer
Layer, 56 is a gate electrode, 57 is a source electrode, and 58 is a drain electrode. The features of this field effect transistor are
The point is that an n-GaAs layer 54 and an n-InGaAs layer 53 are provided as operation layers.

FIG. 11 shows the change characteristics of the output power Pout, the second-order intermodulation distortion IM2, and the third-order intermodulation distortion IM3 shown in the above-mentioned document 1 with respect to the input Pin. Here, the value of the second-order intercept point IP2 indicating the degree of intermodulation distortion is 59.4 dBm, and the value of the third-order intercept point IP3 is 32.2 dBm. However, although the meanings of IP2 and IP3 will be described later, a larger value indicates better distortion characteristics.

FIG. 12 shows the relationship between the gate voltage Vgs and the transconductance gm described in the above reference 1. Here, the transconductance gm is the rate of change of the drain current Ids with respect to the gate voltage Vgs (ΔIds / Δ
Vgs), the transfer characteristic is considered to be more linear as it shows a constant value with respect to the change of the gate voltage Vgs, that is, there is no gate voltage dependency. Generally, the gm characteristic of a field effect transistor having an operation layer composed of a single GaAs layer has a strong dependence on the gate voltage Vgs. In contrast, the n-InGaAs layer has an n-G
As compared with the aAs layer, the electron mobility is large and the solid solution limit of silicon (Si) as a dopant is large, so that high concentration can be achieved. For this reason, a field effect transistor having such a channel structure has a larger drain current and a transconductance gm (ΔIds / Δ) than a field effect transistor whose channel is formed only of a GaAs layer.
ΔVgs) increases, and as a result, operation at a higher frequency becomes possible. Further, by optimizing the carrier concentration and the thickness of the GaAs layer and the InGaAs layer, it is possible to flatten the characteristics of the transconductance gm, the gate and the source voltage Vgs.

[0007] For example, reference 2 (MF Chang et.a
l., Appl. Phys. Lett., Vol. 45, no. 3, 1984, pp. 279
-281), the piezo charge generated in the channel region of the field effect transistor due to the stress (stress) between the GaAs substrate and the passivation film such as SiO ₂ or SiN causes the electric field effect It has been reported that the electric characteristics such as the threshold voltage Vth and the transconductance gm of the transistor are changed.

FIG. 13 is a diagram for defining the relationship between the crystal orientation of the GaAs substrate, the orientation of the gate electrode of the field effect transistor (the direction parallel to the long side of the gate electrode), and the direction in which the drain current flows. Generally, the gate direction is arranged to be perpendicular to the direction in which the drain current flows. Conventionally, when a field-effect transistor is manufactured using a commercially available standard GaAs substrate, the gate orientation is [01] on a GaAs substrate having a (100) main surface.
1] direction or [01 1 ] direction (however, (Bar means minus, and the same applies to the following) in many cases. The electric characteristics of the field-effect transistor formed in such an orientation may change due to stress of a passivation film or the like.

[0009]

By the way, when a high frequency amplifier circuit is formed using a field effect transistor formed on a general conventional compound semiconductor substrate, the non-linearity of the field effect transistor causes In the output signal, a distortion component not included in the input signal may appear.

The distortion includes harmonic components corresponding to n times the frequency of the input signal, and intermodulation distortion generated by the frequency components of two or more types of input signals interfering with each other. ing. Since these distortion components mainly occur due to the non-linearity of the transfer characteristics of the amplifying element, it can be said that the magnitude of the distortion component is substantially determined by the transfer characteristics of the amplifying element. In high-frequency operation, the gate
The non-linearity of the rate of change (ΔCgs / ΔVgs) of the inter-source capacitance Cgs with respect to the gate-source voltage Vgs also becomes an important problem. In other words, it can be said that how to produce an amplification element capable of linear operation largely determines the distortion characteristics of the high-frequency amplification device.

These distortions (mainly second-order intermodulation distortion and 3
Second-order intermodulation distortion) is, for example, desirably reduced as much as possible in radio equipment and the like because it causes interference. Further, in a wideband amplifier for simultaneously amplifying a large number of carriers (carriers) at high frequency, a field effect transistor having extremely good distortion characteristics is required, especially since these distortions may overlap with adjacent carriers and cause interference.

However, conventionally, there is no field-effect transistor exhibiting an ideal good distortion characteristic, and the distortion characteristic of the high-frequency amplifier is improved by forming a complicated circuit such as a push-pull configuration. .

Considering the above-mentioned distortion characteristics, the conventional field-effect transistors described in the above-mentioned conventional documents 1 and 2 have the following problems.

Reference 1 discloses that n-
The GaAs / n-InGaAs pseudomorphic structure is
It is described that epitaxial growth is performed by MBE (molecular beam epitaxy). Where MBE
In order to obtain good crystallinity by the method, for example, GaAs is formed on an In _0.20 Ga _0.80 As layer having an In composition ratio of 0.20.
When forming an s layer, the GaAs layer has a substrate temperature of 580 ° C.
As described above, the InGaAs layer needs to be epitaxially grown at about 470 ° C. to 530 ° C. That is, in order to epitaxially grow the n-GaAs / n-InGaAs pseudomorphic structure as in the conventional example, it is necessary to temporarily set the
After epitaxially growing an n-InGaAs layer at a temperature of about 530 ° C. to 530 ° C., the growth is interrupted, and the
GaAs layer is epitaxially grown or
After epitaxial growth of the n-InGa layer at 530 ° C., the only option was to perform epitaxial growth of the n-GaAs layer without changing the substrate temperature.

However, in the former case, not only a complicated operation is required to temporarily suspend the crystal growth, but also the crystallinity of the n-GaAs / n-InGaAs interface constituting the operation layer becomes poor. In addition, there is a problem that impurities are mixed into the interface. In the latter case, n-InG
In order to give priority to the substrate temperature in the epitaxial growth of the aAs layer, n which should be grown at about 580 ° C.
-The GaAs layer must be grown at a low temperature of 470 ° C to 530 ° C. Therefore, Ga vacancies increase and n
-There was a problem that the crystallinity of the GaAs layer deteriorated.
That is, it is difficult to obtain an epitaxial layer having sufficiently good crystallinity as an operation layer of a field-effect transistor by any method.

It is considered that the high-frequency amplifier is formed by using the field-effect transistor manufactured by such a method. For example, there is a problem that the noise characteristic of the amplifier is deteriorated.

Note that GaAs and In _x Ga _{1 -x} As (x
Is the In composition ratio).
GaAs / In _x Ga _1-x As as in the conventional example described above.
The interface is in a pseudomorphic state. Therefore, although it depends on the In composition ratio x, the thickness of the In _x Ga _1-x layer has a critical thickness for maintaining good crystallinity.

Further, conventionally, a GaAs substrate and, for example, S
It is known that the electrical characteristics of a field effect transistor change due to stress between the passivation film such as iO ₂ and SiN. This is because, for example, SiO ₂ or SiN
A piezo charge (positive or negative) is generated by a stress caused by a difference in thermal expansion coefficient between an insulating film such as a GaAs substrate and a GaAs substrate, and deforms a carrier profile of an operation layer of a field effect transistor formed by introducing impurities. Is what happens to you. Therefore, the electric characteristics of the field-effect transistor depend on the direction (compression or extension) or magnitude of the stress, and are dependent on the crystal orientation.

FIG. 14 shows Ga having a (100) main surface.
FIG. 9 is a diagram illustrating the dependency of the amount of change in the threshold voltage of a field-effect transistor formed on an As substrate on the insulating film thickness. However, the insulating film (passivation film) on the GaAs substrate
Is plotted on the abscissa and the amount of change in the threshold voltage Vth of the field effect transistor is plotted on the ordinate, and the direction of the gate electrode (see FIG. 13) is used as a parameter. Here, the stress of the insulating film is Compressive. As can be seen from the figure, the shift of the threshold voltage tends to increase as the film thickness increases (the stress increases). Also, (1
The shift of the threshold voltage of the field-effect transistor having the [001] plane as the principal plane and the gate orientation in the [011] direction is in the positive direction. On the other hand, the threshold voltage shift of the field-effect transistor having the (100) plane as the main surface and the gate direction in the [011] direction is the same as the shift direction of the threshold voltage when the gate direction is [01 1 ]. Is the opposite negative direction. Further, it can be seen that the threshold voltage of the field effect transistor whose gate orientation is the [010] direction or the [001] direction does not change regardless of the magnitude of the stress. This is because a positive piezo charge is generated in the operation layer region of the field effect transistor when the gate direction is the [01 1 ] direction, and a negative piezo charge is generated when the gate direction is the [011] direction. On the other hand, if the gate orientation is the [010] direction or [001]
This is because, in the case of the direction, no piezo charge which affects the electric characteristics is generated near the operation layer of the field effect transistor.

Here, in the case of a field effect transistor having particularly excellent distortion characteristics, reproducibility (linearity) of transfer characteristics (Vg-Ids characteristics, etc.) is important. Therefore, a change in transfer characteristics (electrical characteristics) due to such a piezo effect means that the distortion characteristics of the field effect transistor are greatly adversely affected. Specifically, since the electrical characteristics of the field effect transistor change due to the piezo effect,
There is a problem that extremely high distortion characteristics cannot be obtained with good reproducibility. Further, there is a problem in that it is difficult to manufacture a field-effect transistor having extremely good distortion characteristics with good reproducibility.

As described above, in the conventional field effect transistor, it is difficult to obtain practically necessary distortion characteristics by a single field effect transistor. Therefore, conventionally, for example, a complicated circuit such as a push-pull circuit in which a plurality of field-effect transistors having the same characteristics are arranged to offset the distortion of the field-effect transistor is configured, so that the distortion characteristics of the high-frequency amplification device are reduced. Had improved.

A first object of the present invention is to provide a field effect transistor which can exhibit extremely good distortion characteristics by itself without forming a complicated circuit.

A second object of the present invention, in addition to the first object, is to eliminate changes in electrical characteristics such as transfer characteristics caused by piezo charges generated by stress.

[0024]

In order to achieve the first object, the means taken by the present invention is a conventional n-InGa
Instead of the operation layer composed of an As layer and an n-GaAs layer,
An object of the present invention is to provide an operation layer including only an InGaAs layer.

More specifically, in order to achieve the first object, means relating to the first charge-effect transistor described in claims 1 and 2 and the second means described in claims 3 and 4 are provided. Means relating to the second charge effect transistor, means relating to the third charge effect transistor according to claims 5 and 6, and means relating to the fourth charge effect transistor according to claims 7 and 8 are taken. ing.

In order to achieve the second object,
In the present invention, the means relating to the fifth field-effect transistor described in claims 9 and 10 is adopted. According to the first field effect transistor of the present invention, as described in claim 1, a substrate, a buffer layer formed on the substrate by epitaxial growth, and an operating current formed on the buffer layer and having an operating current of A flowable operation layer, a gate electrode formed above the operation layer, and a source / drain formed on the substrate located on both sides of the gate electrode and connected to both ends of the operation layer. Have. And the operating layer is formed on the buffer layer,
N-In _a Ga having an In composition ratio of a (0 <a <1)
_An n-In layer formed on the _1-a As layer and the n-In _a Ga _1-a As layer and having an In composition ratio of b (0 <b <a)
_b Ga _1-b As layer.

According to a second aspect of the present invention, in the first aspect, the In composition ratio a of the n-In _a Ga _{1- a} As layer is 0.01 or more, and the n-In _b Ga _1-b
The In composition ratio b of the As layer is preferably 0.25 or less.

According to the first field effect transistor of the first or second aspect, the operation layer is composed of an n-In _a Ga _1-a As layer and an n-
It is composed of In _b Ga _1-b As 2 two n-InGaAs layer that layer. Therefore, n-In _a Ga
_The n-In _b Ga _1-b As layer can be continuously formed on the _1-a As layer under substantially the same conditions, and the upper n-side layer can be formed.
Crystalline -In _b Ga _1-b As layer is satisfactorily maintained.
As a result, high power gain, low noise figure, and high IP
2 and IP3, that is, small intermodulation distortion can be obtained. Also, for example, n-type InGa such as silicon (Si)
The introduction of a donor for constituting As can be controlled completely independently of the above-described In composition ratio. Therefore, the carrier profile can be arbitrarily formed so that the field effect transistor exhibits lower distortion characteristics (linear operation), so that the degree of freedom in designing the operation layer is also improved. The distortion characteristics of the field effect transistor can be improved in combination with the effect of improving the nonlinearity of the mutual conductance gm.

[0029] The second field effect transistor of the present invention comprises:
As described in claim 3, a semi-insulating GaAs substrate, a buffer layer formed on the semi-insulating GaAs substrate by epitaxial growth, and an operating current formed on the buffer layer and capable of flowing an operating current. An operation layer, a gate electrode formed above the operation layer, and a source / drain formed on the semi-insulating GaAs substrate located on both sides of the gate electrode and connected to both ends of the operation layer. It has. The operation layer has three or more nI
_nx Ga _1-x As layer, and each n-In
Each In composition ratio x (0 <x <1) of the _x Ga _1-x As layer is
The upper n-In _x Ga _{1 -x} As layers are different from each other so as to be smaller.

According to a fourth aspect, in the third aspect, the In composition ratio x of each of the n-In _x Ga _{1 -x} As layers is 0.01 or more and 0.25 or less. preferable.

According to the second field effect transistor of claim 3 or 4, at least three n-Is constituting an operation layer.
Since the In composition ratio of the nGaAs layer is configured to decrease as it goes upward, the crystallinity of each n-InGaAs layer is better when forming the operation layer than in the operation layer of the conventional field effect transistor. Can be. Therefore, the distortion characteristics can be further improved as compared with the above-mentioned conventional field effect transistor.

The third field-effect transistor of the present invention comprises:
As described in claim 5, a substrate, a buffer layer formed by epitaxial growth on the substrate, an operation layer formed on the buffer layer, through which an operation current can flow, A gate electrode formed above, and a source / drain formed on the substrate located on both sides of the gate electrode and connected to both ends of the operation layer. The operation layer is formed on the buffer layer, and has an In composition ratio of a (0 <a <1), an n-In _a Ga _1-a As layer, and the n-In _a Ga layer.
_1-a is formed on the As layer and has an In composition ratio x (0 <x <
a) is constituted by an n-In _x Ga _{1 -x} As layer which changes so as to continuously decrease upward.

[0033] As described in claim 6, in claim 5, said n-In _a Ga _1-a As layer having an In composition ratio a is 0.01 or more, the n-In _x Ga _1-x
The In composition ratio x of the As layer is preferably 0.25 or less.

According to the third field effect transistor of the fifth or sixth aspect, two n-InGaAs layers constituting an operation layer are provided.
Of the layers, the upper n-InGaAs layer is configured so that the In composition ratio of the upper n-type InGaAs layer becomes smaller continuously as it goes upward. Each n-I than in layers
The crystallinity of the nGaAs layer can be improved. Therefore, the distortion characteristics can be further improved as compared with the above-mentioned conventional field effect transistor.

The fourth field-effect transistor of the present invention comprises:
As described in claim 7, a semi-insulating GaAs substrate, a buffer layer formed by epitaxial growth on the semi-insulating GaAs substrate, and an operating current formed on the buffer layer and capable of flowing an operating current. An operation layer, a gate electrode formed above the operation layer, and a source / drain formed on the semi-insulating GaAs substrate located on both sides of the gate electrode and connected to both ends of the operation layer. It has. The operating layer has an In composition ratio x
(0 <x <1) is formed of an n-In _x Ga ₁ -xAs layer that changes so as to continuously decrease upward.

[0036] As described in claim 8, in claim 7, an In composition ratio of the n-In _x Ga _{1- x} As layer is preferably 0.25 or less 0.01 or more .

According to the fourth field effect transistor of the seventh or eighth aspect, the operation layer is constituted by one n-InGaAs layer 43, and the In composition ratio of the n-InGaAs layer 43b continuously decreases as going upward. Therefore, when forming the operation layer, the n-InGa layer is formed more than in the operation layer of the conventional field effect transistor.
The crystallinity of the As layer can be further improved. Therefore, the distortion characteristics can be further improved as compared with the above-described conventional field-effect transistor while having a relatively simple configuration.

The fifth field-effect transistor of the present invention comprises:
As described in claim 9, claims 1, 2, 3, 3
In 4, 5, 6, 7, or 8, the plane of the operation layer parallel to the upper surface of the substrate is defined as a (100) plane, and the direction in which the operation current flows in the operation layer is defined as a [010] direction or [001]. Things.

According to a tenth aspect of the present invention, in the ninth aspect, the cross-sectional shape of the gate electrode is a rectangle having a long side and a short side, and the long side of the gate electrode is operated in the operation layer. It is preferable to make the direction perpendicular to the direction in which the current flows.

According to the fifth field effect transistor of the ninth or tenth aspect, the electric characteristics of the field effect transistor are not affected by the piezo effect regardless of the magnitude of the stress generated between the substrate and the passivation film. It becomes possible to. As a result, the electric characteristics of the field-effect transistor have been changed by the stress of the insulating film, but the electric characteristics of the field-effect transistor are almost not changed by the stress. In this manner, a field effect transistor exhibiting extremely good distortion characteristics can be manufactured with good reproducibility.

[0041]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) FIG. 1 is a sectional view of a field-effect transistor according to a first embodiment. In FIG. 1, reference numeral 11 denotes a semi-insulating GaAs substrate, and reference numeral 12 denotes a film having a thickness of 7 as a buffer layer.
4 shows a 00 nm Undope-GaAs layer. Reference numeral 13a denotes a first n-InGaAs layer having a carrier concentration of 8 × 10 ¹⁷ cm ⁻³ , a film thickness of 10 nm, and an In composition ratio of 0.2.
13b has a carrier concentration of 5 × 10 ¹⁷ cm ⁻³ and a film thickness of 6
0 nm, the second n-InG having an In composition ratio of 0.02
4 shows an aAs layer. The first n-InGaAs layer 13a
The second n-InGaAs layer 13b and the second n-InGaAs layer 13b constitute an operation layer through which an operation current flows. Reference numeral 15 denotes an n ⁺ -type GaAs layer having a carrier concentration of about 4 × 10 ¹⁸ cm ⁻³ and a thickness of 50 nm as a contact layer, 16 denotes a gate electrode,
17 is a source electrode and 18 is a drain electrode.

The feature of the field-effect transistor according to this embodiment is that the first n-InGaAs having an In composition ratio of 0.2 is used.
A layer 13a and a second n-InG having an In composition ratio of 0.02.
An aAs layer 13b is provided as an operation layer.

FIG. 5 shows the result of measuring the intermodulation distortion by the two-tone method by forming a negative feedback amplifier using the field effect transistor according to the present invention. However, as shown in FIG. 8, the feedback resistance of the negative feedback circuit is 330Ω and the feedback capacitance is 1000 pF. In FIG. 5, Pin denotes input power per unit wave (unit: dBm), Pout denotes output power per unit wave of fundamental wave (unit: dBm), IM2 denotes second-order intermodulation distortion, and IM3 denotes third-order intermodulation distortion. ing.

Here, when two or more signals are input to the high-frequency amplifier, intermodulation occurs between the input signals or a harmonic generated by nonlinearity of the amplifier, and spurious is generated at the output of the amplifier. I do. In the range where the amplifier operates linearly, as shown in FIG. 5, the fundamental wave Pout of the output signal changes 1: 1 with respect to the input Pin, while the second-order intermodulation distortion IM2 is applied to the input Pin. In contrast, the third-order intermodulation distortion IM3 changes 1: 3 with respect to the input Pin. Generally, an intercept point (IP2, I
P3) is widely used. This is expressed as a theoretical power at which the level (power) of the fundamental wave Pout of the output signal and the intermodulation distortion IM2 and IM3 becomes equal, and the larger the value, the better the distortion characteristic.

As shown in FIG. 5, when the field-effect transistor of this embodiment is used, IP2 is 67.2 dBm.
(Output power display), IP3 is 35 dBm (output power display), and IP2 shown in Document 1 is 59.4 dBm,
This is a great improvement over 32.2 dBm of IP3.
This is considered to be due to the following reasons.

As described in the conventional document 1, In
When forming an operation layer including a GaAs layer, generally,
The In composition ratio is about 0.2. Then, as described above, the n-GaAs / n-In used in the operation layer is used.
_{When 0.2} Ga _0.8 As is epitaxially grown by MBE (molecular beam epitaxy), the GaAs layer must have a substrate temperature of 58 to obtain good crystallinity by MBE.
0 ° C. or more, In _0.2 Ga _0.8 As layer is 470 ° C. to 530
Epitaxial growth at about ° C is required. Therefore, the pseudomo- bility of n-GaAs / n-InGaAs
In order to grow an rphic structure epitaxially, InG
After growing the aAs layer, the growth is interrupted and n-G
The epitaxial growth of the aAs layer is performed or n at the same temperature.
After epitaxial growth of the -InGaAs layer, the only alternative was to perform epitaxial growth of the n-GaAs layer without changing the substrate temperature. Therefore, it is considered that the crystallinity of the n-GaAs layer was deteriorated. In contrast, in the present embodiment, when forming the operation layer, the first n-InGa
Since the second InGaAs layer 13b is formed on the As layer 13a, the second InGaAs layer 13b is formed at 470 ° C.
At a low temperature of about 30 ° C., epitaxial growth can be continuously performed once, and the second InGaAs
The crystallinity of the layer 13b is improved. As a result, n-InG
It is considered that an extremely small intermodulation distortion as shown in FIG. 5 can be realized in combination with the characteristic that the carrier mobility in the aAs layer is high.

FIG. 6 is a diagram showing the gate voltage dependence of the mutual inductance gm of the field effect transistor of the present embodiment and a conventional field effect transistor having an operation layer composed of a single GaAs layer. In the figure, curve A represents GaAs formed by ion implantation.
G of a field-effect transistor having a single-layer operation layer
The m characteristic, curve B, shows the characteristic of the field effect transistor according to the present embodiment. As shown in the figure, the field effect transistor of the present embodiment has a flattened characteristic between the transconductance gm, the gate and the source voltage Vgs, as compared with a conventional field effect transistor using a GaAs single layer. In addition, the conventional n-GaAs / n-InG
The flat range of the characteristic between the transconductance gm, the gate and the source voltage Vgs is slightly wider than that of the aAs field-effect transistor. This seems to be due to the following reasons.

That is, when forming the field effect transistor of the present embodiment, the introduction of the donor using silicon (Si) into the n-InGaAs layer can be controlled completely independently of the above-mentioned In composition ratio. Therefore, I
By optimizing the carrier profile (carrier concentration distribution in the depth direction) and the thickness of the nGaAs layer, the transconductance gm-gate-source voltage Vgs
It is possible to more remarkably flatten the characteristics. As a result, the field-effect transistor having the channel structure as in the present embodiment has the n-GaAs / n-I
Compared to those having an operation layer composed of nGaAs,
It has a high degree of design freedom for the structure of the operating layer and exhibits extremely good distortion characteristics.

FIG. 7 is a graph showing the frequency dependence of the gain Gain and the noise figure NF of the field-effect transistor of this embodiment. As shown in the figure, in the present embodiment, while configuring a simple negative feedback circuit in which the single field-effect transistor shown in FIG. 8 is arranged, a high power gain of 13 dBm or more and a 2 dBm
The following low noise figure is realized. In order to realize such a high power gain and a low noise figure with a field-effect transistor having an operation layer consisting of only an n-GaAs layer, a complicated circuit such as the push-pull circuit described above must be constructed. Absent. Therefore, the circuit itself becomes large, and a plurality of field effect transistors using an expensive compound semiconductor substrate are required, so that the manufacturing cost is also increased. On the other hand, in the present embodiment, it is understood that a high power gain and a low noise figure can be obtained by the negative feedback circuit in which a single field effect transistor is arranged.

As described above, the field effect transistor of the present embodiment has a very small distortion characteristic which cannot be realized by the conventional field effect transistor while maintaining a high gain. This is achieved by a simple configuration as shown in FIG. 8 in a wideband amplifier for simultaneously amplifying a large number of carriers (carriers) such as CATV, that is,
High power gain, low noise figure, and extremely small composite intermodulation distortion (CSO, CTB) can be realized without using a complicated configuration such as a push-pull circuit combining a plurality of field effect transistors. Moreover, it is of great value.

By adding a very small amount (0.1 to 0.4 mol%) of In at the time of crystal growth of a GaAs substrate, crystal defects (EPD) and dislocations are significantly reduced, or the electron mobility and the specific electric resistance are reduced. The fact that the rate can be remarkably uniformed is described, for example, in the literature (GaAs IC Symposium, 19
84, pp. 49-52). It is said that this is because the In atoms have a function of filling the transition generated during the crystal growth, but the same effect can be obtained also in the epitaxial growth using the MBE apparatus. Therefore, it is considered that the extremely low noise characteristic of the electric field transistor obtained by the present invention also contributes to the effect of reducing crystal defects and dislocation caused by the addition of In shown in the document.

(Second Embodiment) FIG. 2 shows a second embodiment and is a cross-sectional view of a field effect transistor according to the present invention. In FIG. 2, reference numeral 21 denotes a semi-insulating GaAs substrate, and reference numeral 22 denotes an undoped film having a thickness of 700 nm as a buffer layer.
4 shows a pe-GaAs layer. 23a has a carrier concentration of 8 ×
This shows a first n-InGaAs layer having 10 ¹⁷ cm ^-3 , a thickness of 10 nm, and an In composition ratio of 0.2. Reference numeral 23b denotes a second n-InGaAs layer having a carrier concentration of 5 × 10 ¹⁷ cm ⁻³ , a thickness of 30 nm, and an In composition ratio of 0.1.
23c has a carrier concentration of 2 × 10 ¹⁷ cm ⁻³ and a film thickness of 3
0 nm, third n-InG having an In composition ratio of 0.02
4 shows an aAs layer. The first InGaAs layer 23a,
The second InGaAs layer 23b and the third InGaAs layer 2
3c constitutes an operation layer. 25 has a carrier concentration of about 4 × 10 ¹⁸ c as a contact layer.
An n ⁺ -type GaAs layer having a thickness of m ⁻³ and a thickness of 50 nm, 26 is a gate electrode, 27 is a source electrode, and 28 is a drain electrode.

The feature of the field-effect transistor of this embodiment is that the first n-InGaAs layer 2 having an In composition ratio of 0.2
3a and a second n-InGaAs having an In composition ratio of 0.1
A layer 23b and a third n-InG layer having an In composition ratio of 0.02.
The point is that three layers including the aAs layer 23c are provided as operation layers.

In the present embodiment, since the In composition ratio of the three n-InGaAs layers constituting the operation layer becomes smaller as going upward, the conventional field effect transistor is formed when the operation layer is formed. The crystallinity of each n-InGaAs layer can be made better than in the operation layer of (1).

(Third Embodiment) FIG. 3 is a sectional view of a field effect transistor according to a third embodiment. 3, reference numeral 31 denotes a semi-insulating GaAs substrate, and 32 denotes an Undope-GaAs layer having a thickness of 700 nm as a buffer layer.
33a has a carrier concentration of 8 × 10 ¹⁷ cm ⁻³ and a thickness of 1
0 nm, the first n-InGa having an In composition ratio of 0.2
4 shows an As layer. 33b has a carrier concentration of 4 × 10 ¹⁷ c
The second n-InGaAs layer has an m ⁻³ , a thickness of 30 nm, and an In composition ratio continuously changing from 0.2 to 0.01 toward the substrate surface. The above first n-InGaAs
The s layer 33a and the second n-InGaAs layer 33ab constitute an operation layer. Reference numeral 35 denotes an n ⁺ -type GaAs layer having a carrier concentration of about 4 × 10 ¹⁸ cm ⁻³ and a thickness of 50 nm as a contact layer; 36, a gate electrode;
Denotes a source electrode and 38 denotes a drain electrode.

The feature of the field-effect transistor of this embodiment is that the first n-InGaAs layer 3 having an In composition ratio of 0.2 is used.
3a and a second n-InGa in which the In composition ratio continuously changes from 0.2 to 0.01 toward the substrate surface.
An As layer 33b is provided as an operation layer.

In this embodiment, of the two n-InGaAs layers forming the operation layer, the upper second n-InGa
Since the In composition ratio of the As layer 33b is configured to decrease continuously as going upward, the crystal of each n-InGaAs layer is formed more in the formation of the operation layer than in the operation layer of the conventional field effect transistor. Properties can be improved.

Note that the second n-InG
It is easy to continuously change the In composition ratio in the aAs layer 33b, which does not cause deterioration of the characteristics of the field effect transistor. However, it is desirable that the maximum value of the In composition ratio in the second n-InGaAs layer 33b is smaller than the In composition ratio in the first n-InGaAs layer 33a.

(Fourth Embodiment) FIG. 4 is a sectional view of a field effect transistor according to a fourth embodiment. In FIG. 4, reference numeral 41 denotes a semi-insulating GaAs substrate, and reference numeral 42 denotes an Undope-GaAs layer having a thickness of 700 nm as a buffer layer.
43 has a carrier concentration of 8 × 10 ¹⁷ cm ⁻³ and a film thickness of 30 n
m, In composition ratio from 0.2 to 0.0 toward the substrate surface
1 shows an n-InGaAs layer changing to 1. This n
The -InGaAs layer 43 constitutes an operation layer.
Reference numeral 45 denotes a carrier concentration of about 4 as a contact layer.
An n ⁺ -type GaAs layer of × 10 ¹⁸ cm ⁻³ and a thickness of 50 nm;
46 is a gate electrode, 47 is a source electrode, and 48 is a drain electrode.

The feature of the field effect transistor of this embodiment is that the In composition ratio is 0.2 to 0.0 toward the substrate surface.
N-InGaAs layer 43a continuously changing to 1
Is provided as an operation layer.

In this embodiment, the operation layer is composed of one n-In
The n-InGaAs layer 4 includes a GaAs layer 43.
Since the In composition ratio of 3b is configured to decrease continuously as it goes upward, the crystallinity of the n-InGaAs layer is more improved in forming the operation layer than in the operation layer of the conventional field-effect transistor. Can be good. Therefore, the effects of the first embodiment can be exhibited with a simple configuration.

(Fifth Embodiment) Although the illustration of the structure of the field effect transistor according to the fifth embodiment is omitted, the gate electrode 1 in the first to fourth embodiments shown in FIG.
The direction parallel to the long sides of Nos. 6 to 46, that is, the gate orientation defined in FIG. 13 is the [010] direction or the [001] direction.

FIG. 9 is a diagram showing the drain current dependence of the distortion characteristics of the field effect transistor according to the fifth embodiment. In the figure, the horizontal axis indicates the drain current Ids of the field effect transistor, and the vertical axis indicates IP2 which is a kind of intermodulation distortion. Here, the stress of the insulating film (passivation film) is Compressive.

As is clear from FIG. 6, when the gate direction of the field effect transistor is set to the [011] direction or the [01 1 ] direction as in the conventional case, the electric characteristics (Vgs-Ids characteristics) of the field effect transistor are caused by the piezo effect. It can be seen that the drain current Ids giving the peak of IP2 moves. On the other hand, when the gate direction of the field effect transistor is set to the [010] direction or the [001] direction as in the present embodiment, the drain current I which gives the peak of IP2 is not affected by the piezo effect.
It can be seen that ds does not change and shows good distortion characteristics with good reproducibility. That is, according to the present invention, it is possible to manufacture a field-effect transistor exhibiting extremely good distortion characteristics with good reproducibility.

In each of the above embodiments, n-InGaAs
Although the In composition of the s layer is 0.2 or less, the present invention is not limited to this range. When forming an n-InGaAs layer on a buffer layer composed of GaAs, it is necessary to ensure a critical film thickness of the n-InGaAs layer large enough to allow an operating current to flow at high speed.
It is preferable that the In composition of the n-InGaAs layer is 0.25 or less.

On the other hand, the In composition ratio of the n-InGaAs layer is preferably 0.01 or more. I below
When the n composition ratio is reached, the epitaxial growth of the n-InGaAs layer by the MBE method may not be performed smoothly.

In the embodiment, the G of the (100) main surface is
Although the description has been given using the aAs substrate, it is needless to say that other combinations of the main surface of the substrate and the gate orientation which are not affected by the piezo effect are also effective. By adopting such a structure, electric characteristics of the field-effect transistor due to the piezo effect caused by the stress between the GaAs substrate and the insulating film are eliminated, so that a field-effect transistor exhibiting extremely good distortion characteristics can be reproducibly obtained. It can be manufactured.

[0068]

As described above, according to the field effect transistors of the first to eighth aspects, the operation layer is formed of the first InGa
Since an operation layer including an As layer and a second InGaAs layer having an In composition ratio smaller than that of the As layer is provided,
With a simple method, the crystallinity of the active layer of the field effect transistor and the complicated workability during epitaxial growth can be remarkably improved, and at the same time, high frequency characteristics that cannot be realized by the conventional field effect transistor, that is, extremely good distortion characteristics And excellent characteristics such as extremely low noise characteristics and operation at higher frequencies.

According to the ninth and tenth aspects, according to the first aspect,
In addition to the configurations described above, the gate orientation is set to the [001] direction or the [010] direction, so that it is not affected by the piezo effect caused by the stress of the insulating film or the like, so that excellent distortion characteristics can be obtained with excellent reproducibility. The field effect transistor shown can be manufactured.

[Brief description of the drawings]

FIG. 1 is a sectional view of a field-effect transistor according to a first embodiment.

FIG. 2 is a sectional view of a field-effect transistor according to a second embodiment.

FIG. 3 is a sectional view of a field-effect transistor according to a third embodiment.

FIG. 4 is a sectional view of a field-effect transistor according to a fourth embodiment.

FIG. 5 is a diagram illustrating distortion characteristics of the field-effect transistor according to the first embodiment.

FIG. 6 is a diagram showing a comparison of the gate voltage dependence of the transconductance gm of the field effect transistor according to the first embodiment and a conventional field effect transistor having a GaAs single layer structure.

FIG. 7 is a diagram illustrating a power gain and a noise figure of the field-effect transistor according to the first embodiment.

FIG. 8 is a diagram showing a configuration of a negative feedback circuit configured to obtain the data shown in FIGS. 5 to 7;

FIG. 9 is a diagram illustrating a drain current dependence characteristic of IP2 with respect to a gate direction in the field-effect transistor according to the fifth embodiment and a conventional field-effect transistor.

FIG. 10 is a cross-sectional view of a conventional n-InGaAs / n-GaAs field-effect transistor.

FIG. 11 is a diagram showing distortion characteristics of a conventional field-effect transistor.

FIG. 12 is a diagram showing the gate voltage dependence of the transconductance gm of a conventional field effect transistor.

FIG. 13 is a diagram for defining the relationship between the crystal orientation in each part of the wafer and the gate orientation of the field-effect transistor.

FIG. 14 is a diagram showing a relationship between a thickness of a general insulating film and a change in threshold voltage of a field-effect transistor.

[Explanation of symbols]

Reference Signs List 11 semi-insulating GaAs substrate 12 buffer layer 13a first n-InGaAs layer 13b second n-InGaAs layer 15 n ⁺ type GaAs layer 16 gate electrode 17 source electrode 18 drain electrode 21 semi-insulating GaAs substrate 22 buffer layer 23a First n-InGaAs layer 23b Second n-InGaAs layer 23c Third n-InGaAs layer 25 n ⁺ -type GaAs layer 26 Gate electrode 27 Source electrode 28 Drain electrode 31 Semi-insulating GaAs substrate 32 Buffer layer 33a First N-InGaAs layer 33b Second n-InGaAs layer 35 n ⁺ -type GaAs layer 36 gate electrode 37 source electrode 38 drain electrode 41 semi-insulating GaAs substrate 42 buffer layer 43 n-InGaAs layer 45 n ⁺ -type GaAs layer 46 gate Electrode 47 Source electrode 48 Drain electrode

Claims (10)

[Claims] 1. A substrate, a buffer layer formed on the substrate by epitaxial growth, an operation layer formed on the buffer layer, through which an operation current can flow, and a gate formed above the operation layer An electrode, and a source / drain formed on the substrate located on both sides of the gate electrode and connected to both ends of the operation layer, wherein the operation layer is formed on the buffer layer, When the composition ratio is a (0 <
a and _{n-In a Ga 1-a} As layer is <1) is formed on the _{n-In a Ga 1-a} As layer, In composition ratio is b (0 <b <a) n -In _b Ga _1-b As
A field-effect transistor, comprising: 2. The field effect transistor according to claim 1, wherein the n-In _a Ga _{1 -a} As layer has an In composition ratio a of 0.
01 or more, and the In composition ratio b of the n-In _b Ga _1-b As layer is 0.1.
A field effect transistor having a size of 25 or less. 3. A semi-insulating GaAs substrate, a buffer layer formed on the semi-insulating GaAs substrate by epitaxial growth, an operating layer formed on the buffer layer, through which an operating current can flow, and A gate electrode formed above the layer; and the semi-insulating GaAs positioned on both sides of the gate electrode.
a source / drain formed on the s substrate and connected to both ends of the operation layer, wherein the operation layer is composed of three or more n-In _x Ga _1-x As layers; Each I of the In _x Ga _1-x As layer
The n composition ratio x (0 <x <1) is determined by the n-In
A field-effect transistor characterized in that _x Ga _{1 -x} As layers are different from each other so as to be smaller. 4. The field effect transistor according to claim 3, wherein the In composition ratio x of each of the n-In _x Ga _{1 -x} As layers is:
A field effect transistor having a value of 0.01 or more and 0.25 or less. 5. A substrate, a buffer layer formed on the substrate by epitaxial growth, an operation layer formed on the buffer layer, through which an operation current can flow, and a gate formed above the operation layer. An electrode, and a source / drain formed on the substrate located on both sides of the gate electrode and connected to both ends of the operation layer, wherein the operation layer is formed on the buffer layer, When the composition ratio is a (0 <
a and _{n-In a Ga 1-a} As layer is <1) is formed on the _{n-In a Ga 1-a} As layer, In composition ratio x (0 <x <a) is upwards And an n-In _x Ga _{1 -x} As layer that changes so as to be continuously smaller. 6. The field effect transistor according to claim 5, wherein the n-In _a Ga _{1 -a} As layer has an In composition ratio a of 0.
And at 01 or more, the _{n-In x Ga 1-x} As layer of the In composition ratio x is 0.
A field effect transistor having a size of 25 or less. 7. A semi-insulating GaAs substrate, a buffer layer formed on the semi-insulating GaAs substrate by epitaxial growth, an operating layer formed on the buffer layer, through which an operating current can flow, and A gate electrode formed above the layer; and the semi-insulating GaAs positioned on both sides of the gate electrode.
a source / drain formed on the s substrate and connected to both ends of the operation layer, wherein the operation layer has an In composition ratio x (0 <x <1) continuously decreasing upward. N-In _x Ga
A field effect transistor comprising a _1-x As layer. 8. The field effect transistor according to claim 7, wherein the n-In _x Ga ₁ -xAs layer has an In composition ratio of 0.0
A field effect transistor, wherein the number is 1 or more and 0.25 or less. 9. The field effect transistor according to claim 1, wherein a plane parallel to the upper surface of the substrate in the operation layer is (10).
0), and the direction in which the operation current flows in the operation layer is [010].
The field effect transistor, wherein the direction is [001]. 10. The field effect transistor according to claim 9, wherein a cross-sectional shape of the gate electrode is a rectangle including a long side and a short side, and the long side of the gate electrode is an operating current in the operation layer. A field-effect transistor, which is orthogonal to the direction in which the current flows.