JPH10125094A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To carry out the write operation with a special data pattern even in the testing mode by providing a first and a second data converting means on the predetermined memory cell sub-array within a memory device. SOLUTION: This semiconductor memory device is composed of a plurality of memory cell sub-arrays 301 including a memory cell, a data input means, a data output means and data converting circuits 303, 310. Moreover, the data input means is connected to a memory cell sub-array 301 via the data converting circuit 303, while the data output means is connected to the memory cell sub- array 301 via the data converting circuit 310. The data converting circuit 303, 310 are respectively composed of an inverter and can write special data pattern to all memory cell sub-arrays 301 during the testing mode. Therefore, a failure depending on the dependence on the data pattern can be detected with a higher possibility as in the case of the normal mode.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to writing and reading in a test mode in a dynamic semiconductor memory device.

[0002]

2. Description of the Related Art Next, a conventional technology will be described in detail with reference to the drawings, taking a 2M × 8 DRAM as an example. First, FIG. 1 shows an overall configuration diagram of a 16 mega DRAM. As shown in FIG.
The memory cell 1 is composed of a plurality of 256K-bit memory cell sub-arrays ARRAY, a row decoder, and a column decoder. However, only the main parts are shown here for the sake of simplicity.

The memory sub-array ARRAY is configured by arranging memory cells (not shown) in a matrix from information storage capacitors and information transfer transistors. A plurality of word lines (not shown) are connected in the row direction of the memory cells, and a desired word line is selected by a row decoder. A plurality of bit lines (not shown) are connected in the column direction, and a desired bit line pair is selected by a column decoder.

FIG. 2 shows a schematic configuration diagram of a DRAM having a 2M word × 8 bit configuration. This DRAM comprises data input means IN, switch sections SWI and SWO, memory cell sub-array block, and data output means OUT.

A memory cell array block is composed of 1M bits, and a 256K bit AR in FIG.
This corresponds to four RAYs. As shown in FIG. 2, the data input means IN is connected to the memory sub-array block via the switch unit SWI, and the data output means OUT
Is a memory sub-array blo through a switch SWO.
ck.

Next, the operation of the DRAM will be described. When the switch units SWI and SWO are connected in the normal direction (normal mode), normal data reading, writing, and refresh operations are performed.

The switch units SWI and SWO are connected to Te.
When connected in the st direction (test mode), a test operation is performed. Hereinafter, the operation in the test mode will be briefly described.

In the test mode, the input units I2 to I8,
The output units O1 to O7 are separated from the block, and only the input unit I1 and the output unit O8 are connected to the memory cell sub-array block.
ck.

Now, test data is input to input means IN. However, as mentioned above, when in test mode,
Since only the input unit I1 and the output unit O8 are connected to the memory cell sub-array block, the data input to the input unit I1 is stored in all the memory cell sub-arrays block.
written to ck. That is, the same data is written in all the memory cell sub-arrays. For example, it is assumed here that data "1" has been written.

Next, the written data is read out all at once and output to the output section O8 via the logic circuit LG.
In this case, since all the read data passes through the AND gate 3, if at least one of the read data is inverted to data "0", the output becomes "0". If the output data is "1", it is determined to be normal, and the output data is "0".
If so, it is determined to be abnormal.

[0011]

As described above, the test mode is to write the same data to a plurality of memory cells at the same time, read the same data at the same time, and determine whether or not it is operating normally. Due to the characteristics (the matching / mismatching method is used as the output method), the same data is written to all the write memory cells at the same time.

As described above, in the test mode, the data pattern at the time of writing can be limited due to the characteristics of the function, and the detection power is lost due to the data pattern dependency defect which has become dominant in recent DRAM failures. I had to rely on tests in normal mode.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a semiconductor memory device capable of performing writing with a special data pattern even in a test mode.

[0014]

SUMMARY OF THE INVENTION The present invention provides a plurality of memory cell sub-arrays including a memory cell comprising a capacitor for storing information and a transistor for transmitting information, and a memory for inputting predetermined data to the memory cell sub-array. A data input unit, a data output unit for reading data from the memory cell sub-array, and a second unit for converting data to be written from the data input unit to the plurality of memory cell sub-arrays into desired data when writing in the test mode. It is characterized by having one data conversion means and a second data conversion means for converting data read from a plurality of memory cell sub-arrays into desired data when reading in the test mode. Since the semiconductor memory device according to the present invention has the first and second data means in the predetermined memory cell sub-array, it is possible to execute the test mode with data other than a uniform data pattern.

[0015]

Next, an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 3 shows a schematic diagram according to the present invention. As shown in FIG. 3, in the present embodiment, a plurality of memory cell sub-arrays 301 including memory cells, a data input unit, a data output unit, a data conversion circuit 303,
310.

The data input means is a data conversion means 3
, The data output means is connected to the memory cell sub-array 301 via the data conversion means 310,
Connected to memory cell sub-array 301.

The schematic diagram of FIG. 3 is shown in more detail in FIG. However, a circuit corresponding to the normal mode for performing normal read, write, and refresh operations is not directly related to the present invention, and thus is omitted, and only circuit components used in the test mode are shown. Here, FIG.
4 shows an example of a 2M × 8-bit DRAM, assuming that the memory cell sub-array 301 of FIG.

As shown in the figure, the output means includes AND gates 320 to 328, OR gates 330 to 338, NA
It comprises an ND gate 340. Next, the operation in the test mode will be described with reference to FIG.

First, the switch SW1 is connected to the test mode side, and the data for the test mode is written to the memory cell sub-array 301 via the data conversion circuit 303. At this time, the data to be written is converted by the data conversion circuit 303 (details will be described later).

Next, the data written in the memory cell sub-array 301 is returned to the original data via the data conversion circuit 310, and the data is transferred to the output means. By determining the match / mismatch of this output data, this DR
A test is performed to determine whether reading and writing of AM is performed normally.

FIG. 5 shows the details of the data conversion circuit. As shown in FIG. 5, the data conversion circuit 303
Is provided for every other memory cell sub-array 301, and the data conversion means 310 is also formed of an inverter, and is connected to the memory cell sub-array 301.

In the test mode using the circuit shown in FIG. 5, the data written in the memory cell sub-array 301 is not all the same as in the prior art. For example, when the input data for test is “1”, “0”, “1”, “0”,
"1", "0"... Are written. Further, as shown in FIG. 6, the data conversion circuit 310 is provided continuously in the memory cell sub-array 301, May not be provided. That is, the arrangement density of the data conversion circuit 310 may be made uniform.

As described above, according to the present invention, in the test mode, a special data pattern can be written in all the memory cell sub-arrays 301. Therefore, similarly to the normal mode, there is a possibility that a defect depending on the data pattern can be detected. Higher and the test reliability can be improved. Further, since the present invention uses an inverter for the data conversion circuit 303, the circuit configuration is simple, and a CMOS inverter consumes less power.

[0024]

As described above, according to the present invention, a special data pattern can be written to all the memory cell sub-arrays 301 in the test mode, thereby improving test reliability. Can be done.

[Brief description of the drawings]

FIG. 1 is a diagram showing an entire conventional 16 Mbit DRAM.

FIG. 2 is a diagram showing a circuit configuration of a portion used in a conventional test mode.

FIG. 3 is a schematic configuration diagram used in a test mode according to the present invention.

FIG. 4 is a detailed circuit diagram used in a test mode according to the present invention.

FIG. 5 is a diagram showing a first embodiment according to the present invention.

FIG. 6 is a diagram showing a first embodiment according to the present invention.

[Explanation of symbols]

 SW1 switch 301 Memory cell sub-array 303, 310 Data conversion means 320-328 AND gate 330-338 OR gate 340 NAND gate

Claims (6)

[Claims] 1. A semiconductor memory device having a normal mode for performing normal reading, writing and refreshing, and a test mode for simultaneously testing a plurality of bits, wherein a memory comprising a capacitor for storing information and a transistor for transmitting information A plurality of memory cell sub-arrays including cells, a first memory cell connected to the memory cell sub-array, and a first memory for converting data to be written to the plurality of memory cell sub-arrays into desired data when writing in the test mode. Data conversion means, connected to the first data conversion means, data input means for inputting predetermined data to the memory cell sub-array, connected to the memory cell sub-array, when reading out the test mode, Data read from multiple memory cell sub-arrays A second data conversion means for converting the data into desired data; and a data output means connected to the second data conversion means for outputting data from the memory cell sub-array. Semiconductor storage device. 2. A semiconductor memory device having a normal mode in which normal reading, writing, and refreshing operations are performed and a test mode in which a plurality of bits are tested at the same time, a memory comprising a capacitor for storing information and a transistor for transmitting information. A plurality of memory cell sub-arrays including cells; and a memory which is connected to a predetermined memory cell sub-array among the plurality of memory cell sub-arrays and which is to be written to the memory cell sub-array when writing in the test mode. A first data conversion unit for converting the data into a first data conversion unit, the first data conversion unit is connected to the memory cell sub-array connected to, when reading the test mode, the data read from the memory cell sub-array A second data converter for reverse conversion to desired data A semiconductor memory device comprising: a stage; data input means connected to the first data conversion means; and data output means connected to the second data conversion means. 3. A semiconductor memory device having a test mode for simultaneously testing a plurality of bits, comprising: a plurality of memory cell sub-arrays including a memory cell including a capacitor for storing information and a transistor for transmitting information; Among the memory cell sub-arrays, connected to a predetermined memory cell sub-array, and at the time of writing in the test mode, first data conversion means for converting data to be written into the memory cell sub-array into desired data, The first data conversion means is connected to the connected memory cell sub-array, and is used to convert data read from the memory cell sub-array based on desired data when reading out the test mode. Data conversion means, and write data connected to the first data conversion means. Data input means for inputting the data to the memory cell sub-array, and data output means connected to the second data conversion means for outputting read data from the memory cell sub-array. Semiconductor storage device. 4. The semiconductor memory device according to claim 1, wherein said first and second data conversion means are constituted by inverters. 5. The semiconductor device according to claim 1, wherein said first and second data conversion means connected to said predetermined memory cell sub-array are arranged so as to have a uniform arrangement density. Storage device. 6. The semiconductor memory device according to claim 5, wherein the first and second data conversion means connected to the predetermined memory cell sub-array are arranged every other one.