JPH1011982A - Non-volatile semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor memory device which assures high speed data read operation. SOLUTION: Two addresses are stored as the multi-value. Since the data of lower address among those in the page is defined after the first read operation is executed with the word line VWL1 , the data is output in serial from a 4-value/2-bit converting circuit 80 for the external side as the read operation and data is read with the word line voltages VWL0 , VWL2 in the inside while the lower digit data is output for the external side, in order to define the upper digit data of the address in the page and data of the upper digit side is output when address data of the lower digit side is output. Thereby, the virtual first access time can be reduced to realize high speed data read operation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-valued nonvolatile semiconductor memory device for recording data of at least three values in a memory cell.

[0002]

2. Description of the Related Art Conventionally, in a semiconductor nonvolatile storage device such as an EPROM or a flash memory, a binary memory in which data having two values of "0" and "1" is recorded in one memory cell transistor. Cell structure is usual. However, with the recent demand for increasing the capacity of the nonvolatile semiconductor memory device, at least three memory cell transistors are required.
A so-called multilevel nonvolatile semiconductor memory device that records data equal to or larger than a value has been proposed (for example, “A
Multi-Level 32Mb Flash Me
molly "'95 ISSCC p132-).

FIG. 9 shows a DINOR type flash memory in which one memory transistor has two bits.
Threshold voltage Vth when recording data having a value
FIG. 4 is a diagram illustrating a relationship between a level and data content.

In FIG. 9, the vertical axis represents the threshold voltage Vth of the memory transistor, and the horizontal axis represents the distribution frequency of the memory transistor. The content of 2-bit data constituting data to be recorded in one memory transistor is represented by [D2, D1], and [D2, D1] =
[1,1], [1,0], [0,1], [0,0]
State exists. That is, there are four states: data “0”, data “1”, data “2”, and data “3”.

[0005] NAND type and DINOR (DIvided)
In a NOR (Normal) type flash memory, rewriting and reading of data are performed in page units. In the case of a general NAND type or DINOR type flash memory,
The memory cell transistor is programmed from an erase state (data "3") to a first program state (data "2"), a second program state (data "1"), and a third program state (data "0") To do this, the write data is [1, 1] while the word line voltage (gate voltage V _G ) is set to a constant voltage, for example, −10V.
0], [0, 1], and [0, 0],
Specifically, for example, the bit line voltage (drain voltage V _D )
Is set to 6 V (gate voltage V _G = −10 V) to perform writing, and the threshold voltage Vth is shifted to distribution 10. At this time, the cell whose write data is [1, 1] has
Drain voltage V _D = 0V (gate voltage V _G = -10V)
Is added, but because of insufficient charge, the threshold voltage Vth
Does not transition (remains distribution 11). Next, writing is performed on cells whose write data is [0, 1] and [0, 0]. Finally, the write data is written to the cell at [0, 0], and the multi-level write is completed. Note that the write operation is performed by write verify.

At the time of reading, two terminals (I
Since the data of the (/ O) section is stored in one memory cell, first, the word line voltage is set to V _WL0 to perform reading, then the word line voltage is set to V _WL1 , and reading is performed.
Set to _WL2 and read. Then, the number of high levels in the read data performed three times is counted,
The count value (binary number) is expressed as IOm + 1 (D2), IO
m (D1) data. For example, when the high level is read twice as a result of the reading, since “2” is “10” in binary, it is determined to be distribution 10 and IOm +
"1" is output for 1 data, and "0" is output for IOm data. As described above, in the conventional read operation, in the case of four values (2 bits / cell), data read is performed after performing read three times.

[0007]

One application of the flash memory is to replace a hard disk. In the case of a multi-valued flash memory such as a NAND type or a DINOR type that rewrites data in units of pages, the hard disk is not used. Substitution is the optimal application. The following two can be cited as specifications expected of a flash memory used for such a purpose. Random access need not be fast. Serial access needs to be fast.

However, in the above-described multi-valued flash memory, no data is output unless reading is performed three times at the time of reading, and the access time of the first address of serial access is shorter than that of the binary-type flash memory. Becomes longer, and the usability becomes worse as compared with a binary flash memory.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a nonvolatile semiconductor memory device capable of increasing the speed of reading data at the first address of serial access.

[0010]

In order to achieve the above object, the present invention relates to a nonvolatile semiconductor memory device for storing multi-valued data of three or more values in a memory cell, the multi-valued data being stored in a plurality of addresses of different addresses. Writing means for storing bit data in one memory cell; and storing data consisting of the plurality of bits defined on an upper bit side and a lower bit side, and at the time of reading, one of an upper bit and a lower bit. And reading means for reading and outputting the bit-side data and reading the other bit-side data during the output period.

According to the nonvolatile semiconductor memory device of the present invention, the multi-value data is stored in one memory cell as a plurality of bits of data at different addresses by the writing means. Then, at the time of reading, for example, after reading the upper bit with the upper bit side as the lower address side, while the data is serially output, the lower bit side is read, and the output of the upper bit side is output. After completion, the lower bits are output. Thereby, the time until the output of the first data of the serial read can be shortened.

[0012]

FIG. 1 is a circuit diagram showing one embodiment of a nonvolatile semiconductor memory device according to the present invention. FIG.
Shows a circuit example of the DINOR type flash memory 1 employing the folded bit line system, and shows only a detailed configuration of one column for simplification of description and drawings, and shows a detailed configuration of other columns. It is omitted because it has the same configuration.

This DINOR type flash memory 1 has
Precharge circuit 10, n-channel MOS (NMOS)
Pre-charge transfer gate 11 composed of a transistor
L, 11R, DINOR type memory cell block 20L,
20R, dummy memory cell blocks 21L, 21R, N
Switching gate 30 composed of a MOS transistor
L, 30R, 31L, 31R, 32L, 32R,
Amplifier 40 (SA1 0), 41 (SA1 1), 4
2 (SA1 2), a switch composed of NMOS transistors
Switching gates 50L, 50R, 51L, 51R, 52
L, 52R, supply connection lines 60L, 60R, 61L, 61
R, 62L, 62R, the second sense amplifier 70 (SA2
0), 71 (SA2 1), 72 (SA2 2) 4 values
/ 2 bit conversion circuit 80 and control circuit 90.
Has been established.

BLL and BLR indicate bit lines forming a pair, and memory cell block 20L and dummy memory cell block 21L are connected to bit line BLL, and memory cell block 20R and dummy memory cell block 21R are connected to bit line BLR. Have been. Bit line B
One ends of LL and BLR are connected to the precharge circuit 10 via transfer gates 11L and 11R whose gates are connected to a supply line for the bit line precharge signal PCBL. The other end of the bit line BLL is branched into three branch bit lines BL0L, BL1L and BL2L, and the other end of the bit line BLR is branched into three branch bit lines BL0R and BL0.
It branches into 1R and BL2R.

The branch bit lines BL0L and BL0R are
The gate electrodes are connected to the first sense amplifier 40 via the switching gates 30L and 30R connected to the supply lines of the signals SBL0L and SBL0R, respectively. The branch bit lines BL1L and BL1R are connected to the first sense amplifier 41 via switching gates 31L and 31R whose gate electrodes are connected to supply lines for the signals SBL1L and SBL1R, respectively. The gate electrodes of the branch bit lines BL2L and BL2R have signals SBL2L and SBL2L, respectively.
Switching gate 3 connected to the supply line of SBL2R
It is connected to the first sense amplifier 42 via 2L and 32R.

The two output lines 40L of the first sense amplifier 40,
40R is the gate electrode whose signal Y1 Common to 00 supply line
Via the connected switching gates 50L, 50R,
Connection line 6 connected to two input lines of second sense amplifier 70
0L, 60R. First sense amplifier 41
The two output lines 41L and 41R have a gate electrode connected to the signal Y1. 1
Switching gate 51 commonly connected to the 0 supply line
L, 51R to two input lines of the second sense amplifier 71
It is connected to the connected connection lines 61L and 61R. No.
The two output lines 42L and 42R of the two sense amplifier 40
Electrode Y is the signal Y1 Switches connected in common to the
Via the switching gates 52L and 52R, the second sense amplifier
Connection lines 62L and 62R connected to the two input lines of the
It is connected. Then, the second sense amplifiers 70 and 7
1,72 output lines 70_OUT, 71_OUT, 72_OUTIs 4 values
Input terminals SA0, SA1, S of the / 2 bit conversion circuit 80
A2.

The memory cell blocks 20L and 20R and the dummy memory cell blocks 21L and 21R are configured, for example, as shown in FIG. That is, the memory cell block 20L includes the enhancement type transistor ET.
And a depletion type transistor DT are connected in series, and a drain of the enhancement type transistor ET is connected in cascade with the select gate 20LS connected to the bit line BLL, and a sub-bit line SB
The memory cell is constituted by four memory cell transistors (hereinafter, memory cells) M21L to M24L connected to LL. The memory cell block 20R includes a depletion type transistor DT and an enhancement type transistor E
T is connected in series, and the depletion type transistor D
A select gate 20RS whose drain to T is connected to the bit line BLR, and four memory cells M connected in cascade to the select gate 20RS and connected to the sub-bit line SBLR.
21R to M24R.

Select gate 2 of memory cell block 20L
0LS and the selection gate 20 of the memory cell block 20R.
RS is connected to a common selection signal supply line SG1A, SG1B. Specifically, the gates of one enhancement transistor ET and the other depression transistor DT are connected to a common selection signal supply line.

The gate of the memory cell M21L of the memory cell block 20L is connected to the common word line WL1 together with the gate of the memory cell M21R of the memory cell block 20R.
The gate of the memory cell M22L is connected to the common word line WL2 together with the gate of the memory cell M22R, and the gate of the memory cell M23L is connected to the memory cell M23R.
Is connected to a common word line WL3, and the gate of the memory cell M24L is connected to a common word line WL4 together with the gate of the memory cell M24R.

Dummy memory cell blocks 21L, 21R
Are configured similarly to the memory cell blocks 20L and 20R. That is, the dummy memory cell block 21L is
A selection gate 21LSD and a selection gate 21LS in which the enhancement transistor ET and the depression transistor DT are connected in series, and the drain of the enhancement transistor ET is connected to the bit line BLL.
D and cascade-connected to D and four dummy memory cells M21LD to M24LD connected to the sub-bit line SBLLD. Dummy memory cell block 21R
A selection gate 21RSD in which a depletion type transistor DT and an enhancement type transistor ET are connected in series, and a drain of the depletion type transistor DT is connected to a bit line BLR;
Four dummy memory cells M21RD to M24RD cascaded to SD and connected to sub-bit line SBLRD
It consists of.

The dummy memory cell block 21L
Select gate 21LSD and memory cell block 21R
Are connected to a common dummy selection signal supply line DSG1A, DSG1B. Specifically, the gates of one enhancement transistor ET and the other depression transistor DT are connected to a common dummy selection signal supply line.

Further, the dummy memory cell block 21L
Of the dummy memory cell M21LD is connected to the common dummy word line DWL1 together with the gate of the dummy memory cell M21RD of the dummy memory cell block 21R.
The gate of the dummy memory cell M22LD is shared with the gate of the dummy memory cell M22RD by a common dummy word line DW.
L2, the gate of the dummy memory cell M23LD is connected to the common dummy word line DWL3 together with the gate of the dummy memory cell M23RD.
The gate of 24LD is connected to the common word line DWL4 together with the gate of the dummy memory cell M24RD.

Each of the memory cells M21L to M24L, M21
The control circuit 90 stores n-bit multi-value data of different addresses in R to M24R. In the present embodiment, data of two addresses is converted into multi-valued data and stored. That is, the data to be multi-valued is the same as in the case of FIG.
The data of the address is multi-valued, and the data of the lower address of the address in the page is defined as being larger or smaller than V _WL1 , and the data of the upper address of the address in the page is V
Defined as greater than or less than _WL0 , or greater than or less than _VWL2 . For example, if one page is 2m Col × x bits and the start address of the selected page is An, the data stored in each cell is “An + i (i: 0 ≦ i <m) and A
n + m + i ".

When accessing the memory cell of the memory cell block 20L connected to the bit line BLL, the dummy memory cell block 21R connected to the bit line BLR is selected and used as a reference, and the bit line BLR is used. Cell block 2 connected to
To access the 0R memory cell, the bit line B
The dummy memory cell block 21L connected to LL is selected and used as a reference.

As shown in FIG. 3, the first sense amplifiers 40, 41, 42 are provided with so-called CMOS inverters I1, I2.
It is composed of a latch (flip-flop) type in which two inputs and outputs are cross-coupled. The connection midpoint between the sources of the p-channel MOS (PMOS) transistors P1 and P2 of each of the sense amplifiers 40 to 42 is connected to a common drive signal supply line VSAH0 (to 2), respectively.
The midpoint of connection between the sources of the S transistors N1 and N2 is connected to a common drive signal supply line VSAL0 (（2). 2 which is the output of each of the sense amplifiers 40 to 42
Storage nodes ND1 and ND2 are connected to branch bit line pair BL
0 (~ 2) L, BL0 (~ 2) R and 40 (~ 42)
L, 40 (to 42) R.

As the second sense amplifiers 70, 71 and 72, for example, a current mirror type is used.

FIG. 4 shows the second sense amplifier 70 (71, 7).
It is a circuit diagram which shows the specific structural example of 2). As shown in FIG. 4, the second sense amplifier 70 includes NMOS transistors NT1 to NT4 and a PMOS transistor PT.
1 to PT3.

The sources of the PMOS transistors PT1 and PT2 are connected to the supply line of the power supply voltage V _CC , and the drain of the PMOS transistor PT1 is connected to the NMOS transistor NT
1 is connected to the gates of the PMOS transistors PT1 and PT2 and the gate of the NMOS transistor NT3. The sources of the NMOS transistors NT1 and NT2 are connected to each other, and the NMOS transistors NT3 and NT2 are connected between the connection point and the ground.
4 are connected in series. The drain of the PMOS transistor PT2 is connected to the drain of the NMOS transistor NT2, and the connection point is connected to the output line 70 _OUT . The gate of the NMOS transistor NT1 is connected to the connection line 60L, and the gate of the NMOS transistor NT2 is connected to the connection line 60R. Further, an equalizing PMO is provided between the connection lines 60L and 60R.
An S transistor PT3 is connected, and the gate of the PMOS transistor PT3 and the NMOS transistor NT
4 are connected to the supply line of the signal Y2n (0 to 2). In this circuit, the PMOS transistors PT1 and P1
T2 forms a current mirror circuit, and PMOS transistors PT1 and PT2 and NMOS transistors NT1 to NT4 form a differential amplifier AMP.

In the second sense amplifier 70 having such a configuration, first, the signal Y2n is set to an inactive low level. Thus, the gate levels of the NMOS transistors NT1 and NT2 as the input terminals of the differential amplifier AMP are equalized. Second sense amplifier 7
When activating 0, the signal Y2n is set to the active high level. As a result, the NMOS transistor NT4 becomes conductive. As a result, the differential amplifier A
MP, two input signals are differentially amplified, and a differential amplifier A
A signal having a predetermined level is output from MP to the 4-level / 2-bit conversion circuit 80 via the output line 70 _OUT .

When the signal S _Amul by the control circuit 90 is input at a low level at the time of reading data, the quaternary / 2-bit conversion circuit 80 outputs the address of the memory designated as the output signal of the second sense amplifier 71. Output the lower data of the read multi-value data stored in the cell,
When the signal S _Amul is input at a high level, the second
From the signals sequentially output from the sense amplifiers 70 and 72, the higher-order data of the multi-valued data is determined and output. In this embodiment, since two addresses are multivalued,
As will be described later, after the first read is performed with the word line voltage _VWL1 , the data of the lower address is determined. Therefore, when the signal S _Amul is inputted at a low level, the _quaternary / 2-bit conversion circuit 80 reads the multi-valued read data stored in the addressed memory cell which is the output signal of the second sense amplifier 71. The data on the lower side of the data is output as it is.

FIG. 5 is a circuit diagram showing a configuration example of the quaternary / 2-bit conversion circuit 80. As shown in FIG. 5, the quaternary / 2-bit conversion circuit 80 includes a two-input OR gate 801,
802, 803, a two-input NAND gate 804, an inverter 805, and transfer gates 806 and 807 connecting the sources and drains of a PMOS transistor and an NMOS transistor.

One input terminal of the OR gate 801 is connected to the second
The other input terminal is connected to the input terminal SA0 connected to the output line 70 _OUT of the sense amplifier 70, and the NAND gate 8
04 is connected to the output terminal. NAND Gate 804
The two input terminals of the NOR gate 803 are connected to an input terminal SA1 connected to an output line 71 _OUT of the second sense amplifier 71 and an input terminal SA2 connected to an output line 72 _OUT of the second sense amplifier 72, respectively. OR gate 8
02 has one input terminal connected to the output terminal of the OR gate 801, the other input terminal connected to the output terminal of the OR gate 803, and the output terminal connected to one input / output terminal of the transfer gate 806. One input / output terminal of the transfer gate 807 is connected to the input terminal SA1. The other input / output terminals of the transfer gates 806 and 807 are connected to the output terminal IOi. Further, the input terminal Am
ul is the input terminal of the inverter 805, the transfer gate 806
Of the NMOS transistor N806, and the gate of the PMOS transistor P807 of the transfer gate 807. The output terminal of the inverter 805 is connected to the PMOS transistor P806 of the transfer gate 806.
And the gate of the NMOS transistor N807 of the transfer gate 807.

In the 4-level / 2-bit conversion circuit 80, when the signal S _Amul is input at a low level, the transfer gate 80
7 is kept conductive and the transfer gate 806 is kept non-conductive. As a result, the output signal of the second sense amplifier 71 input to the input terminal SA1 is directly transmitted to the output terminal IOi via the transfer gate 807. On the other hand, the signal S _Amul
Is input at a high level, the transfer gate 806 is kept conductive and the transfer gate 807 is kept non-conductive. As a result, the output signal of the second sense amplifier 70 input to the input terminal SA0 and the output signal of the second sense amplifier 72 input to the input terminal SA2 are the result of the logical operation by the NAND gate 804 and the OR gates 801 and 803. Is transmitted to the output terminal IOi via the transfer gate 806.

FIG. 6 shows the correspondence between the input of the quaternary / 2-bit conversion circuit 80 and the decimal and binary representations as the output result. As shown in FIG.
When the input of 0, SA1, and SA2 is “000”, the multi-valued data is “00” in binary, “001” is “01” in binary, and “011” is “10” in binary. , "1
In the case of "11", it is "11" in binary.

The control circuit 90 writes the n-bit multi-valued data of a different address to each memory cell and reads out the multi-valued data stored in the addressed memory cell. 2 selection signal supply lines, etc.), the drive signal supply lines VSAH0 to VSAH2, VSAL0 to VS1 of the first sense amplifiers 40 to 42.
AL2 level and timing control, level and timing control of signals Y2n (0-2) for second sense amplifiers 70-72, switching gates 30L-32L,
0R-32R signals SBL0L-SBL2L, SBL0
Signal Y1 for R to SBL2R, 50L to 52L, 50R to 52R 10 to Y1 1n, Y1 00 to Y1 0n level and timing control, and signal S _Amul level and timing control.

In setting the threshold voltage Vth of data at the time of writing, first, it is determined whether the data of the low address An + i is above or below the voltage _VWL1 shown in FIG. Thereafter, the voltage V _{WL0 is determined} by the data of An + i and An + m + i.
Or, determine whether it is above or below V _WL2 . For example, An
+ I data is “1”, An + m + i data is “0”
In this case, the control circuit 90 controls the voltage and the like so that the distribution 10 is obtained.

At the time of reading, first, the word line voltage addressed is set to V _WL1 and reading is performed.
Read data is input to the first sense amplifier 41.
Next, the signal is input to the 4-value / 2-bit conversion circuit 80 through the second sense amplifier 71. At this time, the data read to the sense amplifier is the data of the addresses An to An + m-1, and the data can be serially output at this time. At this time, the signal S _Amul is set to a low level. During the serial output, the word line voltage is changed to V _WL0 ,
After each reading is performed by sequentially setting V _WL2 , the signal S _Amul is set to the high level, and the four-value / 2-bit conversion circuit 80 includes the reading result when the word line voltage is V _WL1. To count the number of "1". In this case, the lower one bit is the address An + m to An + 2m
-1. In a normal configuration (a page is 1K or more), while outputting data of An to An + m-1, A
The internal reading of the data of n + m to An + 2m-1 is sufficiently long, and the continuous serial output of the data of An to An + 2m-1 is possible.

FIG. 7 shows the relationship between multi-value data (for one page), word line voltages V _WL1 , V _WL0 , V _WL2 and signal S _Amul . Note that the four-value / 2-bit conversion circuit 80
mul is the highest address in the page.

Next, the data read operation of the above configuration will be described with reference to the timing chart of FIG.

For example, when reading data stored in the memory cell M21L of the memory cell block 20L connected to the bit line BLL, first, the precharge signal PCBL is set to a high level for a certain period. As a result, the transfer gates 11L and 11R become conductive, and
The precharge circuit 10 precharges the bit line BLL and the bit line BLR to about V _CC / 2.

After that, the selection signal supply line SG1B is set to the high level, and the voltage of the word line _WL1 is set to V _WL1 . As a result, the memory cell M21L connected to the bit line BLL is selected. At the same time, the dummy selection signal supply line DSG1A and the dummy word line DWL1 are set to the high level, and the dummy cell M21RD connected to the bit line BLR is selected. Further, the word line voltage is set to V
_At the same timing set in _WL1 , signals SBL1L, SBL1
BL1R is set to the high level, and the switching gates 31L and 31R are kept conductive. For a predetermined time after the word line voltage is set to V _WL1 , the sense amplifier driving signal lines VSAH0-2 and VSAL0-2 are both at V _CC.
/ 2 approximately although the level is held in, after a predetermined time has elapsed, VSAH1 the power supply voltage V _CC, VSAL1 becomes the ground level GND. Thus, the memory cell M21
Data read from L to the bit line BLL is input to the first sense amplifier 41, and is complementarily latched and amplified to a level corresponding to the potential of the bit lines BLL and BLR. The data read by the first sense amplifier 41 is data on the lower address side of one page.

Next, the word line WL1 and the signal SBL1
After the level of L, SBL1R is set to low level,
Signal Y1 10 is set to the high level, and the switching gates 51L and 51R are kept conductive. Thus, the complementary data latched by the first sense amplifier 41 is input to the second sense amplifier 71. And the signal Y
2 1 is input to the second sense amplifier 71, the input data is amplified by the second sense amplifier 71, and output to the 4-level / 2-bit conversion circuit 80. At this time, the signal S _Amul is set to the low level, and the quaternary / 2-bit conversion circuit 8
From 0, the output data of the second sense amplifier 71 is serially output from the output terminal IOi as it is.

That is, in the operation related to the data output after reading at the word line voltage _VWL1 , the column address (in-page address) Col Adr is sequentially changed from the outside, and the signal Y1-1j (0 ≦ j ≦
m-1) are sequentially changed, and at the same time, the second sense amplifier 71 is activated, and the data is sequentially output through the 4-level / 2-bit conversion circuit 80.

During this period, after the word line voltage is internally switched from V _WL1 to low level, the precharge signal PCBL is set to high level for a certain period,
The bit lines BLL and BLR are precharged, and data is read at the word line voltage _VWL0 . In this case, as described above, the switching gates 30L,
The read data is stored in the first sense amplifier 40 while the 30R is controlled to be conductive. Next, after the word line voltage is switched from V _WL0 to low level, the precharge signal PCBL is set to high level for a certain period, and the bit lines BLL and BLR are precharged, and the word line voltage V _WL2 is used. Data reading is performed. In this case, the switching gates 32 </ b> L and 32 </ b> R are controlled to be conductive, and the read data is stored in the first sense amplifier 42. Then, at the timing when the data output on the lower side of the address within the page is completed, the signal S _Amul is switched to the high level, and the column address Y1 is set. 1n, Y1 0
n is switched. At this time, the data latched by the first sense amplifiers 40 to 42 selected by the column address is passed through the second sense amplifiers 70 to 72 to generate four-value /
The data is input to the 2-bit conversion circuit 80, and the arithmetic processing is performed each time, and the upper data is output from the output terminal IOi.

As described above, after reading and latching the low address side in one page in the first access, while the data is serially output, the first data is read by performing the read twice. The time until output is one reading time, and one page of serial access is possible without any break.

For example, when the capacity is 64M bits and the number of bit lines is 8K, the read system (three sense amplifiers (S
/ A) is 4K, and there are 4K data after reading at the voltage V _WL1 . When the IO configuration is a × 8 configuration, the time required to output this is 25 ns × 4K / 8 = 12.8 when the serial access time is 25 ns.
μs, and if two readings are completed during this time, the upper data can be output continuously. If the time required for data output of the lower address is shorter than the time required for reading twice, the first access time (1st Acc
If the ess time is longer than one reading time, continuous output of data for one page becomes possible.

As described above, according to the present embodiment, two addresses are converted into multi-valued values and stored. After the first read is performed at the word line voltage _VWL1 , the addresses are read out of the addresses in the page. Since the data of the lower address has been determined, the 4-value / 2-bit conversion circuit 8
0 is serially output as it is, and data is read out internally using the word line voltages V _WL0 and V _WL2 while outputting lower-order data to the outside. Is determined, and the data of the upper address is output when the data output of the lower address is completed. Therefore, the apparent first access time can be shortened and the data reading speed can be increased. There is.

When the present invention is applied to a flash memory such as DINOR which performs reading / writing in page units as in the present embodiment, the NOR type has a larger cell current than the NAND type and has a higher speed. μs order)
Therefore, after the first reading, while the data is being serially output, the two readings are completed, and the data can be output continuously. That is, data can be output without waiting time after the first reading.

[0049]

As described above, according to the present invention,
There is an advantage that the apparent first access time can be shortened and the data reading speed can be increased.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of a nonvolatile semiconductor memory device according to the present invention.

FIG. 2 is a circuit diagram showing a configuration example of a memory cell block and a dummy cell block according to the present invention.

FIG. 3 is a circuit diagram showing a configuration example of a first sense amplifier according to the present invention.

FIG. 4 is a circuit diagram showing a configuration example of a second sense amplifier according to the present invention.

FIG. 5 is a circuit diagram showing a configuration example of a 4-level / 2-bit conversion circuit according to the present invention.

FIG. 6 is a diagram showing a correspondence relationship between a decimal number display and a binary number display as an input result and an output result of the quaternary / 2-bit conversion circuit according to the present invention.

FIG. 7 shows multi-level data (for one page) and word line voltage V
_WL1, is a diagram showing a relationship between V _WL0, V _WL2 and signal S _Amul.

FIG. 8 is a timing chart for explaining the operation of the circuit of FIG. 1;

FIG. 9 is a diagram showing a relationship between a threshold voltage Vth level and data content when data of two bits and having four values is recorded in one memory transistor in a NAND flash memory.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... DINOR type flash memory, 10 ... Precharge circuit, 11L, 11R ... Precharge transfer gate,
20L, 20R ... DINOR type memory cell block, 2
1L, 21R: dummy memory cell block, 30L, 3
0R, 31L, 31R, 32L, 32R ... switching gate, 40 (SA1 0), 41 (SA1 1), 4
2 (SA1 2) First sense amplifier, 50L, 50
R, 51L, 51R, 52L, 52R ... switching gate, 70 (SA2 0), 71 (SA2 1), 72
(SA2 2)... Second sense amplifier, 80... Four-value / 2-bit conversion circuit, 90.

Claims (3)

[Claims] 1. A non-volatile semiconductor memory device for storing multi-valued data of three or more values in a memory cell, comprising: writing means for storing the multi-valued data in one memory cell as a plurality of bits of data at different addresses; The stored data composed of the plurality of bits is defined as the upper bit side and the lower bit side, and at the time of reading, one of the upper bit or the lower bit is read and output, and the output period is set. A non-volatile semiconductor memory device having therein a reading means for reading the other bit-side data. 2. The nonvolatile semiconductor memory device according to claim 1, wherein said upper bit side is a lower address side. 3. The memory cell according to claim 1, wherein the amount of charge stored in the charge storage unit changes according to the voltage applied to the word line and the bit line, and the threshold voltage changes according to the change.
At the time of reading, the read means comprises a transistor for outputting data based on the word line voltage and the accumulated charge amount to the bit line, and the reading means comprises a different word line voltage corresponding to the threshold voltage on the upper bit side and the lower bit side, respectively. 2. The non-volatile semiconductor memory device according to claim 1, wherein the setting voltage is sequentially applied to the word line to output the data of the memory cell transistor to the bit line.