JPH10117270A - Photoelectric converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To uniformize a capacitance of crossing parts between signal wires and a stray capacitance. SOLUTION: Optical sensors 10a-i are divided into three blocks (10a-c, 10d-f, 10g-i). Storage capacitors 14a-i store charges corresponding to an incident luminous quantity. Switching transistors(TRs) 140a-i extract charges of the storage capacitors 14a-i in the lump in the unit of blocks. Outputs of the TRs 140a-c, 140g-i are connected respectively to common signal lines 18-22 and outputs of the TRs 140d-f are respectively connected to common signal lines 22-18. A shift register 142 makes switching TRs 42-46 conductive in this order with respect to blocks of the optical sensors 10a-c, 10g-i and makes switching TRs 42-46 conductive in the order reverse to that of the above, with respect to the block of the optical sensors 10d-f.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a photoelectric conversion device, and more particularly, to a photoelectric conversion device used for an image reading device such as a facsimile device and a digital copying machine.

[0002]

2. Description of the Related Art A conventional structure of a photoelectric conversion device used in an image reading device such as a facsimile device and a digital copying machine will be briefly described. FIG. 4 shows a circuit diagram of an optical sensor array having nine optical sensors.

In FIG. 1, optical sensors 10a to 10i are provided.
Are three (10a to 10c, 10d to 10f, 10g to
10i) constitutes one block, and three blocks constitute an optical sensor array. One terminal of each of the optical sensors 10a to 10i is connected to the power supply 12, the other terminal is connected to the ground via the storage capacitors 14a to 14i, and the switching transistors 16a to 16i and the common signal line 18 for each block. , 20, 22.

Switching transistors 16a, 16
d and 16g are connected to the common signal line 18,
The transistors 16b, 16e, and 16h are connected to the common signal line 20.
To the switching transistors 16c, 16c.
f, 16i are connected to the common signal line 22.

[0005] Of the three outputs of the shift register 24, the first output is the switching transistor 16a,
16b, 16c, and the second output is
The third output is connected to the gate electrodes of the switching transistors 16d, 16e, 16f, and the third output is connected to the gate electrodes of the switching transistors 16g, 16h, 16i. Thereby, the switching transistor 16a
16c, 16d to 16f, and 16g to 16i are simultaneously turned on in block units, and are turned on in the order of blocks according to the shift timing of the shift register 24.

The common signal lines 18, 20, 22 are connected to a common amplifier 32 via switching transistors 26, 28, 30, respectively. The three outputs of shift register 34 are connected to the gate electrodes of switching transistors 26, 28 and 30, respectively. The switching transistors 26, 28, 30 are sequentially turned on in accordance with the shift timing of the shift register 34.

The common signal lines 18, 20, 22 are grounded via load capacitors 36, 38, 40, respectively, and grounded via switching transistors 42, 44, 46, respectively. The capacity of the load capacitors 36 to 40 is
It is sufficiently larger than the capacitance of the storage capacitors 14a to 14i. The gate electrodes of the switching transistors 42 to 46 are commonly connected to a control terminal 48. Control terminal 48
Becomes high level, the switching transistors 42 to 46 are simultaneously turned on, and the common signal lines 18 to 22 are grounded.

The operation of the conventional example shown in FIG. 4 will be described with reference to FIG. FIG. 5 shows the switching transistor 16.
The timing charts of a to 16i, 26 to 30, and 42 to 46 are shown. 5 (a) shows the switching transistors 16a to 16c, FIG. 5 (b) shows the switching transistors 16d to 16f, FIG. 5 (c) shows the switching transistors 16g to 16i, FIG. ) Shows the timing of the switching transistor 28, (f) shows the timing of the switching transistor 30, and (g) shows the timing of the switching transistors 42 to 46, respectively. Switching transistor 1
It goes without saying that the ON states of 6a to 16i and 26 to 30 are the timings at which the associated outputs of the shift registers 24 and 34 go high.

When light enters the optical sensors 10a to 10i, electric charges are accumulated from the power supply 12 to the storage capacitors 14a to 14i according to the intensity of the incident light.

After charge storage, first, the shift register 24
Becomes high level, and as shown in FIG. 5A, the switching transistors 16a to 16c are turned on. Switching transistors 16a-1
6c is turned on, so that the storage capacitors 14a to 14c are turned on.
The electric charge accumulated in the switching transistors 16a to 16c and the common signal lines 18,
20 and 22 to the load capacitors 36, 38 and 40. Subsequently, the three outputs of the shift register 34 go high sequentially, and as shown in FIGS. 5D to 5F, the switching transistors 26, 28,
30 are sequentially turned on. As a result, the charges (light information of the first block) of the load capacitors 36 to 40 are sequentially read out and output to the outside via the amplifier 32.

When the information of the first block is read, a high-level voltage is applied to the control terminal 48, and FIG.
As shown in FIG.
To 46 are simultaneously turned on. As a result, the residual charges of the load capacitors 36 to 40 are completely discharged.

When the residual charge on the load capacitors 36-40 has been completely discharged, the shift register 24 shifts, and the second output goes high. As a result, as shown in FIG.
The switches d-16f are turned on, and the charges stored in the storage capacitors 14d-14f of the second block are transferred to the load capacitors 36-40. As in the case of the first block, as shown in FIGS.
By the shift of the register 34, the switching transistors 26 to 30 are sequentially turned on, and the load capacitor 3
The optical information of the second block stored in 6 to 40 is sequentially read.

The third block (storage capacitors 14g-1g)
4i) is similarly transferred (FIG. 5C).

FIG. 6 is a schematic sectional view of a photoelectric conversion section of a conventional photoelectric conversion device, and FIG. 7 is a schematic plan view thereof. In this conventional example, the photoelectric conversion element unit 5 is formed using a-Si: H.
The storage capacitor section 52, the TFT section 54, the matrix signal line section 56, the gate drive line section 58, and the like are integrally formed on the translucent insulating substrate 60 by the same process.

As shown in FIG. 6, a first conductive layer 62 made of Al, Cr, or the like
a first insulating layer 64 of iN or the like, a photoconductive semiconductor layer 66 of a-Si: H, an ohmic contact layer 68 of n + type a-Si: H, and a second layer of Al or Cr or the like.
Are stacked.

In the photoelectric conversion element section 50, main electrodes 72 (source electrode or drain electrode) and 74 (drain electrode or source electrode) are wired above the photoconductive semiconductor layer 66. The incident light L is reflected by the original P, and the reflected light (signal light) L ′ changes the conductivity of the photoconductive semiconductor layer 66,
The current flowing between the main electrodes 72 and 74 facing each other in a comb shape is changed. Note that the metal light-shielding layer 76 may be connected to an appropriate drive source to serve as a control electrode (gate electrode) facing the main electrodes 72 and 74. In FIG. 7, the sensor bias power supply is shown as a VS line.

The storage capacitor section 52 includes a lower electrode line 78.
The first insulating layer 64, the photoconductive semiconductor layer 66, and the ohmic contact layer 68 are sandwiched between the first insulating layer 64 and the upper electrode line 80. Reference numeral 82 (FIG. 6) denotes a contact hole for ohmic connection between the main electrode 74 of the photoelectric conversion unit 50 and the lower electrode line 78 of the storage capacitor unit 52. This configuration of the storage capacitor section 52 has a so-called MIS capacitor structure. Although either positive or negative bias can be used, stable capacitance and frequency characteristics can be obtained by always using the lower electrode line 78 in a negative bias state. In this conventional example, on the contrary, a high capacitance value per unit area is obtained by using the upper electrode line 80 in a state where it is always biased negatively.

The TFT section 54 includes a lower electrode line 84 serving as a gate electrode, an insulating layer 64 serving as a gate insulating layer, and a semiconductor layer 6.
6, an ohmic contact layer 68, an upper electrode line 86 as a source electrode, and an upper electrode line 88 as a drain electrode.

In the matrix signal line section 56, an insulating layer 64 covering the first conductive layer 62 to be an individual signal line 90 (FIG. 7), a semiconductor layer 66, an ohmic contact layer 68, The second conductive layers 92 serving as common signal lines intersecting with the individual signal lines 90 are sequentially stacked. 94
Is a contact hole for ohmic connection between the individual signal line 90 (conductive layer 62) and the common signal line (conductive layer 92). In addition, the individual signal lines and the common signal lines connected to the individual signal lines are generally referred to as signal lines.

In the TFT gate drive line portion 58, the substrate 60
The first conductive layer 62 that becomes the individual gate line 96, the insulating layer 64 that covers the conductive layer 62, the semiconductor layer 66, the ohmic contact layer 68, and the common gate line 98 that intersects with the individual gate line 96 Two conductive layers 70 are sequentially stacked.

As described above, the conventional photoelectric conversion device includes the photoelectric conversion element 50, the storage capacitor 52, and the TFT 5
4. Since the matrix signal line portion 56 and the gate drive line portion 58 all have a laminated structure of a photoconductive semiconductor layer, an insulating layer, a conductor layer, and the like, each portion is formed simultaneously by the same process.

Further, on the second conductive layer 70, a passivation layer 100 made of SiN or the like and a document P are mainly provided for the purpose of protecting and stabilizing the semiconductor layer surfaces of the photoelectric conversion element section 50 and the TFT section 54. Anti-friction layer 1 made of microsheet glass or the like that protects photoelectric conversion elements and the like from friction
12 are formed. An antistatic layer 114 (conductive layer) made of a light-transmitting conductive layer is formed between the passivation layer 100 and the friction layer 112. The static electricity countermeasure layer 114 is arranged to prevent static electricity generated by friction between the original P and the friction layer 112 from affecting the photoelectric conversion element and the like. The antistatic layer 114 is
Since it is necessary to transmit the illumination light L and the signal light L ′, I
An oxide semiconductor transparent conductive film such as TO is used.

In the conventional example, the anti-friction layer 112 having the antistatic layer 114 attached thereto is adhered to the passivation layer 100 with an adhesive 116, and the antistatic layer 114 is grounded.

Also, Japanese Patent Application Publication No. 1786 in 1985
A matrix wiring method as disclosed in JP-A-63-63 is also known. FIG. 8 shows a wiring plan view of the technique described in this publication. In this conventional example, only the matrix signal line section is different from the conventional example shown in FIG. The same components as those in FIG. 7 are denoted by the same reference numerals. The cross-sectional structure is the same as FIG. Matrix signal line section 56a
Thus, the individual signal line is extended beyond the contact hole 94 as shown by reference numeral 118. Although this extension is not necessary for the enemy, the dispersion of the stray capacitance of each signal line can be reduced by making all the individual signal lines the same length. Further, it is assumed that the line width and the line interval of each signal line are constant. This configuration is uniformly applied to all signal wirings and all blocks.

[0025]

However, in the conventional example shown in FIGS. 6 and 7, the matrix signal line portion 56 is not provided.
Since the lengths of the individual signal lines are different depending on which common signal line is connected, the stray capacitance of each signal line varies. As a result, when originals having the same density are read, variations occur in the signal output of 8.
When high-quality image processing such as gradation reading is performed, there is a problem that an image different from the original document density is obtained.

In the technique described in Japanese Patent Application Publication No. 178,661 in 1985, the dispersion of the stray capacitance is improved, but the individual signal lines are extended beyond the contact holes in the matrix signal line portion 56a. Accordingly, the area of the intersection between the common signal line and the individual signal line is greatly increased. As a result, the cross capacitance between each signal line is greatly increased, and the amount of crosstalk between each signal line is also increased, so that the image quality is significantly reduced.

For example, an A4 size original is set to 8 Pel / m
In order to read with m, 1,728 sensors are required, and when these are configured as a matrix of 24 × 72 blocks, 23 × 24 = 552 intersections are formed per block. Therefore, the number of all intersections is 552
× 72 = 39,744.

When this crosstalk is to be corrected by a method as disclosed in Japanese Patent Application Publication No. 183694/1993, a correction error occurs when the crosstalk amount of one signal line differs. However, there is a problem that the image quality is significantly reduced.

An object of the present invention is to provide a photoelectric conversion device that solves these problems.

[0030]

According to the present invention, there is provided a photoelectric conversion apparatus comprising: a plurality of optical sensors;
Switch means for sequentially taking out one block at a time,
Storage means for storing one block of signals taken out by the switch means;
Signal reading means for sequentially taking out signals for blocks,
A photoelectric conversion device having a matrix wiring means for connecting the storage means and the signal reading means, wherein the matrix wiring means is connected to the n-th (1)
≦ n ≦ M) and a block connecting the n-th common signal line to the n-th common signal line from the photosensor. It is characterized by having two types of blocks, and the two types of blocks have the same number or almost the same number.

As described above, the n-th (1 ≦ 1)
n ≦ M), and a block that connects the n-th individual signal line from the optical sensor and the (M−n + 1) -th common signal line. By making the number of blocks the same or almost the same,
The intersection capacitance and the stray capacitance between the signal lines can be made uniform without extending the individual signal lines after the connection point (contact portion). This makes it possible to obtain a uniform signal output without increasing the amount of crosstalk. Since the crosstalk amount becomes uniform, a higher quality signal can be reproduced by using a simple crosstalk correction method.

[0032]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a schematic plan view of a photoelectric conversion unit according to one embodiment of the present invention. Since it is the same as the conventional example shown in FIG. 7 except for the matrix signal line portion 56b, the same components as those shown in FIG.
The detailed description is also omitted. The cross-sectional structure is the same as FIG.

As shown in FIG. 1, in the matrix signal line section 56b of the present embodiment, in the block #n, the first individual signal line 120 is connected to the first common signal line 124 through the contact hole 40. . Similarly, the second individual signal line 122 is connected to the second common signal line 126 by a contact hole, and the m-th individual signal line is connected to the m-th common signal line. Conversely, in the next block # (n + 1), the first individual signal line 132 is connected to the m-th common signal line 130, and the second individual signal line 134 is connected to (m-
1) The common signal line 128 is connected to the m-th individual signal line 136 in the same manner.
24.

In this embodiment, the connection order of the individual signal lines and the common signal lines is reversed for each block. Then, such two types of blocks have the same number or almost the same number in one photoelectric conversion device. In this, the length of the individual signal line from the light sensor of the same arrangement of each block is
Since the same or almost the same for all the individual signal lines, the length of the individual signal lines can be adjusted uniformly without increasing the cross capacitance between the signal lines.

FIG. 2 shows a circuit diagram of an embodiment of the present invention applied to an optical sensor array having nine optical sensors similar to the conventional example (FIG. 4). FIG. 2 shows the storage capacitors 14a-1
The connection mode between the switching transistors 140a to 140i for extracting the charge signal of 4i and the common signal lines 18, 20, 22 is different from the conventional example, and accordingly, as will be described later, the switching transistors 26, 28, 30 The shift direction of the shift register 142 that controls on / off is different from that of the shift register 34. The other elements are exactly the same as in FIG. 4, and the same components are denoted by the same reference numerals.

In this embodiment, the switching transistors 140a, 140b, 140c and 140g,
Outputs of 0h and 140i are connected to common signal lines 18, 20, and 22, respectively, as in the conventional example. Outputs of switching transistors 140d, 140e, and 140f are conversely connected to common signal lines 22, 20, and 22, respectively. Connect to 18.

Switching transistors 140a-1
The gate electrode 40i is commonly connected to each block similarly to the conventional example, and the shift register 24
Are connected to the parallel output terminals. Therefore, the switching transistors 140a to 140i are sequentially turned on for each block according to the shift timing of the shift register 24.

FIG. 3 shows a timing chart of this embodiment. 3 (a) and 3 (a) show switching transistors 140a to 140c, FIG. 3 (b) shows switching transistors 140d to 140f, FIG. 3 (c) shows switching transistors 140g to 140i, and FIG. 3 (d) shows switching transistor 26. (E) is switching
Transistor 28, (f) is switching transistor 30, and (g) is switching transistor 42
To 46 are shown.

When light enters the optical sensors 10a to 10i, electric charges are accumulated in the storage capacitors 14a to 14i from the power supply 12 according to the intensity of the incident light.

After the charge accumulation, first, the shift register 24
Becomes high level, and as shown in FIG. 3A, the switching transistors 140a to 140c
Is turned on. Switching transistor 140
When the switches a through 140c are turned on, the charges stored in the storage capacitors 14a through 14c are transferred to the load capacitors 36, 140 through the switching transistors 140a through 140c and the common signal lines 18, 20, 22, respectively.
38, 40. Then, shift register 1
42 goes high in turn, and FIG.
As shown in (d) to (f), the switching transistors 26, 28, and 30 are sequentially turned on. As a result, the charges (light information of the first block) of the load capacitors 36 to 40 are sequentially read out and output to the outside via the amplifier 32.

When the information of the first block is read out, a high-level voltage is applied to the control terminal 48, and FIG.
As shown in FIG.
To 46 are simultaneously turned on. As a result, the residual charges of the load capacitors 36 to 40 are completely discharged. Up to this point, it is exactly the same as the conventional example.

When the residual charges in the load capacitors 36 to 40 are completely discharged, the shift register 24 shifts, and the second output goes high. As a result, as shown in FIG.
0d to 140f are turned on, and the charges stored in the storage capacitors 14d to 14f of the second block are:
The load capacitor 4 is connected via the common signal lines 22, 20, and 18.
0,38,36. Shift register 142
Shifts in the opposite direction to the case of the first block, and FIG.
As shown in (d) to (f), the switching transistors 30, 28, and 26 are turned on in this order. As a result, the optical information of the second block stored in the load capacitors 40, 38, and 36 is sequentially read in this order.

The third block (storage capacitors 14g-1g
4i), the shift register 142 shifts as in the case of the first block, and the load capacitors 36, 3
8, 40, switching transistors 26, 28, 3
0 and are taken out via the amplifier 32.

[0045]

As can be easily understood from the above description, according to the present invention, the capacitance at the intersection between signal lines (that is,
Without increasing the amount of crosstalk, the stray capacitance of each signal line can be made uniform, and thus the amount of crosstalk can be made uniform. Thus, a high-quality image reading device can be provided.

[Brief description of the drawings]

FIG. 1 is a schematic plan view of a photoelectric conversion unit according to an embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram of the present embodiment.

FIG. 3 is a timing chart of the circuit diagram shown in FIG. 2;

FIG. 4 is an equivalent circuit diagram of a conventional photoelectric conversion device.

FIG. 5 is a timing chart of a conventional example.

FIG. 6 is a schematic cross-sectional view of a photoelectric conversion unit of a conventional photoelectric conversion device.

FIG. 7 is a schematic plan view of a conventional photoelectric conversion unit.

FIG. 8 is a schematic plan view of another conventional photoelectric conversion unit.

[Explanation of symbols]

 10a to 10i: Optical sensor 12: Power supply 14a to 14i: Storage capacitor 16a to 16i: Switching transistor 18, 20, 22: Common signal line 24: Shift register 26, 28, 30: Switching transistor 32: Amplifier 34: Shift register 36, 38, 40: Load capacitor 42, 44, 46: Switching transistor 48: Control terminal 50: Photoelectric conversion element 52: Storage capacitor 54: TFT 56: Matrix signal line 56a: Matrix signal line Part 56b: Matrix signal line part 58: Gate drive line part 60: Translucent insulating substrate 62: Conductive layer 64: Insulating layer 66: Photoconductive semiconductor layer 68: Ohmic contact layer 70: Conductive layer 72, 74: Main electrode 76: Metal light-shielding layer 78: Lower electrode line 80: Upper layer Electrode line 82: Contact hole 84: Lower electrode line 86: Upper layer electrode line 88: Upper layer electrode line 90: Individual signal line 92: Conductive layer 94: Contact hole 96: Individual gate line 98: Common gate line 100: Passivation layer 112: anti-friction layer 114: antistatic layer (conductive layer) 116: adhesive 118: extension of individual signal line 120, 122: individual signal line 124, 126: common signal line 128, 130: common signal line 132, 134 , 136: individual signal lines 140a to 140i: switching transistor 142: shift register

Claims (1)

[Claims] 1. A plurality of optical sensors, switch means for sequentially taking out M output signals of the optical sensors as one block, accumulating means for accumulating one block of signals taken out by the switch means, A photoelectric conversion device comprising: signal readout means for sequentially taking out signals of one block stored in the means; and matrix wiring means for connecting the storage means and the signal readout means. A block connecting the n-th (1 ≦ n ≦ M) individual signal line from the sensor and the n-th common signal line, and the (M−n + 1) -th common communication with the n-th individual signal line from the optical sensor A photoelectric conversion device comprising two types of blocks for connecting to a signal line, and the two types of blocks have the same number or almost the same number.