JPH10116981A - Electronic device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize an extremely fine patterning exceeding a limit drastically by fabricating an electronic device using a surface level being formed in a band gap through a dangling bond or the like. SOLUTION: A conductive layer on the surface of a semiconductor substrate 1 is stripped by means of a scanning tunnel microscope while leaving only the parts corresponding to a quantum dot 2, a gate electrode 3, a source electrode 4 and a drain electrode 5 thus fabricating a single electronic transistor. The gap between the source electrode 4 and the quantum dot 2 and the gap between the drain electrode 5 and the quantum dot 2 are on the order of 1nm which allows tunneling of electrons. The number of electrons to be tunneled at one time depends on the voltage being applied between the source electrode 4 and the drain electrode 5. Current flowing between the source electrode 4 and the drain electrode 5 is controlled or switched by applying a voltage between the gate electrode 3 and the quantum dot 2 thereby varying the energy level in the quantum dot 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology for fabricating ultra-fine electronic devices in ultra-high density integrated circuit technology.

[0002]

2. Description of the Related Art Conventionally, electronic devices in the integrated circuit technology are formed on a semiconductor substrate by using a planar technology. Specifically, first, an oxide film is formed on the semiconductor surface,
A photosensitive agent pattern is formed at a predetermined location by photolithography. A desired electronic device is formed by repeating etching, impurity diffusion, metal deposition, and the like using this pattern to form a pn junction inside the semiconductor and to attach electrodes to the surface. Since the photolithography technique is used in the planar technique, it is possible to form a submicron microstructure.

[0003]

All of these electronic devices operate using the electrical properties of semiconductors, metals, and insulating bulks. As microfabrication progresses and the device size decreases, the quantum effect becomes larger. In addition, the influence of the tunnel phenomenon and the like cannot be ignored, and the device does not operate as an original electronic device. Further, in the electronic device according to the related art, there is also a limit of miniaturization due to deterioration of characteristics due to an essential variation (fluctuation) of a dopant concentration or the like due to miniaturization.

It is an object of the present invention to provide an electronic device capable of extremely miniaturizing which greatly exceeds this limit.

[0005]

SUMMARY OF THE INVENTION The electronic device of the present invention does not have a bulk electrical characteristic of a semiconductor or an insulator, but has an electric conduction through a surface level localized in one to several atomic layers on the surface thereof. Use In general, a surface state or an interface state exists at the outermost surface of a substance or at a steep interface between substances, and has electric characteristics different from those of a bulk. On the surface of semiconductors and insulators, surface levels due to dangling bonds and defects are formed in the forbidden band (band gap), and the surface has a more metallic electronic state. Therefore, the surface generally has good conductivity. To form a conductive surface.

The present invention focuses on the fact that such a level is localized in a very narrow region of one to several atoms near the surface, and forms an electronic device using this surface level. In this way, it is intended to make it possible to make the device extremely fine.

[0007]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 In this embodiment, an embodiment of an electronic device using surface levels of a semiconductor surface will be described. Generally, a large number of dangling bonds are present on a clean semiconductor surface, thereby forming metallic surface states in a bulk band gap. A scanning tunneling microscope (STM), which is a representative of a scanning probe microscope (SPM), applies a high voltage between the probe and the semiconductor surface, so that surface atoms that assume this surface state are applied. The layer can be easily peeled off, resulting in an insulating surface free of surface states. further,
By applying a voltage while moving the STM probe and processing unnecessary parts of the conductive surface into an insulating surface, an arbitrary pattern of the conductive surface having surface levels can be formed on the originally conductive surface. it can.

In this processing, an arbitrary scanning probe microscope (SPM) can be used, not limited to the application of a high voltage by the STM. For example, a probe of an atomic force microscope (AFM) can be made conductive so that an electric field, current or heat can be applied in the same manner as an STM. An AFM probe is an optical fiber, or a laser source is fixed to the tip of the probe. Thereby, light, electromagnetic waves or heat can be applied. And A
The FM probe can be brought into contact with the semiconductor surface by rubbing it. Further, in some cases, chemical reactions on the surface or introduced molecules induced by these operations may cause stripping of surface atoms, adsorption of oxygen, hydrogen, or other atoms that inactivate surface levels, or changes in surface structure. In addition, a method of inactivating the surface state can be used.

[0009] Conversely, on the surface where the dangling bonds of the surface are inactivated, for example, the hydrogen-terminated surface of silicon, the surface atoms are stripped or oxygen is removed by SPM in the same manner as described above. A method of activating surface states, such as stripping off hydrogen or other surface states that inactivate surface states, or changing the surface structure, for example, performing a process of restoring surface states by stripping off hydrogen atoms be able to. As a result, an arbitrary pattern of a conductive surface having surface levels can be formed on an originally insulating surface.

In this case, since the surface processed portion becomes a conductive surface, the above-mentioned method has a negative-positive relationship. The generalization of the above-described negative-positive conductive surface pattern formation technique is the same in the second and subsequent embodiments.

FIG. 1 shows an example of a single-electron transistor in which a conductive surface formed on a semiconductor surface by using this technique is used as an electrode. A single-electron transistor was formed by stripping the conductive layer on the surface of the semiconductor substrate 1 by STM and leaving only portions corresponding to the quantum, dots 2, gate electrode 3, source electrode 4, and drain electrode 5. The gap between the source electrode 4 and the quantum dot 2 and the gap between the drain electrode 5 and the quantum dot 2 are about 1 nm, and electrons can tunnel through those gaps. However, the quantum dot 2 is as small as about several nm in diameter or less (in principle, it can be as small as one elementary element). When electrons tunnel from the source electrode 4 to the quantum dot 2, the energy in the quantum dot 2 is reduced. Since this rises and the Coulomb blockade phenomenon occurs, no more electrons can tunnel from the source electrode 4 until the electron tunnels to the drain electrode 5.
The number of electrons that can be tunneled at one time is determined by the voltage applied between the source electrode 4 and the drain electrode 5. Here, by applying a voltage between the gate electrode 3 and the quantum dot 2, the energy level in the quantum dot 2 is changed to control the current flowing between the source electrode 4 and the drain electrode 5 or to perform switching. It is possible to do.

FIG. 1 shows a case where all the parts other than the necessary electrodes are formed into an insulating surface. However, as long as the performance of the element is not reduced, the number of the insulating surfaces is reduced, and a conductive surface is left other than the electrode part. It is also possible. In FIG. 1, a portion indicated by reference numeral 13 indicates a conductive surface left except for the electrode portion. In this case, it is natural that the electrode is separated from the electrode by about 2 to 5 nm so as not to adversely affect the original operation. When the conductive surface is to be left other than the electrode portion as described above, the electronic device can be formed by processing only the periphery of the electrode portion with the SPM probe, so that the manufacturing time can be reduced.

When the surface state of the semiconductor or insulator does not show a metallic electronic state, the conductive surface 13 remaining at a portion other than the electrode portion is used as a nearby auxiliary electrode, and is used as an auxiliary electrode. During the application of an appropriate voltage, the relative energy between the surface level and the Fermi level was controlled by the so-called electric field effect, thereby controlling the electric conductivity of the conductive surface.
In addition, the electric conduction through this surface state can be reduced to such an extent that the electrical coupling between the electrode and the substrate can be completely ignored by controlling the voltage applied to the electrode using the conductive surface. Was. In addition, after forming a circuit as an electronic device instead of the auxiliary electrode, a dopant or a defect is introduced into the surface to control relative energy with respect to the Fermi level, or charge transfer, and to perform electric conduction. Be able to do it.

Actually, a quantum dot 2 having a diameter of 5 nm, a gate electrode 3 having a width of 5 nm, a source electrode 4 and a drain electrode 5 are formed on a silicon (111) substrate 1, and the distance between the quantum dot 2 and each electrode is 1 nm. Thus, the current flowing between the source electrode 4 and the drain electrode 5 could be controlled and switched by applying a voltage to the gate electrode 3. Similar results were obtained on the silicon (100), (110) surface, germanium surface and gallium arsenide surface of the semiconductor substrate, and particularly good results were obtained on the silicon (111) surface. The size of the quantum dot 2 is 1n
m to 100 nm, and the width of the gate electrode 3, the source electrode 4, and the drain electrode 5 can be 1 nm or more. The smallest single electron transistor of 10 nm × 10 nm can be formed, and the integration degree at this time is 1 cm ²
It is 10 ¹² pieces per. In this embodiment, the thickness of the substrate does not affect the function as a single-electron transistor.

Embodiment 2 In this embodiment, an embodiment of a resistance element using a surface level of a semiconductor surface will be described.

FIG. 2 shows a resistance element formed on the semiconductor surface in the same manner as in the first embodiment. The resistive element 7 was formed by stripping the conductive surface layer of the semiconductor substrate 1 by STM and leaving the electrode terminal 6 thinner at the center. By changing the characteristics of the length, width and surface state, a resistance element having a wide range of resistance values can be realized.

FIG. 3 shows a resistance element formed by forming an electrode terminal 6 on the surface of the semiconductor substrate 1 and providing a gap 8 having a length of about 1 nm at the center thereof. Gap 8
During the period, a current flows due to a tunnel phenomenon, so that the resistance value can be controlled by adjusting the size of the gap 8.
The resistance value can be controlled by changing the width of the electrode terminal 6 instead of adjusting the size of the gap 8.

Actually, an electrode terminal 6 having a width of 5 nm was formed on a silicon (111) substrate 1, a resistance element 7 having a length of 10 nm and a width of 1 nm was formed at the center thereof, and the resistance value was measured. However, the resistance value was 300 MΩ. Further, by providing a gap 8 having a width of 1 nm at the center of the electrode terminal 6 having a width of 5 nm, a resistance of 1 GΩ could be formed. A resistance value of about 10 MΩ to 1 GΩ in FIG. 2 and a resistance value of about 10 MΩ to 1 TΩ in FIG. 3 could be formed.

The semiconductor substrate has a silicon (100) surface,
A similar resistance element could be formed on the (110) surface, the germanium surface, and the gallium arsenide surface, but the resistance value can vary greatly depending on the difference in substrate material and surface structure, and the resistance value is 1 Ω to 1 GΩ in FIG. It was about.

Embodiment 3 In this embodiment, an embodiment of a capacitor using the surface level of the semiconductor surface will be described. FIG. 4 shows a capacitor formed on a semiconductor surface in the same manner as in the first embodiment. A counter electrode 9 is provided at an end of each electrode terminal 6 and faces each other to form a capacitor. The capacitance can be controlled by adjusting the width of the counter electrode 9 and the interval between the electrodes.
FIG. 5 shows an example of a capacitor in which the capacitance is increased by making the counter electrode 10 in a comb shape.

[0021] In fact, silicon (111) to form an electrode terminal 6 of the width 5nm on the substrate 1, by opposing one which formed the counter electrode 9 of width 20nm at its tip at intervals of 2 nm 4 × 10 ^{- A 20} F capacitor was formed. In addition, a pattern of the conductive surface is formed in such a manner that the opposing electrode 10 has a width of 5 nm, a length of 15 nm, and a tooth interval of 15 nm, and as a comb-shaped electrode having four teeth, a counterpart tooth of 10 nm is inserted between each tooth. As a result, a capacity of 12 × 10 ⁻²⁰ F was obtained. The semiconductor substrate is silicon (100),
Similar capacitors could be formed on the (110) surface, the germanium surface, and the gallium arsenide surface.

Embodiment 4 In this embodiment, a large number of quantum dots constituted by a conductive surface formed on a semiconductor surface are regularly arranged, and are excited by external light or by electron excitation by an electron injection electrode. An example of a light emitting element that emits light will be described. FIG. 6 shows that a large number of quantum dots 11 formed on a semiconductor surface in the same manner as in Example 1 are regularly arranged, and electron injection electrodes 12 having a width similar to that of the quantum dots 11 are arranged on both sides thereof. It is a light emitting element. Since the interval between the quantum dot 11 and the adjacent quantum dot 11 was formed by stripping the conductive layer on the surface of the semiconductor substrate 1 by STM and leaving the quantum dot 11, high-precision arrangement was possible. The quantum dot interval determined the light wavelength of the light emitting element, and the actual light emission wavelength almost coincided with this value. The position where the electron injection electrode 12 is arranged may be between the rows of the quantum dots 11 or between the rows in addition to both sides.

[0023]

According to the present invention, a very fine electronic device can be realized.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration example of a single-electron transistor using a surface state formed on a semiconductor surface.

FIG. 2 is a diagram showing a configuration example of a resistive element composed of a fine wire using a surface level formed on a semiconductor surface.

FIG. 3 is a diagram illustrating a configuration example of a resistance element formed by a tunnel junction using a surface state formed on a semiconductor surface.

FIG. 4 is a diagram showing a configuration example of a capacitor using surface states formed on a semiconductor surface.

FIG. 5 is a diagram showing a configuration example of a capacitor having a comb-shaped electrode using surface levels formed on a semiconductor surface.

FIG. 6 is a diagram illustrating a configuration example of a light-emitting element in which a large number of quantum dots using surface states formed on a semiconductor surface are arranged.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Quantum dot, 3 ... Gate electrode, 4
... source electrode, 5 ... drain electrode, 6 ... electrode terminal, 7 ...
Resistance element, 8 gap, 9, 10 counter electrode, 11 ...
Quantum dots, 12: Electron injection electrode, 13: Conductive surface left other than the electrode part.

Claims (9)

[Claims] 1. A conductive surface which is localized in one to several atomic layers from the surface of a semiconductor or an insulator and has a surface level capable of carrying out electric conduction, and an insulation in which the surface level is inactivated. An electronic device formed using a conductive surface and using electrical conduction through surface states. 2. The electronic device is formed on a semiconductor surface.
2. The method according to claim 1, wherein a voltage having a magnitude that can substantially neglect the electrical coupling between the electrode and the substrate with respect to electric conduction through a surface state is applied between the electrode and the substrate using the conductive surface. Electronic devices. 3. The electronic device according to claim 1, further comprising an auxiliary electrode formed on a surface of a semiconductor or insulator, an auxiliary electrode for effecting an electric field effect disposed close to the electronic device, or introducing a dopant or a defect into the surface. Or the electronic device according to 2. 4. The electronic device according to claim 3, wherein the electronic device has a conductive surface remaining except for peripheral portions of components of the device, and the conductive surface is used as an auxiliary electrode. 5. The electronic device according to claim 1, wherein a dangling bond on the surface of the semiconductor or the insulator is deactivated on a surface thereof, and an electric field, a current, light, an electromagnetic wave, heat or a contact by a scanning probe microscope probe and the like. A method for activating surface states such as surface atom stripping, oxygen, hydrogen, and other atoms that inactivate surface states due to a chemical reaction or the like at the induced surface or introduced molecules, or changes in the surface structure. By applying a process to activate the surface state of an arbitrary pattern formed by moving the scanning probe microscope tip using the above, an arbitrary pattern of the conductive surface having the surface state is formed, and it is used as a constituent unit The electronic device according to claim 1. 6. An electronic device comprising: a quantum dot formed by a conductive surface formed on a semiconductor surface; a gate electrode;
The electronic device according to claim 1, wherein the electronic device is a single-electron transistor including a source electrode and a drain electrode. 7. The electronic device according to claim 1, wherein the electronic device is a resistive element comprising an electrode terminal formed by a conductive surface formed on a semiconductor surface and a conductive surface formed by narrowing a central portion. The electronic device according to claim 1. 8. The electronic device has a set of electrode terminals constituted by a conductive surface formed on a semiconductor surface and a set of opposed electrodes connected to the electrode terminals. The electronic device according to any one of claims 1 to 5, wherein the capacitor is a capacitor whose capacity is increased by forming the counter electrode into a comb shape. 9. The electronic device according to claim 1, wherein a large number of quantum dots constituted by a conductive surface formed on a semiconductor surface are regularly arranged, and light is emitted by external light excitation or by electronic excitation by an electron injection electrode. The electronic device according to claim 1, wherein: