JPH10112510A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To facilitate forming a second electrode by forming a transistor having first and second electrodes through first and second gate oxide films on a substrate and providing a wiring layer on a thicker insulation layer than the second gate oxide film. SOLUTION: On a semiconductor substrate 1, an oxide film is formed to form source/drain regions 3 on memory cell-forming regions M and peripheral circuit-forming regions C. On the structure 1, a first gate oxide film 4 is formed and first gate electrodes 5a, 5b of a first transistor are formed thereon. A second gate oxide film 10 is formed on a channel-forming region of a second transistor and second gate electrode 11a is formed parallel between the first gate electrodes 5a and gate electrode 11b and wiring 11c are formed. The wiring layer 11c is the same layer as the second gate electrode layers 11a, 11b and a thicker insulation layer 7 than the second gate oxide film 10 is formed just beneath this layer 11c. This facilitates wiring the second gate electrodes 11a, 11b.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a high-density mask programmable ROM using double poly gate electrodes and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, as a memory cell system of a mask ROM, a NAND type ROM for writing ROM data by selecting an enhancement type transistor and a depletion type transistor with respect to cell transistors connected in series, There is a NOR-type ROM in which the threshold voltage is selectively set to be equal to or higher than the power supply voltage and the ROM data is written to the cell transistor connected to the ROM. In general, NAND type ROMs are excellent in high integration,
An R-type ROM is excellent in speeding up, but the opposite is inferior to each other.

A general NOR type ROM requires one contact hole for two memory cell transistors. Therefore, a margin for contact hole and mask alignment must be secured. It was very difficult to miniaturize. Therefore, high integration mainly involves NA
ND type ROMs have been used. In a NAND-type ROM, cell transistors need only be connected in series, and contact holes need only be provided at both ends of the transistor row. Therefore, the higher the number of transistors connected in series, the higher the integration.

However, in recent years, in order to achieve higher integration by using a NAND-type ROM, various measures have been taken to reduce a dimensional shift and a step in an element isolation region. For example,
As one of the methods, element isolation is performed without forming an element isolation film, and a high-density NOR type R which has both advantages of a NAND type ROM and a NOR type ROM.
OM memory cells have been proposed.

This memory cell is shown in FIGS. 22 (a) to 22 (d).
As shown in FIG. 2, a plurality of high-concentration diffusion layers 55 serving as source / drain regions and bit lines are formed in parallel in a memory cell region on a semiconductor substrate 51, and a gate oxide film 52 is formed on the semiconductor substrate 51. , A plurality of gate electrodes (word lines) 53 are arranged so as to be orthogonal to the high-concentration diffusion layers 55 that become bit lines. Also,
In the region 57 where the gate electrode 53 and the high concentration diffusion layer 55 are not formed, an impurity having a conductive layer different from the source / drain region is ion-implanted.
7 functions as element isolation between the cell transistor a and the cell transistor b.

In the memory cell having such a configuration, since the element isolation film such as the LOCOS film is not formed, the surface of the semiconductor substrate 51 is flat, and the gate electrode 53 is formed at a pitch smaller than a processing limit usually used. Can be arranged, and ions can be implanted into the element isolation region 57 in a self-aligned manner by using the gate electrode 53 as a mask, which has a great effect on high integration of memory cells.

For example, Japanese Patent Application Laid-Open No. Sho 53-41188 discloses a NAND-type ROM.
Japanese Patent Application Publication No. 1568 proposes a method for further increasing the density of memory cells by using a multi-layer structure of a high-density NOR type ROM. However, the demand for large capacity semiconductor memory devices is strict, and in order to achieve higher integration, a multi-layered semiconductor device having both a NAND ROM and a high-density NOR ROM has been developed. Various studies have been made on a semiconductor device performed by a PN junction without using the same.

[0008]

In order to achieve high integration of memory cells, the gate electrode has a multilayer structure of two or more layers.
The first problem in the method for increasing the density of memory cells is the difficulty in processing. For example, in the case where a plurality of first gate electrodes are formed in a memory cell and then a second gate electrode is formed between the first gate electrodes, a step formed by the first gate electrode causes a stepped portion of the second gate electrode to be formed. The film thickness is approximately twice the thickness of the flat portion. Further, since the first memory cell transistor and the second memory cell transistor are required to have almost the same performance, the second gate oxide film thickness of the base is the same level as that of the first gate oxide film (the thinner the finer process, the thinner). The gate processing is becoming strict even in the single-layer gate process.) In other words, the selectivity of the second gate electrode etching needs to be several times higher than the selectivity required for the first gate electrode etching in order to etch away the thick portion of the second gate electrode. If the second
If the underlying second gate oxide film is completely lost during the etching of the gate electrode, the silicon substrate is dug, resulting in a defect. Further, since the process using the two-layer gate electrode takes a long time, there is a problem that problems such as an increase in wafer manufacturing cost and a decrease in total wafer processing in a factory occur.

In addition, in the method of separating elements by PN junction without using a LOCOS film, it is important to simplify the process, and there is a problem that the parasitic capacitance of the gate electrode wiring used for wiring is large. .

[0010]

According to the present invention, device isolation is achieved by a PN junction formed in a semiconductor substrate.
A first transistor comprising a first gate electrode formed on a semiconductor substrate via a first gate oxide film, and a second transistor comprising a second gate electrode formed via a second gate oxide film.
There is provided a semiconductor device having a transistor, a wiring layer formed on an insulating layer thicker than the second gate oxide film, and having the same layer as the second gate electrode.

Further, according to the present invention, a first transistor comprising a first gate electrode formed on a semiconductor substrate via a first gate oxide film, and a second transistor formed via a second gate oxide film on the semiconductor substrate. A memory cell portion having a second transistor comprising a gate electrode;
And a peripheral circuit portion having a transistor.
OM, the first and second transistors in the peripheral circuit section have an LDD structure, and the second transistor has a low-concentration diffusion region having an arbitrary width, so that the first transistor has a higher breakdown voltage than the first transistor. A semiconductor device is provided, which is formed on an insulating layer thicker than the second gate oxide film and has a wiring layer formed of the same layer as the second gate electrode.

According to the present invention, (ia) ion implantation for forming source / drain regions in an arbitrary region on a semiconductor substrate is performed, and (ii-a) ion implantation is performed on the obtained semiconductor substrate.
Forming a first gate oxide film and a first gate electrode constituting the first transistor, and (iii-a) laminating an insulating layer over the entire surface of the semiconductor substrate including the first gate electrode, and forming at least a channel of the second transistor. Forming a mask having an opening on a region to be a part, etching back the insulating layer using the mask, and (iv-a) forming a second substrate on the semiconductor substrate including the insulating layer.
Forming a second gate oxide film and a second gate electrode constituting a transistor, and simultaneously forming a wiring layer of the same layer as the second gate electrode in an arbitrary region on the insulating layer; A manufacturing method is provided.

Further, (ib) ion implantation for forming a source / drain region in an arbitrary region of the memory cell formation region of the semiconductor substrate is performed, and (ii-b) ion implantation is performed on the obtained memory cell formation region of the semiconductor substrate. Forming a first gate oxide film forming a first transistor and a plurality of first gate electrodes parallel to each other, and forming a first gate oxide film on a peripheral circuit formation region;
(Iii-b) ions for forming a gate oxide film and a first gate electrode, and forming a low concentration source / drain region constituting the first transistor and the second transistor in an arbitrary region of the peripheral circuit formation region; Implantation is performed, and (iv-b) an insulating layer is stacked on the entire surface of the semiconductor substrate including the first gate electrode, and the insulating layer is formed on the memory cell formation region and at least on the region serving as the channel portion of the second transistor in the peripheral circuit formation region. A mask having an opening is formed, and the insulating layer is etched back using the mask to form a sidewall spacer on a side wall of the first gate electrode in the memory cell forming region and a second spacer in the peripheral circuit forming region. (Vb) removing an insulating layer over a region serving as a channel portion of the transistor between the first gate electrodes in the memory cell forming region of the semiconductor substrate including the sidewall spacer; And forming a second gate oxide film forming a second transistor in a peripheral circuit forming region of the semiconductor substrate including the insulating layer, and further forming a second gate electrode using a second gate electrode forming pattern, A wiring layer made of the same layer as the second gate electrode is formed in an arbitrary region on the insulating layer, and (vi-b) a wiring layer formed on the peripheral circuit formation region using the second gate electrode formation pattern. By etching back the insulating layer, sidewall spacers are formed on the side walls of the first gate electrode,
(vii-b) A method of manufacturing a semiconductor device, comprising performing ion implantation for forming high-concentration source / drain regions constituting first and second transistors in an arbitrary region of the peripheral circuit formation region. Is done.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to the present invention preferably uses a PN junction formed in a semiconductor substrate as element isolation, and has first and second transistors. This semiconductor device includes mask ROM, EPROM, E
It can be used for various semiconductor devices such as a peripheral circuit unit such as an EPROM and / or a memory cell unit. Optionally, by forming an impurity region (well) having a conductivity type different from that of the semiconductor substrate, a PMOS, an NMOS, or the like can be formed.
And CMOS devices. When the semiconductor device is used for a peripheral circuit section or the like, the first and second transistors may be formed in a multilayer structure, or may be formed independently of each other. Further, a PN is provided between the first and second transistors.
The first and second transistor forming regions may be separated from other circuit portions (for example, a memory cell portion or the like) by a PN junction. When one of the first and second transistors is set to have a high withstand voltage, the devices need not necessarily be separated by a PN junction, and may be separated by a known LOCOS film or the like. . On the other hand, when the semiconductor device is used in a memory cell portion, the first and second transistors are preferably formed in a multilayer structure. Specifically, the first transistor forming the first transistor
There is a structure in which a plurality of gate electrodes are provided, and a plurality of second gate electrodes constituting the second transistor are provided between the first transistors. Further, in this semiconductor device, a wiring layer is formed separately from the first and second transistors. This wiring layer may be formed on an element isolation region by a PN junction, or may be formed on an element formation region. This wiring layer is formed of the same layer as the second gate electrode layer forming the second transistor, and an insulating layer thicker than the second gate oxide film is formed immediately below this wiring layer.

It is preferable that the gate oxide film forming the first and second transistors is formed to have a thickness of, for example, about 50 to 300 °, and the gate electrode is formed to have a thickness of, for example, about 2000 to 3000 °. The thicknesses, materials, and the like of the gate oxide film and the gate electrode may be different between the first and second transistors, or different between the first or second transistors, or within the first or second transistors. You may. Note that in the case where the first and second transistors are used for a memory cell of a mask ROM, it is preferable to set the thickness and material of the gate electrode in consideration of writing of ROM data. That is, when data is simultaneously written into the first transistor and the second transistor by ion implantation, the first gate electrode and the second gate electrode are set to have the same ion implantation stopping ability. Preferably, the same film thickness and material may be selected, or the material and / or film thickness may be different. For example, if one is a polysilicon single layer and the other is a WSi / polysilicon layer, the ion implantation stopping power of WSi is about twice as large as that of polysilicon. / 1000 °. In the case where the semiconductor device of the present invention has a memory cell portion and a peripheral circuit portion, first and / or second transistors are formed respectively. The two transistors do not necessarily have to have the same structure in each part.

The wiring layer in the semiconductor device of the present invention is formed to have a thickness substantially equal to that of the second gate electrode. The insulating layer disposed immediately below the wiring layer is not particularly limited, but may be, for example, about 1000 to 4000 degrees. By forming such an insulating layer directly under the wiring layer,
It is possible to prevent the occurrence of parasitic capacitance of the wiring layer with respect to the semiconductor substrate. The insulating layer may be formed only immediately below the wiring layer. For example, when the first and second transistors are used in a multi-layer structure, an insulating layer is formed between the first gate electrode and the second gate electrode. May be arranged as a film or a sidewall spacer or the like for securing the thickness.

Note that the first and second transistors are:
Each has a source / drain region, and the source / drain region may have an LDD structure such as having a double diffusion layer in which a low concentration diffusion region is formed on the outer periphery of a high concentration diffusion region. In order to realize a high breakdown voltage, the width of the low-concentration diffusion region may be arbitrarily different depending on the characteristics to be obtained, or the low-concentration diffusion regions of both source / drain regions are symmetrically arranged. Alternatively, they may be arranged asymmetrically. Source / drain regions, when having regions with different LDD structure such as density, the density difference is not particularly limited, may be 10 to 10 ⁴ times.

In the method of manufacturing a semiconductor device according to the present invention, in the step (ia), ion implantation for forming a source / drain region in an arbitrary region on a semiconductor substrate is performed. The ion implantation at this time is not particularly limited, but can be performed at a dose of 1 × 10 ¹³ to 1 × 10 ¹⁶ ions / cm ² and an implantation energy of about 10 to 100 keV. In the case where the semiconductor device has a memory cell portion and a peripheral circuit portion, it is preferable to form the semiconductor device and the peripheral circuit portion at the same time.

In the step (ii-a), a first gate oxide film and a first gate electrode constituting a first transistor are formed on the semiconductor substrate obtained above. The materials and thicknesses of the gate oxide film and the gate electrode can be the same as those described above. In addition, an insulating film having a desired thickness may be formed over the gate electrode to arbitrarily ensure insulation with a conductive layer or the like formed in an upper layer in a later step.
In the case where the semiconductor device has a memory cell portion and a peripheral circuit portion, it is preferable to form the semiconductor device and the peripheral circuit portion simultaneously.

In the step (iii-a), an insulating layer is laminated on the entire surface of the semiconductor substrate obtained above. Next, a mask having an opening is formed at least over a region to be a channel portion of the second transistor, and the insulating layer is etched back using the mask. Accordingly, the semiconductor substrate is exposed only in the region where the second gate electrode is provided, and that region can be used as a channel portion of the second transistor. In the case where the semiconductor device has a memory cell portion and a peripheral circuit portion, a mask having an opening in the memory cell formation region is provided in addition to the region serving as the channel portion of the second transistor in the peripheral circuit formation region. Then, the insulating layer is etched back using the mask. In this case, a sidewall spacer can be formed on the side wall of the first gate electrode in the memory cell formation region.

In the step (iv-a), a second gate oxide film and a second gate electrode constituting a second transistor are formed on a semiconductor substrate including an insulating layer, and at the same time, an arbitrary region on the insulating layer is formed. Then, a wiring layer made of the same layer as the second gate electrode is formed. At this time, the gate oxide film and the gate electrode can be formed by the same method as in the step (ii-a). Note that when the semiconductor device has a memory cell portion and a peripheral circuit portion, it is preferable to form the semiconductor device and the peripheral circuit portion at the same time. In other words, in the memory cell formation region, by a normal photolithography and etching process,
A plurality of second gate electrodes can be formed in a self-aligned manner between the first gate electrodes, and in the peripheral circuit region,
Since the insulating layer of only the channel portion is removed in the step (iii-a), the second gate electrode can be formed in the portion where the insulating layer has been removed. Further, in addition to the above-described method, it can be formed in a self-aligned manner by a method such as buried etch back. When this buried etch-back method is used, the first gate electrode and the second gate electrode can be prevented from overlapping, and in a later step, there is no region where ion implantation is insufficient and uniform implantation is performed. Can be done.

Before, during or after the above series of steps, it is preferable to implant an impurity of the same conductivity type as that of the semiconductor substrate only in a desired region to form an element isolation region. .
Preferably, after step (ii-a), 10 ¹² to 10 ¹³ ion
Ions of the same conductivity type as that of the substrate of about s / cm ² are implanted at an implantation energy of about 15 to 100 keV, and if this state is left as it is, the threshold voltage of the second transistor becomes too high. For controlling the threshold value (impurities of the opposite type to the substrate).

In another method of manufacturing a semiconductor device according to the present invention, in step (ib), ion implantation for forming source / drain regions in an arbitrary region of a memory cell formation region of a semiconductor substrate is performed. The ion implantation at this time can be performed in the same manner as in the step (ia). A semiconductor device manufactured by this method has a memory cell portion and a peripheral circuit portion. In this step, source / drain regions of only the memory cell portion are formed.

In the step (ii-b), a first gate oxide film constituting a first transistor and a plurality of first parallel oxide films are formed on the memory cell formation region of the semiconductor substrate obtained above.
A gate electrode is formed, and a first gate oxide film and a first gate electrode are also formed on the peripheral circuit formation region.
At this time, the gate oxide film and the gate electrode can be formed in the same manner as in the step (ii-a).

In the step (iii-b), ion implantation for forming low-concentration source / drain regions constituting the first transistor and the second transistor is performed in an arbitrary region of the peripheral circuit formation region. At this time, a resist pattern having an opening only in a desired region of the peripheral circuit formation region is formed,
It is preferable to perform ion implantation using this resist pattern as a mask. The dose of the ion implantation is, for example, 1
Approximately 0 ¹² to 10 ¹⁴ ions / cm ² , implantation energy 1
About 0 to 100 keV is mentioned.

In the step (iv-b), an insulating layer is laminated on the entire surface of the semiconductor substrate including the first gate electrode, and the insulating layer is formed on the memory cell forming region and at least on the region serving as the channel portion of the second transistor in the peripheral circuit forming region. Then, a mask having an opening is formed, and the insulating layer is etched back using the mask. The method of stacking the insulating film, forming the mask, and etching back can be performed in the same manner as in the step (iii-a). As a result, a sidewall spacer is formed on the side wall of the first gate electrode in the memory cell formation region, and the insulating layer on the region serving as the channel portion of the second transistor in the peripheral circuit formation region is removed to expose the semiconductor substrate. be able to.

In the step (vb), a second gate oxide film forming a second transistor is formed on the semiconductor substrate including the sidewall spacer, and the second gate oxide film is formed on the second gate oxide film.
A second gate electrode material is laminated. Further, a pattern for forming a second gate electrode is formed on the gate electrode material,
Using this pattern, a second gate electrode is formed between the first gate electrodes in the memory cell formation region and in the peripheral circuit formation region of the semiconductor substrate including the insulating layer, and at the same time, the second gate electrode is formed in an arbitrary region on the insulating layer. A wiring layer made of the same layer as the electrodes is formed. Thus, the second gate electrode can be formed in a self-aligned manner between the first gate electrodes in the memory cell formation region.

In the step (vi-b), the insulating layer formed on the peripheral circuit forming region is subsequently etched back by using the second gate electrode forming pattern. Thus, a sidewall spacer can be formed on the side wall of the first gate electrode, and an unnecessary insulating layer on the peripheral circuit formation region can be removed. Further, in the step (vii-b), ion implantation for forming high-concentration source / drain regions constituting the first transistor and the second transistor is performed in an arbitrary region of the peripheral circuit formation region. The ion implantation at this time can be formed by the same method as in the step (iii-b), and the ion implantation dose is, for example, 10 ¹⁴
About 10 ¹⁶ ions / cm ² , implantation energy 10
About 100 keV. Thus, the low-concentration diffusion region formed in the previous step has a low-concentration diffusion region arranged at the outer peripheral portion, or the low-concentration diffusion region has a double-concentration diffusion region of the low-concentration diffusion region disposed only at its end. An LDD structure can be formed.

When the semiconductor device manufactured by this method is element-isolated by a PN junction, the same steps as those of the above-described semiconductor device manufacturing method can be applied. When element isolation is performed, a LOCOS film can be formed by a known method before the step (ib) or after an appropriate step. Since a semiconductor device manufactured by the above method can have a high breakdown voltage, the same can be achieved by combining with a semiconductor device formed by the manufacturing method described above or by arbitrarily changing the arrangement of the low concentration diffusion region. Since various elements can be formed in the process, the degree of freedom in combining the circuits is increased, and the EEP required for a high withstand voltage circuit is required.
It can also be suitably used for ROM. Hereinafter, a semiconductor device and a method of manufacturing the same according to the present invention will be described with reference to the drawings.

Embodiment 1 First, as shown in FIG. 1, an oxide film 2 is formed on a semiconductor substrate 1.
And a resist pattern having a desired shape (not shown)
Using the resist pattern as a mask, impurity ions of the opposite conductivity type to the semiconductor substrate 1, for example, arsenic ions, are implanted at an implantation dose of 40 keV and 10 ¹⁵ cm ⁻² .
Thus, source / drain regions 3 are formed in the memory cell formation region M and the peripheral circuit formation region C.

Next, as shown in FIG.
A first gate oxide film 4 having a thickness of about 50 to 300 ° is formed thereon. In the memory cell formation region M, a plurality of first gate electrodes 5a are arranged in parallel on the gate oxide film 4, and in the peripheral circuit formation region C, the first gate electrodes 5a are formed on the gate oxide film 4 in the region where the first transistor is formed. One gate electrode 5b is formed. As the gate electrodes 5a and 5b, for example, 2000 to 3
A two-layered structure including an N ⁺ polysilicon film having a thickness of 2,000 mm or a lower N ⁺ polysilicon film having a thickness of 1,000 mm and an upper tungsten silicide film having a thickness of 1,000 mm is used. An insulating film 6 is formed on the first gate electrodes 5a and 5b as an etching mask for the first gate electrodes 5a and 5b in the subsequent steps. This film also functions as an interlayer insulating film between the film and a second gate electrode described later.

Next, as shown in FIG. 3, for device separation, the same conductivity type impurity to the semiconductor substrate, for example, boron ions are implanted at ^{20keV, 1 × 10 13 ions /} cm 2 conditions, the substrate surface To increase the impurity concentration. Next, FIG.
As shown in (1), an insulating film 7 is formed on the semiconductor substrate 1 including the first gate electrodes 5a and 5b. A resist is applied thereon to form a resist pattern 8 having openings in the memory cell formation region M and the peripheral circuit formation region C, which are regions to be the channel portions of the second transistors. Using this resist pattern 8 as a mask, side wall etching is performed to form a side wall spacer 9a on the side wall of the first gate electrode 5a in the memory cell forming region M, and to form a channel portion of the second transistor in the peripheral circuit forming region C with the channel portion. The insulating film 7 only on the region to be removed is removed. Note that the sidewall spacer 9a is used as an interlayer insulating film between the sidewall spacer 9a and a second gate electrode described later. After that, ion implantation is performed to control the threshold voltage of the second transistor.

After removing the resist pattern 8, as shown in FIG. 5, a second gate oxide film 10 is formed in a region to be a channel portion of the second transistor, and an insulating film 6, a sidewall spacer 9a and a second gate oxide film 10 are formed. A conductive layer for a second gate electrode is formed via the gate oxide film 10, and etching is performed using the resist pattern 12 having a desired shape formed on the conductive layer for the second gate electrode as a mask. The second gate electrode 11a is formed in parallel between the first gate electrodes 5a, and the gate electrode 11b of the second transistor and the wiring 11c are formed in the peripheral circuit formation region C. As a result, not only the thin first gate oxide film 4 but also the thick insulating film 7 for forming the sidewall spacer remains under the wiring 11c, so that the wiring capacity for the semiconductor substrate 1 can be significantly reduced.

When the semiconductor device is used as a mask ROM, ROM data is written in a later step.
Since it is desired to simultaneously perform the first transistor including the gate electrode 5a and the second transistor including the second gate electrode 11a, the ion implantation stopping power of the first gate electrode 5a and the second transistor
It is desirable to select and set the material and thickness of the film so that the ion implantation stopping power of the gate electrode 11a is the same. For example, the second gate electrodes 11a to 11c can be formed using the same material as the first gate electrodes 5a and 5b described above.

After the second gate electrode 11 is formed, as shown in FIG. 6, the insulating film 7 is subsequently removed by etching using the resist pattern 12 as a mask. 1 gate electrode 5
The side wall spacer 9b is formed on the side wall of the gate electrode b, and the insulating film 7 can be left only under the wiring 11c and only on the side wall of the second gate electrode 11b. In the memory cell formation region M, the insulating film 6 formed on the first gate electrode 5a is removed.

FIG. 8 is a plan view of FIG. 7 and FIG.
As shown in (1), the first half process of the semiconductor device can be performed by performing ordinary processes such as formation of an interlayer insulating film 13, formation of a contact hole 14, formation of a metal wiring 15, and formation of a protective film (not shown). The semiconductor device is completed by completing the assembly process in the latter half of the process. Note that, optionally, Vth control implantation of a transistor, element isolation ion implantation, a ROM data writing step, or the like may be appropriately performed during the above-described steps.

Embodiment 2 In a series of manufacturing steps of Embodiment 1, after forming the second gate electrodes 11a and 11b and the wiring 11c as shown in FIG. 5, the resist pattern 12 is formed as shown in FIG. By removing, the insulating film 7 may be left as it is. As a result, the height of the memory cell formation region is substantially equal to that of the peripheral circuit formation region, and the flatness is improved. Therefore, as shown in FIG. 10, the metal wiring is easily processed.

Embodiment 3 The transistor structure of the peripheral circuit section of the embodiment 1
A semiconductor device having a structure for obtaining D and a high withstand voltage and a method for manufacturing the same will be described. First, as shown in FIG. 11, an oxide film 2 is formed on a semiconductor substrate 1, a resist pattern (not shown) having a desired shape is formed, and a memory cell on the semiconductor substrate 1 is formed using this resist pattern as a mask. Only in the formation region M, the source / drain regions 3 are formed by ion implantation under the same conditions as in the first embodiment.

Next, as shown in FIG. 12, a first gate oxide film 4 is formed on the semiconductor substrate 1. In the memory cell formation region M, a plurality of first gate electrodes 5a are arranged in parallel on the gate oxide film 4, and in the peripheral circuit formation region C, the first gate electrodes 5a are formed on the gate oxide film 4 in the region where the first transistor is formed. One gate electrode 5b is formed. Further, an insulating film 6 is formed on the first gate electrodes 5a and 5b. Subsequently, a resist pattern 16 having an opening only in a region 17 that becomes the low-concentration source / drain region of the first transistor and the second transistor in the peripheral circuit formation region C is formed. Ion (P
⁺ ) Is ion-implanted at an implantation dose of the order of 10 ¹³ cm ⁻² at an implantation energy of 30 keV.

Next, as shown in FIG. 13, the resist pattern 16 is removed, and impurities of the same conductivity type as that of the semiconductor substrate, for example, boron ions are added at 20 keV for element isolation.
Implantation is performed under conditions of 1 × 10 ¹³ ions / cm ² to increase the impurity concentration on the substrate surface. Subsequently, an insulating film 7 is formed on the semiconductor substrate 1 as shown in FIG. A resist is applied thereon, and a resist pattern 8 similar to that of the first embodiment is used.
Using the resist pattern 8 as a mask, a sidewall spacer 9a is formed on the side wall of the first gate electrode 5a in the memory cell formation region M, and a region serving as a channel portion of the second transistor in the peripheral circuit formation region C is formed. The upper insulating film 7 is removed. After that, ion implantation is performed to control the threshold voltage of the second transistor.

After removing the resist pattern 8, FIG.
As shown in FIG. 5, a second gate oxide film 10 is formed in a region to be a channel portion of the second transistor, and a second gate electrode conductive film is formed via the insulating film 6, the sidewall spacer 9a and the second gate oxide film 10. A layer is formed, and is etched using the resist pattern 12 having a desired shape formed on the second gate electrode conductive layer as a mask. 2
The gate electrode 11b of the second transistor is formed in the peripheral circuit formation region C while forming the gate electrode 11a.
And the wiring 11c. At this time, the gate electrode 11b of the second transistor is formed in such a shape that one end is longer than the other end and covers the insulating film 7.

Next, as shown in FIG. 16, the insulating film 7 is removed by etching using the resist pattern 12 as a mask in the same manner as in the first embodiment. The side wall spacer 9b is formed on the side wall of the gate electrode 5b, and the insulating film 7 can be left only under the wiring 11c and only on the side wall of the second gate electrode 11b. In the memory cell formation region M, the insulating film 6 formed on the first gate electrode 5a is removed.

Subsequently, as shown in FIG. 17, a resist pattern 19 having an opening only in the region 20 which becomes the high-concentration source / drain region of the first and second transistors in the peripheral circuit forming region C is formed. , Arsenic ion (As
⁺ ) Is ion-implanted at an implantation dose of the order of 10 ¹⁵ cm ^{−2 and} an implantation energy of 40 keV. As shown in FIG. 18, a double diffusion layer 21 including the low-concentration source / drain region 18 and the high-concentration source / drain region 20 is formed in the first and second transistors by the above-described two ion implantations. . Further, since the length of the low concentration source / drain region 18 of the second transistor can be set to an arbitrary value, various transistors having a high breakdown voltage structure can be formed simultaneously.

Subsequently, as shown in FIG. 19, normal steps such as formation of an interlayer insulating film 13, formation of a contact hole 14, formation of a metal wiring 15, and formation of a protective film (not shown) are performed. As a result, the first half process of the semiconductor device is completed,
Further, the latter half of the assembly process is performed, and the semiconductor device is completed. Note that, optionally, Vth control implantation of a transistor, element isolation ion implantation, a ROM data writing step, or the like may be appropriately performed during the above-described steps.

Embodiment 4 Next, an embodiment in which the semiconductor device of Embodiment 2 is applied to a mask ROM will be described below. 20 and FIG.
As shown in FIG. 21 which is a cross-sectional view taken along the line A ′, in the memory cell region, the first gate electrodes 5 and the second gate electrodes 11 serving as the word lines and the selection lines of the memory cells are alternately arranged without gaps. I have. The contact hole 14 to the bit line wiring 15 outside the memory cell region is hollowed out inside the selection line (second gate electrode 11), but the boundary leaves the thick insulating film 7 for sidewall formation. Therefore, the thin gate oxide film 4 is not directly etched. At the time of writing the ROM data, OFF injection of the parasitic channel is performed at the same time, and the injection region is indicated by 22 (the ROM data writing pattern is omitted).

[0046]

According to the semiconductor device of the present invention, even in a semiconductor device having a two-layer structure having first and second gate electrodes, the processing of the second gate electrode can be easily performed, and the yield is improved. be able to. In addition, even when a wiring layer is formed using a gate electrode, generation of parasitic capacitance of the wiring layer with respect to the semiconductor substrate can be prevented, and characteristics such as high speed of the semiconductor device can be improved.

Further, according to the method of manufacturing a semiconductor device of the present invention, a semiconductor device having the above configuration can be easily manufactured, and an LDD transistor structure and a high breakdown voltage transistor structure are simultaneously manufactured in a peripheral circuit portion. Thus, the versatility of the semiconductor device can be improved, and the semiconductor device can be easily applied to a CMOS structure which is a mainstream of the semiconductor device.

Therefore, it is possible to obtain a semiconductor device and a method of manufacturing a semiconductor device which achieve both high integration and low cost.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional process drawing of a main part showing one embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 2 is a schematic cross-sectional process drawing of a main part showing one embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 3 is a schematic cross-sectional process drawing of a main part showing one embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 4 is a schematic cross-sectional process drawing of a main part showing one embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 5 is a schematic cross-sectional process drawing of a main part showing one embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 6 is a schematic cross-sectional process drawing of a main part showing one embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 7 is a schematic cross-sectional process drawing of a main part showing one embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 8 is a schematic plan view of the semiconductor device of the present invention including the schematic cross section shown in FIG. 7;

FIG. 9 is a schematic cross-sectional process drawing of a main part showing another embodiment of the method for manufacturing a semiconductor device of the present invention.

FIG. 10 is a schematic cross-sectional process diagram of a main part showing another embodiment of the method for manufacturing a semiconductor device of the present invention.

FIG. 11 is a schematic cross-sectional process drawing of a main part showing still another embodiment of the method for manufacturing a semiconductor device of the present invention.

FIG. 12 is a schematic cross-sectional process drawing of a main part showing still another embodiment of the method for manufacturing a semiconductor device of the present invention.

FIG. 13 is a schematic cross-sectional process drawing of a main part showing still another embodiment of the method for manufacturing a semiconductor device of the present invention.

FIG. 14 is a schematic cross-sectional process drawing of a main part showing still another embodiment of the method for manufacturing a semiconductor device of the present invention.

FIG. 15 is a schematic cross-sectional process drawing of a main part showing still another embodiment of the method for manufacturing a semiconductor device of the present invention.

FIG. 16 is a schematic cross-sectional process drawing of a main part showing still another embodiment of the method for manufacturing a semiconductor device of the present invention.

FIG. 17 is a schematic cross-sectional process drawing of a main part showing still another embodiment of the method for manufacturing a semiconductor device of the present invention.

FIG. 18 is a schematic cross-sectional process drawing of a main part showing still another embodiment of the method for manufacturing a semiconductor device of the present invention.

FIG. 19 is a schematic cross-sectional process drawing of a main part showing still another embodiment of the method for manufacturing a semiconductor device of the present invention.

FIG. 20 is a schematic plan view of a main part when the semiconductor device of the present invention is used for a mask ROM.

FIG. 21 is a sectional view taken along line AA ′ of FIG. 20;

FIG. 22 is a schematic plan view and a cross-sectional view illustrating a conventional semiconductor device.

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate 2 oxide film 3 source / drain region 4 first gate oxide film 5a, 5b first gate electrode 6 first gate electrode insulating film 7 insulating layer 8, 12, 16, 19 resist pattern 9a, 9b sidewall spacer DESCRIPTION OF SYMBOLS 10 2nd gate oxide film 11a, 11b 2nd gate electrode 11c Wiring layer 13 Interlayer insulating film 14 Contact hole 15 Metal wiring 17 Low concentration source / drain region 18 Low concentration source / drain region 20 High concentration source / drain region 21 Double diffusion layer 22a, 22b Parasitic channel OFF implantation region 23 Element isolation implantation ion

Claims (8)

[Claims] An element is separated by a PN junction formed in a semiconductor substrate, and a first transistor including a first gate electrode formed on the semiconductor substrate via a first gate oxide film; and a second gate oxide. A second transistor comprising a second gate electrode formed through a film, the second transistor being formed on an insulating layer thicker than the second gate oxide film,
And a wiring layer comprising the same layer as the second gate electrode. 2. The semiconductor device according to claim 1, wherein the mask ROM comprises a memory cell section having a first transistor and a second transistor, and a peripheral circuit section having at least a second transistor. 3. A memory device comprising: a first transistor including a plurality of first gate electrodes formed in parallel with each other;
A second transistor including at least one second gate electrode formed between the first gate electrodes via a sidewall spacer formed on a side wall of the first gate electrode; 3. The semiconductor device according to claim 2, further comprising a wiring layer formed on the same layer as the side wall spacer and formed on the same layer as the second gate electrode. 4. A first transistor comprising a first gate electrode formed on a semiconductor substrate via a first gate oxide film, and a second transistor comprising a second gate electrode formed via a second gate oxide film. A mask ROM including a memory cell portion having a transistor and a peripheral circuit portion having the first transistor and the second transistor, wherein the first and second transistors in the peripheral circuit portion are L
Since the second transistor has a DD structure and has a low-concentration diffusion region having an arbitrary width, the second transistor is set to have a higher breakdown voltage than the first transistor, and is formed on an insulating layer thicker than the second gate oxide film. And a wiring layer formed of the same layer as the second gate electrode. 5. A memory device comprising: a first transistor including a plurality of first gate electrodes formed in parallel with each other;
A second transistor including at least one second gate electrode formed between the first gate electrodes via a sidewall spacer formed on a side wall of the first gate electrode; 5. The semiconductor device according to claim 4, further comprising a wiring layer formed on the same layer as the side wall spacer and formed on the same layer as the second gate electrode. 6. An ion implantation for forming a source / drain region in an arbitrary region on a semiconductor substrate,
(ii-a) forming a first gate oxide film and a first gate electrode constituting a first transistor on the obtained semiconductor substrate;
(iii-a) stacking an insulating layer over the entire surface of the semiconductor substrate including the first gate electrode, forming a mask having an opening at least over a region to be a channel portion of the second transistor, and Etching back the layer, (iv-a) forming a second gate oxide film and a second gate electrode constituting a second transistor on the semiconductor substrate including the insulating layer, A method for manufacturing a semiconductor device, comprising: forming a wiring layer made of the same layer as the second gate electrode in a region. 7. A semiconductor device comprising a memory cell formation region having first and second transistors and a peripheral circuit formation region,
In ii-a), the insulating layer is etched back using a mask having openings on the memory cell formation region and a region serving as a channel portion of the second transistor in the peripheral circuit formation region, thereby forming a memory cell formation region. Forming a sidewall spacer on the side wall of the first gate electrode in the region,
7. The method of manufacturing a semiconductor device according to claim 6, wherein the insulating layer on a region of the peripheral circuit forming region which is to be a channel portion of the second transistor is removed. 8. (ib) ion implantation for forming source / drain regions in an arbitrary region of the memory cell formation region of the semiconductor substrate; and (ii-b) on the memory cell formation region of the obtained semiconductor substrate. Forming a first gate oxide film forming a first transistor and a plurality of first gate electrodes parallel to each other, and forming a first gate oxide film and a first gate electrode also on a peripheral circuit forming region; And (iii-b) a first transistor and a second transistor in an arbitrary region of the peripheral circuit formation region.
Ion implantation is performed to form low-concentration source / drain regions constituting the transistor, and (iv-b) an insulating layer is stacked on the entire surface of the semiconductor substrate including the first gate electrode, and is formed on the memory cell formation region and in the periphery. At least the second of the circuit formation region
A mask having an opening is formed over a region to be a channel portion of a transistor, and the insulating layer is etched back using the mask, so that a sidewall spacer is formed on a side wall of a first gate electrode in a memory cell formation region. And (vb) removing a portion of the insulating layer over a region serving as a channel portion of the second transistor in the peripheral circuit forming region between the first gate electrodes of the memory cell forming region of the semiconductor substrate including the sidewall spacer and the insulating layer. In the peripheral circuit formation region of the semiconductor substrate including
A gate oxide film is formed, and a second gate electrode is formed using a pattern for forming a second gate electrode. At the same time, a wiring layer made of the same layer as the second gate electrode is formed in an arbitrary region on the insulating layer. (Vi-b) using the second gate electrode formation pattern to etch back an insulating layer formed on the peripheral circuit formation region, thereby forming a sidewall spacer on the first gate electrode side wall; (vii-b)
A method of manufacturing a semiconductor device, comprising performing ion implantation for forming high-concentration source / drain regions constituting first and second transistors in an arbitrary region of the peripheral circuit formation region.