JPH10112442A - Semiconductor wafer and its manufacture and manufacture of semiconductor integrated circuit device using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an SIMOX(separation by implanted oxygen) wafer having few silicon oxide deposit on a surface silicon layer, a manufacturing method, and a manufacturing method for a semiconductor integrated circuit device using the same. SOLUTION: In a manufacturing method for a semiconductor wafer, a silicon epitaxial layer 2 is firstly formed on a silicon substrate as a substrate for a base by using an epitaxial growing method. After that ion implantation of oxygen ions being infused from the surface of the silicon epitaxial layer 2 into the inner part of the silicon epitaxial layer 2 is performed. After that an anneal processing is made to form an oxide silicon layer 3 for implantation in the inner part of the silicon epitaxial layer 2 and also to distribute a surface silicon layer 4 as an element forming region on the oxide silicon layer 3 for implantation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor wafer, a method of manufacturing the same, and a semiconductor integrated circuit device using the semiconductor wafer. More particularly, the present invention relates to a SIMOX wafer having a reduced silicon oxide precipitate on a surface silicon layer and a method of manufacturing the same. And a method of manufacturing a semiconductor integrated circuit device using the same.

[0002]

2. Description of the Related Art The present inventors have proposed a SIMOX (Separation b).
y IMplanted OXygen), a semiconductor wafer (hereinafter referred to as a SIMOX wafer) and a semiconductor integrated circuit device manufacturing technique using the same were studied. The following is
This is a technique studied by the inventor, and its outline is as follows.

[0003] That is, a SIMOX wafer is an SOI
(Silicon on Insulator) This is a kind of wafer, and a surface silicon layer as an uppermost layer is formed on a silicon (Si) substrate through a buried silicon oxide (SiO ₂ ) layer having a thickness of several hundred nm to a thickness of 0.1 to 0.1. It is provided with a thickness of 0.3 μm. Then, a semiconductor integrated circuit device using the same has a MOSFET on a surface silicon layer composed of a single crystal silicon layer.
(Metal Oxide Semiconductor Field Effect Transisto
r) and other semiconductor elements are formed.

[0004] In a method of manufacturing a SIMOX wafer, a silicon substrate made of single crystal silicon formed by using a CZ (Czochralski) method as a single crystal manufacturing method is used, and the silicon substrate has 10 ¹⁸ / cm ^2. After implanting oxygen ions (O ⁺ ) before and after with an acceleration energy of 100 to 200 KeV, annealing is performed at a high temperature of 1200 ° C. or more to form a buried silicon oxide layer and to recover ion implantation damage in the surface silicon layer. Manufactured.

[0005] Incidentally, as a document describing a manufacturing technique of a semiconductor integrated circuit device using an SOI wafer, for example, on December 15, 1990, W. Mari published by Keigaku Shuppan Co., Ltd. "P321 to p3
25.

[0006]

However, the aforementioned S
Since the IMOX wafer uses a silicon substrate made of single crystal silicon formed using the CZ method, oxygen atoms in the single crystal silicon are 7 to 10 × 1.
It was found that about 0 ¹⁷ / cm ^{3 was} present, and that high-density silicon oxide precipitation nuclei introduced during crystal growth were included.

As a result, in a silicon substrate made of single-crystal silicon formed by using the CZ method, oxygen atoms originally present therein are converted into silicon oxide precipitate nuclei by high-temperature annealing after oxygen ion implantation. There is a problem that the silicon oxide precipitates to form silicon oxide precipitates in the surface silicon layer. The silicon oxide material in the surface silicon layer is, for example, a dynamic random access memory (DRAM).
Causes various problems such as a reduction in the refresh time of the semiconductor integrated circuit device, a deterioration in the reliability of the gate silicon oxide film, and an increase in the leak current of the pn junction such as a source / drain. There is a problem that the yield is reduced.

An object of the present invention is to provide a SIMOX wafer having a small amount of silicon oxide precipitates on a surface silicon layer, a method of manufacturing the same, and a semiconductor integrated circuit device using the SIMOX wafer.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, (1). The SIMOX wafer of the present invention has a silicon substrate as a base substrate, a buried silicon oxide layer, and a surface silicon layer as a device forming region composed of a silicon epitaxial layer on the buried silicon oxide layer. And a surface silicon layer composed of a silicon epitaxial layer having less silicon oxide precipitates than a silicon substrate.

(2). According to the method for manufacturing a SIMOX wafer of the present invention, after forming a silicon epitaxial layer on a silicon substrate as a base substrate by using an epitaxial growth method, oxygen ions are introduced into the silicon epitaxial layer from the surface of the silicon epitaxial layer. After the ion implantation, an annealing process is performed to form a buried silicon oxide layer inside the silicon epitaxial layer and to arrange a surface silicon layer on the buried silicon oxide layer.

(3). The method of manufacturing a semiconductor integrated circuit device using a SIMOX wafer of the present invention
A plurality of semiconductor devices such as MOSFETs are formed on a surface silicon layer composed of a silicon epitaxial layer having less silicon oxide precipitates than a silicon substrate in an X wafer.

[0014]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and redundant description will be omitted.

(Embodiment 1) FIGS. 1 to 3 are sectional views showing a manufacturing process of a SIMOX wafer according to an embodiment of the present invention. With reference to FIG.
The X wafer and its manufacturing method will be specifically described.

First, a silicon substrate 1 is prepared as a base substrate for a SIMOX wafer (FIG. 1). Silicon substrate 1 in SIMOX wafer of the present embodiment
Is a single crystal silicon wafer having a (100) crystal plane orientation, n-type conductivity, 10 Ωcm resistivity, 7 × 10 ¹⁷ / cm ³ oxygen concentration, 150 mm diameter, and 650 μm thickness. It is. In this case, the oxygen concentration in the silicon substrate 1 is desirably as low as possible in order to suppress outward diffusion of oxygen atoms from the silicon substrate 1 to the silicon epitaxial layer due to high-temperature heating during epitaxial growth, which will be described later.

Next, a silicon epitaxial layer 2 is formed on the silicon substrate 1 by using an epitaxial growth method (FIG. 2). The condition of the epitaxial growth method in this case is that dichlorosilane (SiH ₂ Cl ₂ ) gas is used as a raw material,
Using hydrogen (H) gas as carrier gas and heating temperature of 10
At a temperature of 50 ° C., a silicon epitaxial layer 2 having a thickness of 2 μm is formed on a silicon substrate 1 by using an epitaxial growth method under the above conditions. When forming the silicon epitaxial layer 2, the conductivity type is set to n-type,
To make the resistivity 10 Ωcm, phosphine (PH ₃ ) gas is doped in the carrier gas.

Thereafter, a buried silicon oxide layer 3 is formed inside the silicon epitaxial layer 2, and the region of the silicon epitaxial layer 2 on the surface is used as a surface silicon layer 4 as a device forming region (FIG. 3). In this case, with the silicon substrate 1 on which the silicon epitaxial layer 2 is formed kept at a temperature of 550 ° C., oxygen ions are implanted into the surface of the silicon epitaxial layer 2 under the conditions of ion implantation and the acceleration energy is 180 KeV and the dose is Ion implantation is performed at 2 × 10 ¹⁸ / cm ² . Thereafter, in a nitrogen (N) atmosphere, annealing is performed at a temperature of 1350 ° C. for 4 hours to form a buried silicon oxide layer 3. 5 is formed. In this SIMOX wafer 5, the surface silicon layer 4 has a thickness of about 200 nm, and the buried silicon oxide layer 3 has a thickness of about 500 nm, all of which are formed inside the silicon epitaxial layer 2.

According to the method of manufacturing the SIMOX wafer 5 of the present embodiment described above, after the silicon epitaxial layer 2 is formed on the silicon substrate 1, the buried silicon oxide layer 3 is formed inside the silicon epitaxial layer 2. By arranging the surface silicon layer 4 on the surface,
Surface silicon layer 4 composed of silicon epitaxial layer 2
Is formed. Therefore, the silicon epitaxial layer 2 serving as the surface silicon layer 4 is
Since the oxygen concentration is lower and silicon oxide precipitation nuclei do not exist, silicon oxide precipitates are less likely to be formed even when annealing is performed at a high temperature, such as when forming the buried silicon oxide layer 3. As a result, S
Since the surface silicon layer 4 in the IMOX wafer 5 is a silicon epitaxial layer 2 and has a small amount of silicon oxide precipitates, when the surface silicon layer 4 is used as an active region of the semiconductor integrated circuit device, the semiconductor integrated circuit device It is possible to prevent a defect and a decrease in electrical characteristics due to a silicon oxide precipitate from occurring, and to improve a manufacturing yield of the semiconductor integrated circuit device.

(Embodiment 2) FIGS. 4 to 6 are cross-sectional views showing steps of manufacturing a SIMOX wafer according to another embodiment of the present invention. With reference to FIG.
An OX wafer and a method for manufacturing the OX wafer will be specifically described.

First, a silicon substrate 1 is prepared as a base substrate in a SIMOX wafer (FIG. 4). Silicon substrate 1 in SIMOX wafer of the present embodiment
Uses the same material as the silicon substrate 1 of the first embodiment.

Next, the silicon substrate 1 is annealed in a nitrogen atmosphere at a temperature of 1100 ° C. for 2 hours to diffuse oxygen atoms contained in the silicon substrate 1 outward. The oxygen concentration in a region within a few tens of micrometers from the surface is reduced to 7 × 10 ¹⁷ / cm ³ or less. By this step, out-diffusion of oxygen atoms from the silicon substrate 1 to the silicon epitaxial layer can be suppressed in high-temperature heating during epitaxial growth described later.

Next, a silicon epitaxial layer 2 as a surface silicon layer 4 is formed on the silicon substrate 1 by using an epitaxial growth method (FIG. 5). The condition of the epitaxial growth method in this case is a condition under which a silicon epitaxial layer 2 in a thin film state as the surface silicon layer 4 can be formed, using a monosilane (SiH ₄ ) gas as a raw material, a hydrogen gas as a carrier gas, and a heating temperature of 1000. The silicon epitaxial layer 2 having a thickness of about 200 nm is formed on the silicon substrate 1 by using the epitaxial growth method under the above conditions. In forming the silicon epitaxial layer 2 as the surface silicon layer 4, the carrier gas is doped with a phosphine gas so that the conductivity type is n-type and the resistivity is 10 Ωcm.

Thereafter, a buried silicon oxide layer 3 is formed in the silicon substrate 1 under the interface between the silicon epitaxial layer 2 as the surface silicon layer 4 and the silicon substrate 1.
A SIMOX wafer 6 is formed (FIG. 6). In this case, with the silicon substrate 1 on which the silicon epitaxial layer 2 is formed kept at a temperature of 550 ° C., oxygen ions are implanted into the surface of the silicon epitaxial layer 2 under the conditions of ion implantation and the acceleration energy is 180 KeV and the dose is Ion implantation is performed at 2 × 10 ¹⁸ / cm ² . Thereafter, in a nitrogen atmosphere, an annealing process is performed at a temperature of 1350 ° C. for 4 hours to form the buried silicon oxide layer 3.
Is formed to form the SIMOX wafer 6. In this SIMOX wafer 6, the thickness of the surface silicon layer 4 is about 200 nm, which is the same as the thickness of the silicon epitaxial layer 2, and the thickness of the buried silicon oxide layer 3 is about 500nm. Part is formed.

According to the method of manufacturing the SIMOX wafer 6 of the present embodiment described above, after the silicon epitaxial layer 2 is formed on the silicon substrate 1, the silicon oxide layer is embedded in the region of the silicon substrate 1 below the silicon epitaxial layer 2. By forming the silicon oxide layer 3, the surface silicon layer 4 is disposed on the surface thereof, and the surface silicon layer 4 composed of the silicon epitaxial layer 2 is formed. Therefore,
A SIMOX wafer 6 having the same effect as the SIMOX wafer 5 of the first embodiment can be obtained.

(Embodiment 3) FIGS. 7 to 9 are cross-sectional views showing steps of manufacturing a SIMOX wafer according to another embodiment of the present invention. With reference to FIG.
An OX wafer and a method for manufacturing the OX wafer will be specifically described.

First, a silicon substrate 1 as a base substrate for a SIMOX wafer is prepared (FIG. 7). Silicon substrate 1 in SIMOX wafer of the present embodiment
Uses the same material as the silicon substrate 1 of the first embodiment.

Next, a silicon epitaxial layer 2 is formed on the silicon substrate 1 by using an epitaxial growth method (FIG. 8). The condition of the epitaxial growth method in this case is a condition under which a silicon epitaxial layer 2 in a thin film state can be formed, and a heating temperature is set to 1000 ° C. using a monosilane gas as a raw material, a hydrogen gas as a carrier gas, and the epitaxial growth method under that condition. Then, a silicon epitaxial layer 2 having a thickness of about 500 nm is formed on the silicon substrate 1. When forming the silicon epitaxial layer 2 as the surface silicon layer 4, the conductivity type is set to n-type, and the resistivity is set to 10 Ωcm.
The carrier gas is doped with a phosphine gas.

Thereafter, a buried silicon oxide layer 3 is formed in a region near the interface between the silicon epitaxial layer 2 and the silicon substrate 1, and the silicon epitaxial layer 2 on the buried silicon oxide layer 3 is used as a surface silicon layer 4. And a SIMOX wafer 7 (FIG. 9). In this case, with the silicon substrate 1 on which the silicon epitaxial layer 2 is formed kept at a temperature of 550 ° C., oxygen ions are implanted into the surface of the silicon epitaxial layer 2 under the conditions of ion implantation and the acceleration energy is 180 KeV and the dose is Ion implantation is performed at 2 × 10 ¹⁸ / cm ² .
Then, at a temperature of 1350 ° C. in a nitrogen atmosphere,
The annealing silicon oxide layer 3 is formed by performing annealing for a long time, and the surface silicon layer 4 is disposed on the surface thereof to form the SIMOX wafer 7. This S
In the IMOX wafer 7, the thickness of the surface silicon layer 4 is about 200 nm, the thickness of the buried silicon oxide layer 3 is about 500 nm, and the buried silicon oxide layer 3 is composed of the silicon epitaxial layer 2 and the silicon substrate 1.
And is formed in a state where it exists over both.

According to the method for manufacturing the SIMOX wafer 7 of the present embodiment described above, after the silicon epitaxial layer 2 is formed on the silicon substrate 1, the silicon oxide layer is formed in a region near the interface between the silicon epitaxial layer 2 and the silicon substrate 1. By forming the buried silicon oxide layer 3, the surface silicon layer 4 is disposed on the surface thereof, and the surface silicon layer 4 composed of the silicon epitaxial layer 2 is formed. Therefore, it is possible to obtain a SIMOX wafer 7 having the same effect as the SIMOX wafer 5 of the first embodiment.

(Embodiment 4) FIGS. 10 to 13 are sectional views showing a process of manufacturing a semiconductor integrated circuit device using a SIMOX wafer according to another embodiment of the present invention. The semiconductor integrated circuit device of this embodiment and a method of manufacturing the same will be specifically described with reference to FIG.

First, the SIMOX of the first embodiment described above.
A wafer is prepared, and a field insulating film 8 made of a silicon oxide film is formed in a device isolation region which is a selective region of the surface silicon layer 4 by using a thermal oxidation process (FIG. 10).

Next, a gate insulating film 9 made of silicon oxide is formed in an active region surrounded by the field insulating film 8, and a gate electrode 10 made of conductive polycrystalline silicon is formed on the gate insulating film 9. I do. Gate electrode 10
Is formed by sequentially depositing an insulating film 11 composed of a polycrystalline silicon film and a silicon oxide film on a SIMOX wafer and etching these sequentially. Then, the gate electrode 1
A sidewall insulating film 12 made of silicon oxide is formed on the 0 side wall. Thereafter, a p-type impurity such as boron (B) is ion-implanted into the surface silicon layer 4 to form a p-type semiconductor region 13 serving as a source and a drain (FIG. 11).

Thereafter, the insulating film 1 is formed on the SIMOX wafer.
4 is formed. The insulating film 14 is formed, for example, by depositing a silicon oxide film or the like using a CVD (Chemical Vapor Deposition) method and then, if necessary, using a CMP (Chemical Mechanical Deposition) method.
The surface is planarized using a polishing (chemical mechanical polishing) method to form an insulating film 14 having a flat surface. Thereafter, a contact hole is formed in the insulating film 14 using a photolithography technique and a selective etching technique, and then a wiring layer 15 made of, for example, a conductive polycrystalline silicon layer or an aluminum layer is formed (FIG. 1).
2).

Next, an interlayer insulating film 16 is formed on the SIMOX wafer. The interlayer insulating film 16 is formed by forming an insulating film such as a silicon oxide film using a CVD method.
Thereafter, a through hole is formed in the interlayer insulating film 16 by using a photolithography technique and a selective etching technique, and then a wiring layer 17 made of, for example, an aluminum layer is formed (FIG. 13). Next, using multilayer wiring technology,
By forming a surface protection film (not shown) such as an interlayer insulating film and a wiring layer on the SIMOX wafer, the manufacturing process of the semiconductor integrated circuit device is completed.

According to the above-described semiconductor integrated circuit device using the SIMOX wafer and the method of manufacturing the same according to the present embodiment, since the SIMOX wafer having the surface silicon layer 4 with less silicon oxide precipitate is used, Even if a semiconductor element such as a MOSFET is formed on the surface silicon layer 4 using the surface silicon layer 4 as an active region of the semiconductor integrated circuit device, a high-temperature thermal oxidation treatment or a high-temperature annealing treatment is performed during the manufacturing process. In addition, since the formation of silicon oxide precipitates on the surface silicon layer 4 is reduced, it is possible to prevent the occurrence of defects due to the silicon oxide precipitates and the deterioration of electrical characteristics, and to reduce the production yield of semiconductor integrated circuit devices. Can be improved.

As described above, the invention made by the inventor has been specifically described based on the embodiments of the invention. However, the invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

For example, the SI of the first to third embodiments described above
The MOX wafer uses an n-type silicon substrate 1 and, at the time of forming the silicon epitaxial layer 2 to be the surface silicon layer 4, phosphine gas is doped into a carrier gas to form the n-type silicon epitaxial layer 2.
A p-type silicon epitaxial layer can be obtained by doping diborane (B ₂ H ₆ ) gas into a carrier gas at the time of forming a silicon epitaxial layer to be a surface silicon layer using a silicon substrate of a silicon type. . Further, the SIMOX wafer of the present invention has a surface silicon layer formed of an n-type or p-type silicon epitaxial layer and has the same conductivity type as the silicon substrate. Can be applied to SIMOX wafers having different conductivity types.

In the present invention, the semiconductor integrated circuit device of the fourth embodiment and the method of manufacturing the same use the SIMOX wafer of the first embodiment. Form 3 SIM
A semiconductor integrated circuit device using an OX wafer and a method for manufacturing the same can be provided.

Further, in the semiconductor integrated circuit device and the method of manufacturing the same according to the fourth embodiment, the MOSFET
However, in addition to this aspect, an aspect in which various semiconductor elements such as CMOSFETs and bipolar transistors are formed on the surface silicon layer can be adopted.

Further, the present invention relates to a DRAM, an SRA
The present invention can be applied to various semiconductor integrated circuit devices such as a memory system such as M or a logic system having a CMOS logic circuit and the like and a method of manufacturing the same. In this case, the present invention provides a SIM having a surface silicon layer with low silicon oxide precipitates.
By using OX wafers, for example, DRA
M such as a decrease in refresh time caused by a silicon oxide precipitate of a semiconductor integrated circuit device, a decrease in reliability of a gate silicon oxide film, and an increase in leak current of a pn junction such as a source / drain. Problems can be prevented, and the manufacturing yield of the semiconductor integrated circuit device can be improved.

[0042]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1). According to the method for manufacturing a SIMOX wafer of the present invention, a silicon epitaxial layer is formed on a silicon substrate, and then a silicon oxide layer for embedding is formed inside the silicon epitaxial layer. And a surface silicon layer composed of a silicon epitaxial layer is formed.

Therefore, the silicon epitaxial layer serving as the surface silicon layer has a lower oxygen concentration than the silicon substrate, and has no silicon oxide precipitation nuclei. , It is difficult to form silicon oxide precipitates even if annealing treatment is performed.

As a result, since the surface silicon layer in the SIMOX wafer of the present invention is a silicon epitaxial layer and has a small amount of silicon oxide precipitates, when this surface silicon layer is used as an active region of a semiconductor integrated circuit device, It is possible to prevent the semiconductor integrated circuit device from being defective due to the silicon oxide precipitate and to reduce the electrical characteristics, and to improve the production yield of the semiconductor integrated circuit device.

(2). According to the semiconductor integrated circuit device using the SIMOX wafer and the method of manufacturing the same according to the present invention, the SI having the surface silicon layer with less silicon oxide precipitates
By using the MOX wafer, even if this surface silicon layer is used as an active region of a semiconductor integrated circuit device and a semiconductor element such as a MOSFET is formed on the surface silicon layer, a high-temperature thermal oxidation treatment is performed during the manufacturing process. Alternatively, even when high-temperature annealing is performed, the formation of silicon oxide precipitates on the surface silicon layer is reduced, so that defects due to the silicon oxide precipitates and deterioration of electrical characteristics can be prevented from occurring. In addition, the production yield of the semiconductor integrated circuit device can be improved.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a process for manufacturing a SIMOX wafer according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a process of manufacturing a SIMOX wafer according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a process for manufacturing a SIMOX wafer according to an embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a process of manufacturing a SIMOX wafer according to another embodiment of the present invention.

FIG. 5 is a cross-sectional view showing a process of manufacturing a SIMOX wafer according to another embodiment of the present invention.

FIG. 6 is a cross-sectional view showing a process of manufacturing a SIMOX wafer according to another embodiment of the present invention.

FIG. 7 is a cross-sectional view showing a process of manufacturing a SIMOX wafer according to another embodiment of the present invention.

FIG. 8 is a cross-sectional view showing a process of manufacturing a SIMOX wafer according to another embodiment of the present invention.

FIG. 9 is a cross-sectional view showing a process of manufacturing a SIMOX wafer according to another embodiment of the present invention.

FIG. 10 is a sectional view showing a manufacturing process of a semiconductor integrated circuit device using a SIMOX wafer according to another embodiment of the present invention.

FIG. 11 is a sectional view showing a manufacturing process of a semiconductor integrated circuit device using a SIMOX wafer according to another embodiment of the present invention.

FIG. 12 is a cross-sectional view showing a process of manufacturing a semiconductor integrated circuit device using a SIMOX wafer according to another embodiment of the present invention.

FIG. 13 is a cross-sectional view showing a process of manufacturing a semiconductor integrated circuit device using a SIMOX wafer according to another embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Silicon epitaxial layer 3 Embedding silicon oxide layer 4 Surface silicon layer 5 SIMOX wafer 6 SIMOX wafer 7 SIMOX wafer 8 Field insulating film 9 Gate insulating film 10 Gate electrode 11 Insulating film 12 Side wall insulating film 13 Semiconductor region 14 Insulation Film 15 wiring layer 16 interlayer insulating film 17 wiring layer

Claims (9)

[Claims] 1. A semiconductor device comprising: a silicon substrate as a base substrate; a buried silicon oxide layer; and a surface silicon layer as an element forming region comprising a silicon epitaxial layer on the buried silicon oxide layer. Semiconductor wafer. 2. The semiconductor wafer according to claim 1, wherein
A semiconductor wafer, wherein the buried silicon oxide layer is formed inside a silicon epitaxial layer. 3. The semiconductor wafer according to claim 1, wherein
The semiconductor wafer, wherein the buried silicon oxide layer is formed on a surface of the silicon substrate below a silicon epitaxial layer as the surface silicon layer. 4. The semiconductor wafer according to claim 1, wherein
The buried silicon oxide layer is formed in both the silicon epitaxial layer and the silicon substrate in a region near an interface between the silicon epitaxial layer as the surface silicon layer and the silicon substrate. Semiconductor wafer. 5. The semiconductor wafer according to claim 1, wherein the surface silicon layer is made of an n-type or p-type silicon epitaxial layer, and is the same as the silicon substrate. A semiconductor wafer having a conductivity type. 6. A step of forming a silicon epitaxial layer on a silicon substrate as a base substrate using an epitaxial growth method, and oxygen ions are implanted into the silicon epitaxial layer from the surface of the silicon epitaxial layer. Forming a buried silicon oxide layer inside the silicon epitaxial layer by performing an annealing process, and arranging a surface silicon layer on the buried silicon oxide layer. Manufacturing method. 7. A step of forming a silicon epitaxial layer on a silicon substrate as a base substrate by using an epitaxial growth method, and oxygen ions from a surface of the silicon epitaxial layer are supplied to the silicon substrate under the silicon epitaxial layer. Performing an annealing process to form a buried silicon oxide layer on the silicon substrate and arranging a surface silicon layer on a silicon epitaxial layer above the buried silicon oxide layer. A method for manufacturing a semiconductor wafer. 8. A step of forming a silicon epitaxial layer on a silicon substrate as a base substrate by using an epitaxial growth method, and forming oxygen ions from a surface of the silicon epitaxial layer between the silicon epitaxial layer and the silicon substrate. After ion implantation into the region near the interface, an annealing process is performed to form a buried silicon oxide layer in both the silicon epitaxial layer and the silicon substrate in the region near the interface, and to embed the buried silicon oxide layer. Arranging a surface silicon layer on the silicon epitaxial layer above the semiconductor wafer. 9. A method for manufacturing a semiconductor integrated circuit device, comprising: forming a plurality of semiconductor elements on a surface silicon layer of the semiconductor wafer according to claim 1. Description: