JPH10108353A - Load failure discriminating device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To discriminate failure occurrence accurately not only when a load becomes in an abnormal condition continuously but also when it becomes in such an abnormal condition as repeatability is unstable like layer short by discriminating it as a load failure if at least one of an abnormal condition integrated time value and an abnormal condition integrated frequency value reaches a prescribed value. SOLUTION: A micro processor 1 outputs a power source control signal and a load driving control signal, and an IC3 outputs load driving voltage and a diagnosing. The diagnosing signal and the load driving control signal are supplied to the micro processor 1 as diagnostic response signals through an XOR gate 6. When load 2 is normal, the diagnostic response signal is always low. When the load 2 is short-circuited or open-circuited or the IC3 is in an overheated condition, the diagnostic response signal is the one including HIGH. The micro processor 1 calculates the abnormal condition integrated time value and the abnormal condition integrated frequency value, and if at least one of them reaches a prescribed value, it discriminates as a failure.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for determining a failure of a load of an electromagnetic actuator or the like in a vehicle such as an automobile, a ship, an aircraft, or the like.

[0002]

2. Description of the Related Art FIG. 1A shows a judgment apparatus including a microprocessor 1 for judging a failure of a load such as an electromagnetic actuator for controlling a gear shift of a transmission in an automobile. The microprocessor 1 is usually a CPU,
It is composed of a RAM and a ROM (not shown), and also takes in signals from various sensors to make various determinations, and stores and executes a program for failure determination and the like, and stores and reads data. The microprocessor 1 supplies a load drive control signal for controlling the load 2 from the port P2 to the input terminal VIN of the IC3. The IC 3 includes a drive circuit 31 as shown in FIG. 1 (B). When the load drive control signal VIN is received from the input terminal, the drive circuit 31 applies a low voltage to the gate of the drive transistor 32 to make it conductive. The voltage Vb is supplied from the turned-on drive transistor 32 to the load 2 via the output terminal. At this time, if the load circuit including the load 2 (hereinafter simply referred to as the load 2) is in an abnormal state in which it is short-circuited, the potential of the output potential VO of the IC 3 becomes the same potential as the ground potential GND, and does not become the load driving voltage Vb.
On the other hand, when a circuit such as disconnection occurs in the load 2,
During the period when the voltage Vb is not supplied from VO, the potential VO of the output terminal becomes a potential obtained by subtracting the Zener voltage by the Zener diode 4 from the power supply voltage VB. Therefore, by detecting the output terminal potential VO in relation to VIN in the diagnostic circuit 33, it is possible to diagnose an abnormal state such as a short circuit or open circuit of the load 2. The diagnostic circuit 33 outputs the diagnostic result from the DIAG terminal as a diagnostic signal. The output diagnostic signal is supplied to the port P1 of the microprocessor 1,
The determination of the failure of the load 2 is performed by the determination routine in (1). Details regarding this determination routine will be described in the description of FIG. 1A, a power control signal from a port P0 of the microprocessor 1 is supplied to a base of a power transistor 5 for controlling power supply to the IC 3. This power supply transistor 5
Switch operates in response to the supplied power control signal, and I
In order to prevent heat generation of C3, power supply from power supply VB to power supply input Vb of IC3 is prohibited. Further, the IC 3 includes a regulator 35 therein, and supplies a stable power to the drive circuit 31, the diagnostic circuit 33, and the protection circuit 34.

FIG. 2 shows the load drive control signal VIN described above,
An output terminal potential VO corresponding to the state of the load 2 and a diagnostic signal D issued from the diagnostic circuit 33 for this load drive voltage
3 shows an IAG signal waveform. When the load 2 is normal, the load 2 is in a controllable state by the load drive control signal, so that the output terminal potential VO has the same waveform as the load drive control signal VIN, and the diagnostic signal DIAG at this time is also the load drive control signal VIN. It has the same waveform as the control signal. When the load 2 is in an open circuit state and the load drive control signal VIN is LOW, the output terminal potential VO becomes a potential obtained by subtracting the Zener voltage from the power supply voltage.
GH. When the load 2 is in the short-circuit state, the output terminal potential VO becomes the same potential as GND, so that the corresponding diagnostic signal DIAG becomes LOW. Further, when the IC 3 itself becomes overheated, the protection circuit 34 operates to deactivate the drive open circuit 31 to cut off Vb, so that the output terminal potential VO becomes LOW, and a LOW signal is output as the diagnostic signal. Therefore, when the load 2 is normal, the diagnostic signal always has the same waveform as the load drive control signal VIN. When the load 2 is abnormal and the protection circuit 34 operates, the drive circuit 31 is forcibly deactivated. , The load drive control signal VIN is set to HIGH or LOW and the diagnostic signal DIAG is set to HI
It will not match GH or LOW. Based on this, the load 2 is determined in the microprocessor 1.

Next, a determination routine for determining a failure of the load 2 in the microprocessor 1 will be described with reference to a flowchart of FIG. First, a CPU (not shown) in the microprocessor 1 starts a determination routine in accordance with the load drive timing, for example, immediately before a load drive signal is generated. In the first step S1, the diagnostic signal DIA output from the IC3 and supplied to the port P1
The contents of the diagnostic signal DIAG are captured by sampling G or the like. Next, the diagnostic signal DIAG is compared with the drive load control signal VIN (step S2). This comparison is performed as described with reference to FIG.
If AG does not coincide with the load drive control signal VIN, it is determined that an abnormality has occurred in the load 2.
Is determined to be normal. When it is determined that the load is normal, the clock signal in the microprocessor 1 and the timer constituted by the RAM are reset (Step S).
3), end the determination routine. If it is determined in S2 that an abnormality has occurred in the load 2, the value of the timer is integrated for a predetermined time (step S4). Next, a comparison is made between the integration time indicated by the timer and a predetermined time set in advance (that is, the maximum integration time) (Step S).
5). If the integration time indicated by the timer exceeds the maximum integration time, it is determined that the load has failed (step S
6), end the determination routine. If the integration time of the timer does not exceed the maximum integration time, the determination routine ends as it is.

As is clear from the above-described determination routine,
When the load 2 is diagnosed as normal, the timer is reset. Therefore, the accumulated time by the timer indicates the accumulated time when the diagnosis circuit 33 continuously diagnoses the load 2 as abnormal. This will be described with reference to FIG. The abscissa indicates the time of diagnosis, and the ordinate indicates the integrated time of the abnormal state in which the load 2 has been diagnosed as having an abnormality. When the load 2 is diagnosed to be normal, the abnormal state accumulated time by the timer is always reset.
The abnormal state integration time is zero. After it is diagnosed that an abnormality has occurred in the load 2, the abnormal state integrated time by the timer is integrated, so that the abnormal state integrated time increases in proportion to the time. When the diagnosis time increases and the abnormal state integration time exceeds a predetermined maximum integration time set in advance, it is determined that the load 2 has failed. This determination method is effective when the load 2 is continuously diagnosed as normal and abnormal as shown in FIG.

However, there is a case where a state called a rare short circuit occurs in which the load 2 is repeatedly short-circuited in a short time. For example, although the load 2 is not completely short-circuited, the resistance value may be extremely low.
The heat value of C3 becomes large, and the overheat protection circuit 34 of IC3 itself becomes large.
Operates to forcibly deactivate the drive circuit. Then, the diagnostic signal DIAG indicates an abnormality. However, after a while, the overheating of the IC 3 is stopped.
, The forced stop of the drive circuit 31 is released, and the diagnostic signal DIAG indicates normal. However, if the incomplete short-circuit state of the load 2 continues, the diagnostic signal DIAG again indicates an abnormality. As a result, the diagnostic signal DIAG repeats abnormal and normal in a short time. Figure 4 shows this situation.
This will be described with reference to FIG. As in FIG. 4A, the horizontal axis represents time, and the vertical axis represents abnormal state integration time. If it is diagnosed that an abnormality has occurred in the load 2, the abnormal state integrated time is integrated, but if it is diagnosed even once, the abnormal state integrated time accumulated up to that time is reset. Therefore, when a rare short occurs and the diagnostic signal diagnosed as normal and abnormal is issued alternately with respect to time in a short time, the abnormal state integration time does not reach the maximum integration time even if time passes. For the above reasons, the conventional determination method cannot determine a load failure when a rare short circuit occurs.

[0007]

SUMMARY OF THE INVENTION In view of the above circumstances, the present invention provides a load failure judging device capable of judging not only a case where a load continuously becomes abnormal but also a case where a rare short circuit occurs. It is intended to provide.

[0008]

According to the present invention, there is provided an apparatus for determining a load failure, comprising: a load driving means for driving a load; a load driving control means for outputting a load driving control signal for controlling the load driving means; A load failure determining device including: a diagnostic signal generating unit configured to generate a diagnostic signal based on a load current flowing through the load; and a determining unit configured to determine a failure of the load based on the diagnostic signal and the load drive control signal. An arithmetic processing means for arithmetically processing the diagnostic signal and the load drive control signal to generate a diagnostic response signal; and an abnormal state integration obtained by integrating a time during which the diagnostic response signal indicates an abnormality. A time integrating means for obtaining a time value; a frequency integrating means for obtaining an abnormal state integrated frequency value obtained by integrating the number of times the diagnostic response signal indicates an abnormality; At least one state integration number value and wherein said load failure and the determining means, be made of when it reaches a predetermined value.

[0009]

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 5 shows a load failure determination device according to an embodiment of the present invention. Note that components corresponding to those of the conventional example shown in FIG. 1 are denoted by the same reference numerals. A load drive control signal VIN for controlling the load 2 is supplied to the input terminal of the IC 3 from the port P2 of the microprocessor 1. IC3 is the IC shown in FIG.
3, which outputs Vb as the output terminal potential VO to drive the load 2 and outputs the diagnostic signal DIAG. The diagnostic signal DIAG and the load drive control signal VIN are XO
The operation is performed by the R gate and supplied to the port P1 of the microprocessor 1 as a diagnostic response signal. The microprocessor 1 determines a failure using the diagnostic response signal.

FIG. 6 shows a signal waveform of a diagnostic response signal obtained by performing an XOR operation on the load drive control signal VIN and the diagnostic signal DIAG. The four states shown in FIG. 6 are, similarly to the state shown in FIG. 2, a normal state, an open circuit, and a short circuit of the load 2, and an overheat state by the self-diagnosis of the overheat protection circuit. When the load 2 is normal, the diagnostic response signal RD subjected to the XOR operation is always LOW. When the load 2 is open, the diagnosis response signal RD is a signal in which HIGH and LOW are reversed with respect to the load drive control signal VIN. When the load 2 is in a short-circuit state, the diagnostic response signal RD is obtained as a signal having the same waveform as the load drive control signal VIN. When the IC 3 has an overheating abnormality, the diagnosis response signal RD has the same waveform as the load drive control signal VIN. From the above, if the load 2 is normal, the diagnostic response signal RD
Is always LOW, and when the load 2 or the diagnostic circuit 33 is abnormal, the diagnostic response signal RD always contains HIGH. Therefore, if the diagnostic response signal RD does not include HIGH, the load 2 and the diagnostic circuit 33 can be diagnosed as normal. By using this diagnostic response signal, the determination in the microprocessor 1 is made by a simpler logic than the conventional failure determination in which the determination is made using two kinds of signals, the load drive control signal VIN and the diagnostic signal DIAG.

Next, a routine for determining a failure of the load 2 in the microprocessor 1 will be described with reference to FIG. First, in this routine, the diagnostic response signal RD supplied to the port 1 is taken in by sampling or the like (step S11). Next, it is determined whether the captured diagnosis response signal RD is abnormal (step S12). If the current value of the diagnosis response signal RD is a signal indicating an abnormality of the load 2, a time counter (not shown) in the microprocessor 1 is counted up to accumulate the abnormal state accumulated time (step S13). Further, the number counter (not shown) in the microprocessor 1 is counted up and the number of times of abnormal state integration is integrated (step S14). Next, the abnormal state integration time is compared with a preset maximum integration time (step S15). If the abnormal state integration time does not exceed the maximum integration time, the process proceeds to the next step, where the abnormal state integration number is compared with a preset maximum number of diagnoses (step S16). If the total number of abnormal conditions does not exceed the maximum number of diagnostics,
It is determined that the load 1 is normal (step S17). If it is determined in step S15 that the abnormal state integration time has exceeded the maximum integration time,
In step S1, if it is determined that the number of times of abnormal state integration has exceeded the maximum number of diagnoses, the load 1 is determined to have failed (step S1).
8) Yes. If the diagnostic response signal RD indicates normal in step S12, the abnormal state integration time of the time counter is reset (step S19), and the diagnostic response signal stored in the RAM of the microprocessor 1 in advance. If the previous value of RD is a signal indicating normality, the number of times of abnormality diagnosis integration of the number counter is reduced by a predetermined number of times (step S21), and the process proceeds to step S17 to determine that the load is normal. If the previous value of the diagnostic response signal RD is a signal indicating an abnormality, step S17
To determine that the load is normal.

FIG. 8 shows changes in the abnormal state integration time and the abnormal state integration number by the failure determination device according to the present invention. When a rare short circuit occurs in the load 2, the abnormal state integration time by the time counter is reset every time the state becomes normal (FIG. 8A). However, each time the load 2 is diagnosed as an abnormal state, the cumulative number of times of the abnormal state is accumulated (FIG. 8B). Further, when the load 2 is diagnosed as normal after being diagnosed as abnormal, the abnormal state integration number holds the current value. If the load 2 is continuously diagnosed as normal two or more times, it is determined that the load 2 has returned to the normal state, and the number of times of abnormal state integration is reduced by a predetermined number. By performing the above determination, the load 2
Can be determined both when the abnormality is continuously diagnosed and when a rare short circuit occurs.

In the above-described embodiment, the method of performing the XOR operation on the diagnostic reference signal and the diagnostic response signal RD has been described as being implemented by hardware using a logic circuit or the like. Obviously, it can also be realized by software.

[0014]

As described above, in the load failure judging device according to the present invention, when the load is continuously in an abnormal state, the judgment is made based on the abnormal state integration time, and the reproducibility such as a rare short is obtained. In the case of an unstable abnormal state, a judgment is made based on the number of abnormal state integrations reflecting the previous load diagnosis result, and a judgment method according to the load state is provided. It becomes possible.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a conventional example of a load failure determination device.

FIG. 2 is a graph showing a relationship between a load drive control signal, a load drive voltage, and a diagnostic signal.

FIG. 3 is a flowchart showing a failure determination routine in a conventional load failure determination device.

FIG. 4 is a graph showing the change in the integration of the abnormal state integration time by the timer when the normal / abnormal state of the load is clear, and the change in the integration of the abnormal time integration time by the timer when a rare short circuit occurs in the load. A graph showing.

FIG. 5 is a block diagram showing a load failure determination device according to the present invention.

FIG. 6 is an XO diagram of the load control signal and the diagnostic signal in FIG.
9 is a graph showing a signal subjected to an R process.

FIG. 7 is a flowchart showing a failure determination routine in the load failure determination device according to the present invention.

FIG. 8 is a graph showing a change in an abnormal state integration time and an abnormal state integration number when a rare short circuit occurs in a load when the load failure determination device according to the present invention is used.

[Description of Signs of Main Parts]

 Reference Signs List 1 microprocessor 2 load 3 IC 4 diode 5 power supply transistor 6 XOR gate 31 drive circuit 32 drive transistor 33 diagnostic circuit 34 protection circuit

Claims (7)

[Claims] 1. A load driving unit for driving a load, a load driving control unit for outputting a load driving control signal for controlling the load driving unit, and a diagnostic signal for generating a diagnostic signal based on a load current flowing through the load. A load failure determination device comprising: a generation unit; and a determination unit configured to determine a failure of the load based on the diagnosis signal and the load drive control signal, wherein a relationship between the diagnosis signal and the load drive control signal is provided. A time integrating means for obtaining an abnormal state integrated time value obtained by integrating the time in which an abnormality is indicated, and a frequency integrating means for obtaining an abnormal state integrated number value obtained by integrating the number of times in which the relationship indicates an abnormality. A determination means for determining that the load has failed when at least one of the abnormal state integrated time value and the abnormal state integrated count value has reached a predetermined value. Constant apparatus. 2. The load failure judging device according to claim 1, wherein said time integrating means initializes said abnormal state integrated time when said relationship indicates normal. 3. The load failure judging device according to claim 1, wherein said count integrating means gradually subtracts said abnormal state integrated count value as long as said relationship indicates normal. 4. The apparatus according to claim 1, wherein said determining means further comprises an arithmetic processing means for arithmetically processing said diagnostic signal and said load drive control signal to generate a diagnostic response signal representing said relationship. Load failure judgment device. 5. The load failure judging device according to claim 1, wherein said time integrating means judges normal or abnormal based on a sample value obtained by sampling said diagnostic response signal. 6. The load fault judging device according to claim 1, wherein the number-of-times accumulating means judges normal or abnormal based on a sample value obtained by sampling the diagnostic response signal. 7. The load failure judging device according to claim 1, wherein both the load drive control signal and the diagnosis response signal are binary signals, and the arithmetic processing means comprises an exclusive OR gate.