JPH10108080A - Solid-state image-pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To be easily adapted even to a video processing system for which normal interlace scanning is a premise without damaging an information amount form an image-pickup part by delaying the output of a first horizontal transfer register worth one vertical scanning period. SOLUTION: The output of a video processing circuit part 1 for processing the output of a horizontal transfer register 4 of a solid-state image-pickup part 100 is inputted to a delay circuit 13 for performing delay for one vertical scanning period and delayed output is respectively impressed to the B contact point of a switch circuit 15 and the A contact point of the switch circuit 16. The output of the video processing circuit 2 for processing the output of the horizontal transfer register 5 is respectively directly impressed to the A contact point of the switch circuit 15 and the B contact point of the switch circuit 16. The selected outputs of the switches 15 and 16 are respectively led out as video outputs #1 and #2 through buffers 8 and 9. A control circuit 12 receives vertical synchronization signals from a synchronization signal generating circuit 10 and generates switch control signals 202, and the switch circuits 15 and 16 are synchronized with each other and changeover controlled by the control signals 202.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device, and more particularly to an improvement of a frame shutter type solid-state imaging device.

[0002]

2. Description of the Related Art A so-called frame shutter type solid-state imaging device capable of reading out charges of all photoelectric conversion elements within one vertical scanning period is becoming popular. Solid-state imaging unit 10 used in this type of solid-state imaging device
FIG.

A plurality of photoelectric conversion elements P11 to Pmn are composed of n rows × m
The columns are two-dimensionally arranged in a matrix of columns, and vertical transfer registers 31 to 3m are provided in one-to-one correspondence with all columns of the matrix array. The constituent elements of the vertical transfer register 31 provided corresponding to the first column are provided corresponding to the photoelectric conversion elements P11 to P1n of the first column, respectively. We take in each one.

The electric charge taken into each of these constituent elements is synchronized with a transfer pulse (not shown) by the vertical transfer register 3.
In FIG. 1, the data is sequentially transferred downward (vertically) from the top of the figure.

The same applies to the other vertical transfer registers 32 to 3m in the second to m-th columns.

Each transfer output of each of the vertical transfer registers 31 to 3m is taken into each of the constituent elements of the two horizontal transfer registers 4 and 5, and in synchronization with a transfer pulse (not shown), Are sequentially transferred to the right (horizontal direction), and are derived via output buffers 6 and 7, respectively.

In this case, during the horizontal blanking period, each charge of the odd-numbered photoelectric conversion element (belonging to the odd-numbered row) is transferred to the horizontal transfer register 5 and the even-numbered photoelectric conversion element (belonging to the even-numbered row) is transferred. Are transferred to the horizontal transfer register 4.

The electric charges transferred to these two horizontal transfer registers 4 and 5 are sequentially output within the effective video period. That is, the charges of the odd-numbered photoelectric conversion elements are read continuously from the horizontal transfer register 5, and the charges of the even-numbered photoelectric conversion elements are read from the horizontal transfer register 4.

FIG. 4 shows a timing chart of an output signal of the solid-state imaging section 100 of FIG. In FIG.
Denotes an output signal from an even-numbered photoelectric conversion element, that is, an output signal of an even-numbered field, and O denotes an output signal from an odd-numbered photoelectric conversion element, that is, an output signal of an odd-numbered field. The numbers 1 to 5 of the vertical synchronization signal indicate the numbers of the vertical scanning period.

As described above, with the configuration of FIG. 3, it is possible to read out the charges of all the odd-numbered and even-numbered photoelectric conversion elements within one vertical scanning period.

Conventionally, as an example of a solid-state imaging device using such a frame shutter type solid-state imaging section 100,
There is a configuration as shown in FIG. In this example, the solid-state imaging unit 1
Outputs of the two horizontal transfer registers 00 and 00 (in FIG. 5, the output buffers 6 and 7 in FIG. 3 are omitted for simplification) are input to the video processing circuits 1 and 2, respectively. Video processing is performed, and the video output is derived as video outputs # 1 and # 2 via buffers 8 and 9, respectively.

The driving pulse 2 of the solid-state imaging unit 100
01 is generated by the image sensor driving circuit 11. The image sensor drive circuit 11 generates a drive pulse 201 based on the synchronization signal from the synchronization signal generation circuit 10.

FIG. 6 is a time chart of signals of the apparatus shown in FIG. 1 is the signal output from the even-numbered photoelectric conversion elements in one vertical scanning period, and 10 is N
o. It is a signal output from an odd-numbered photoelectric conversion element in one vertical scanning period.

FIG. 7 is a block diagram showing another example of a conventional solid-state image pickup device using a frame shutter type solid-state image pickup unit 100, and the same parts as those in FIG.

In the present embodiment, a signal output from the horizontal transfer register 4 and passed through the video processing circuit 1 is delayed by one vertical scanning period using a delay circuit 13 and output. Then, a signal output from the horizontal transfer register 5 and passed through the video processing circuit 2 is used as another input of the adder 14.

By doing so, the same signal as in normal interlaced scanning can be obtained, as shown in the time chart of the signal in FIG.

In the examples shown in FIGS. 5 and 6, signals for two fields are simultaneously generated every one vertical scanning period, so that twice the amount of information as in normal interlaced scanning can be obtained. In addition, in the examples shown in FIGS. 7 and 8, since a normal interlaced signal is obtained, an image can be displayed on a normal television monitor, and thus it can be easily adapted to a conventional image processing system.

[0018]

The first problem is that the conventional examples shown in FIGS. 5 and 6 cannot be adapted to a video processing system on the premise of ordinary interlacing. For this reason, a dedicated processing system is required. The reason is 2
This is because two systems of video signals are output simultaneously.

The second problem is that in the conventional examples shown in FIGS.
That is, the information amount is reduced by half compared with the conventional example of FIGS. The reason is that since the video signals from the two systems of image sensors are integrated into one system, the signals are thinned out and output every other vertical scanning period.

An object of the present invention is to solve all the problems of the conventional example described above and easily adapt to a video processing system on the premise of ordinary interlaced scanning without impairing the amount of information from the imaging section. An object of the present invention is to provide a solid-state imaging device.

[0021]

According to the present invention, a plurality of photoelectric conversion elements are two-dimensionally arranged, and the signal charges of all of these photoelectric conversion elements are transferred to the first and second photoelectric conversion elements within one vertical scanning period. 2. A solid-state imaging device having an imaging unit derived through two horizontal transfer registers, the delay unit delaying an output of the first horizontal transfer register by one vertical scanning period, and an output of the delay unit. First and second switch means for alternately deriving the output of the second horizontal transfer register, and switching control for synchronizing the first and second switch means every one vertical scanning period A solid-state imaging device comprising:

The control means controls the switching of these switch means so that an interlaced video signal output is obtained at each output of the first and second switch means. In this case, the control unit controls the second switch unit to derive the output of the second horizontal transfer register when the first switch unit derives the output of the delay unit. It is characterized by:

Further, the image pickup unit includes a vertical transfer unit for transferring signal charges from the photoelectric conversion element in a vertical direction, and an odd-numbered and an even-numbered one-line charge transferred from the vertical transfer unit. An odd-numbered and even-numbered line horizontal transfer unit for taking in and transferring in the horizontal direction is provided, wherein the odd-numbered and even-numbered line horizontal transfer units are the first and second horizontal transfer registers.

In describing the operation of the present invention, two signals for selectively deriving a signal obtained by delaying one of the outputs of the two horizontal transfer registers by a delay circuit for one vertical scanning period and the other output signal, respectively, are provided. By providing a switch circuit and performing switching control of these two switch circuits in synchronization with each other every vertical scanning period, an interlaced video signal can be obtained from each of the outputs of these two switch circuits. .

[0025]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of the embodiment of the present invention, and the same parts as those in FIGS. 3, 5, and 7 are denoted by the same reference numerals. Referring to FIG. 1, the solid-state imaging unit 100
Processing circuit 1 that processes the output of horizontal transfer register 4
Is input to the delay circuit 13 which is delayed by one vertical scanning period. This delay output is applied to the B contact of the switch circuit 15 and to the A contact of the switch circuit 16, respectively.

The output of the video processing circuit 2 for processing the output of the horizontal transfer register 4 is directly applied to the A contact of the switch circuit 15 and the B contact of the switch circuit 16, respectively. The selected outputs of these switch circuits 15 and 16 are derived as video outputs # 1 and # 2 via buffers 8 and 9, respectively.

The control circuit 12 receives the vertical synchronizing signal from the synchronizing signal generating circuit 10 and generates a switch control signal 202. The switch circuits 15 and 16 are switched and controlled in synchronization with each other by the switch control signal 202. Shall be.

FIG. 2 is a timing chart of signals of various parts showing the operation of the circuit of FIG. The switch circuits 15 and 16 derive the signal on the contact A side when the switch control signal is at a low level, and derive the signal on the contact B side when the switch control signal is at a high level. The state is shown in the lowermost row of FIG. 2, and "A" and "B" indicate "A contact" and "B contact", respectively.

As is clear from FIGS. 1 and 2, the output # 1 of the buffer amplifier 8 is 1O, 1E, 3O, 3E, 5O,
5E, ... Similarly, output # 2 of buffer 9 is 2
O, 2E, 4O, 4E, 6O, 6E,... These outputs # 1 and # 2 are interlaced together in this way, and the information from the imaging unit 100 is not lost.

Therefore, the outputs of the buffer amplifiers 8 and 9 can be displayed on a television monitor for normal interlaced scanning, and can be easily adapted to a video system based on conventional interlaced scanning. It is.

[0032]

As described above, according to the present invention, it is possible to obtain an interlace signal with a very simple structure without impairing the information amount at all, and therefore a conventional television which is premised on interlace. There is an effect that it can be easily applied to a monitor and a video processing system.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the block in FIG.

FIG. 3 is a configuration diagram of a frame shutter type solid-state imaging unit.

FIG. 4 is a timing chart showing an operation of the solid-state imaging unit in FIG. 3;

FIG. 5 is a diagram illustrating an example of a conventional solid-state imaging device using the solid-state imaging unit in FIG. 3;

6 is a timing chart showing the operation of the device shown in FIG.

FIG. 7 is a diagram illustrating another example of a conventional solid-state imaging device using the solid-state imaging unit in FIG. 3;

FIG. 8 is a timing chart showing the operation of the device of FIG. 7;

[Explanation of symbols]

 1, 2 video processing circuit 4, 5 horizontal transfer register 6 to 9 buffer 10 synchronization signal generation circuit 11 image sensor drive circuit 12 control circuit 13 delay circuit 15, 16 switch circuit 31 to 3m vertical transfer register 100 solid-state imaging unit

Claims (4)

[Claims] 1. A plurality of photoelectric conversion elements are two-dimensionally arranged, and signal charges of all of these photoelectric conversion elements are derived via first and second horizontal transfer registers within one vertical scanning period. A solid-state imaging device having an imaging unit configured as described above, wherein a delay unit that delays an output of the first horizontal transfer register by one vertical scanning period; an output of the delay unit and an output of the second horizontal transfer register. And first and second switch means for alternately deriving the first and second control means, and control means for switching control of the first and second switch means in synchronization with each one of the vertical scanning periods. Solid-state imaging device. 2. The apparatus according to claim 1, wherein the control means controls the switching of the first and second switch means so that an interlaced video signal output is obtained at each output of the first and second switch means. The solid-state imaging device according to claim 1. 3. The control means, when the first switch means is outputting the output of the delay means, the second switch means
3. The solid-state imaging device according to claim 2, wherein said switch means controls to derive the output of said second horizontal transfer register. 4. The image pickup section includes: a vertical transfer section for transferring signal charges from the photoelectric conversion element in a vertical direction; and an odd-numbered and even-numbered one-horizontal-line charge transferred from the vertical transfer section, respectively. 2. An odd-numbered and even-numbered line horizontal transfer unit for taking in and transferring in the horizontal direction, wherein the odd-numbered and even-numbered line horizontal transfer units are the first and second horizontal transfer registers. 3. The solid-state imaging device according to any one of 3.