JPH10107690A - Signal extract circuit and correlation device using it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain phase information from a transmission modulation signal D3 that represents a binary value of PN code data in terms of phases for a plurality of cycles. SOLUTION: An input signal D3 is respectively sampled and held by sample- and-hold circuits 121-124. In this case, one period of the input signal D3 is used for a unit and points of the input signal except zero cross points are sampled and held in timings apart by one unit or over. Output signals D41-D44 are added by an adder 13, from which a signal D5 representing the phase by the polarity is generated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal extracting circuit for directly extracting phase information from an input signal in which binary ("1", "0") of code data is represented by phases of a plurality of cycles, and The present invention relates to a correlator for spread spectrum communication used.

[0002]

2. Description of the Related Art In a spread spectrum communication, as shown in FIG.
Multiply by N-sequence code data D2 (however, transmission data D
"0" of 1 is considered to be -1. ), And the multiplication data “D1
× D2 ”is subjected to BPSK modulation to generate a transmission modulation signal D3, which is transmitted to a transmission path.

The PN code data D2 is obtained by converting "1" of the transmission data D1 into data of plural bits (for example, 32 bits) of "1" and "0". “1” or “0” of the PN code data is called “chip” in spread spectrum communication. In BPSK modulation, the P
The carrier modulation is inverted at the rising edge and the falling edge of the N code data D2, and the transmission modulation signal D3 representing the information of "1" and "0" of the PN code data D2 in phase.
It is assumed that. For example, 190 cycles are assigned to this transmission modulation data D3 per chip of the PN code data D2 (however, it is represented by 5 cycles in FIG. 11).

On the receiving side, the above-mentioned transmission modulation signal D3 is fetched and converted by a frequency converter (not shown) such as a down converter into a frequency signal of one cycle per chip of PN code data D2. Is input to the correlator having the configuration shown in FIG.
Is demodulated and reproduced.

In the correlator shown in FIG. 12, reference numeral 1 denotes a signal transfer unit utilizing a CCD or the like, and the input transmission modulation signal D3 (one cycle as described above) receives the chip rate of the PN code data D2 and the chip rate. Each of the cells 1a is sequentially fetched as binary data of a positive peak (+1) or a negative peak (-1) by the clock signal φ1 of the same frequency.
Is output from each of the cells 1a while being transferred. The data (+1, -1) output from each cell 1a is multiplied by the multiplier 2
Is multiplied by a coefficient of a spreading code (a code corresponding to the PN code data D2) set in advance in each multiplier 2a ("1" is +1 and "0" is -1).

Therefore, at the timing when the same data as the coefficient of the PN code data D2 is output from each cell 1a of the signal transfer unit 1, the multiplication result of each multiplier 2a is 1 (=
+ 1 × + 1 = −1 × −1), and these are added by the adder 3, so that the added output becomes a peak value (correlation peak). For example, when the chip length is 32 chips and the number of cells 1a of the signal transfer unit 1 is 32, the value of the correlation peak is 3
It becomes 2.

The PN code data D2 corresponding to "0" of the transmission data D1 is obtained by inverting each bit of the PN code data D2 corresponding to "1" of the transmission data D1. At the timing when the same data as the sequence of the PN code data D2 corresponding to “0” is fetched, the multiplication result of each multiplier 2a is −1 (= + 1 × −1).
And the addition is performed by the adder 3, so that the peak value becomes negative. When the number of cells 1a is 32 as described above,
The value of the correlation peak is -32.

The correlation peak obtained from the adder 3 as described above is identified by a comparator (not shown) as "1" when it is positive and "0" when it is negative. The transmitted data D1 is restored / reproduced and output to the subsequent stage. As described above, by setting the multiplication coefficient corresponding to the PN code data D2 on the transmission side in the correlator, the transmission data D1 identified by the PN code data D2 can be captured.

The data of the correlation peak is input to a synchronizing signal generator 5, which controls the clock generator 4 by the obtained synchronizing signal so that the phase of the clock signal φ1 becomes the phase of the transmission modulation signal D3. Controlled to fit.

[0010]

By the way, as described above, the modulated transmission modulation signal D3 has a very high carrier frequency.
The clock φ1 for operating the correlator must also match the frequency. However, this may exceed the operating frequency limit of the signal transfer unit 1, and the number of cells 1a of the signal transfer unit 1 becomes enormous and consumed. The power becomes very large.

Therefore, conventionally, as described above, the transmission modulation signal D3 is converted by the frequency converter into PN code data D2.
Is converted into a signal of 1 cycle (or 1 to 2 cycles) per 1 bit, and then taken into the correlator. However, when the signal passes through the frequency converter, the waveform is distorted by the intermodulation and the transmission data is distorted. There is a problem that an error occurs in taking out D1.

The present invention has been made in view of the above points, and an object of the present invention is to directly extract phase information from an input signal in which binary values of code data are represented by phases of a plurality of cycles. Another object of the present invention is to provide a signal extraction circuit which does not require a frequency converter and a correlator using the same.

[0013]

According to a first aspect of the present invention, there is provided a signal extraction circuit for directly extracting phase information from an input signal in which binary values of code data are represented by phases of a plurality of cycles,
A plurality of sample-and-hold circuits for individually sampling and holding the input signal; and an adder for adding output signals of the plurality of sample-and-hold circuits, wherein each of the sample-and-hold circuits is a unit of one cycle of the input signal. A point other than the zero cross point of the input signal is sampled and held by each sample and hold signal which is activated at a timing shifted by one unit or more, and the adder generates a signal representing the phase by polarity.

According to a second aspect of the present invention, there is provided a signal extracting circuit for directly extracting phase information from an input signal in which binary values of code data are represented by phases of a plurality of cycles, comprising a plurality of cascaded sample-and-hold circuits; An adder for adding outputs from the second stage to the final stage of the plurality of sample-hold circuits, and controlling an odd-numbered stage of the plurality of sample-hold circuits with a sample-hold signal having the same frequency as the input signal. Then, a sample and hold is performed at a timing excluding the zero cross point of the input signal, and an even-numbered stage is controlled by a sample and hold signal having a phase opposite to that of the sample and hold signal.

According to a third aspect of the present invention, there is provided a signal extracting circuit for directly extracting phase information from an input signal in which binary values of code data are represented by a plurality of cycles of phases, wherein the signal extracting circuit is opened and closed by a clock signal having the same frequency as the input signal. A switch circuit for receiving a signal of a half cycle of the input signal; an integrator that integrates a signal passing through the switch circuit and is reset every period corresponding to a bit rate of the code data; and resetting the integrator. And a sample-and-hold circuit for holding the immediately preceding signal.

According to a fourth aspect of the present invention, an input section of the signal extracting circuit according to the first aspect of the present invention has the same configuration as that of the signal extracting circuit according to the first aspect of the invention, and the sample-and-hold signal is the signal of the first aspect of the present invention. Another signal extraction circuit that operates with a sample-and-hold signal shifted by a half cycle of the input signal with respect to the sample-and-hold signal of the extraction circuit is connected in parallel, and the difference between the output signals of both signal extraction circuits is calculated by a differential amplifier. Or the input section of the signal extraction circuit of the second invention has the same configuration as the signal extraction circuit of the second invention, and the sample-and-hold signal is the signal of the second invention. Another signal extraction circuit that operates with a sample and hold signal that is shifted by a half cycle from the sample and hold signal of the extraction circuit is connected in parallel, and the difference between the output signals of both signal extraction circuits is calculated by a differential amplifier and output. And so that arrangement, or the third to the input portion of the signal extraction circuit of the present invention, the third and clock signal the third in the same configuration as the signal extraction circuit of the present invention
Another signal extraction circuit that operates with a clock signal shifted by a half cycle from the clock signal of the signal extraction circuit of the invention of the invention is connected in parallel, and the difference between the output signals of both signal extraction circuits is calculated by a differential amplifier and output. It was configured to do so.

According to a fifth aspect of the present invention, there is provided a signal extracting circuit for directly extracting phase information from an input signal in which binary values of code data are represented by a plurality of cycles of phases, and transferring the phase information obtained by the signal extracting circuit. A signal transfer unit, a multiplication unit having a plurality of multipliers for multiplying a signal obtained from each cell of the signal transfer unit by a predetermined coefficient, and an addition unit for adding a result obtained by each multiplier of the multiplication unit In the correlator, the signal extraction circuit is constituted by the signal extraction circuit according to any one of the first to fourth inventions, and the sample and hold signal is generated based on a signal obtained from the addition unit. Alternatively, the clock signal is generated.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION

[First Embodiment] FIG. 10 is a diagram showing a configuration of a correlator according to a first embodiment of the present invention. The same components as those shown in FIG. 12 are denoted by the same reference numerals. Here, a signal extraction circuit 10 is provided before the signal transfer unit 1, and in this signal extraction circuit 10, PN code data D 2 is extracted from the transmission modulation signal D 3 and sent to the signal transfer unit 1. That is, the signal extraction circuit 10 fetches a timing signal from the timing generator 14 that operates based on the synchronization signal obtained by the synchronization signal generator 5, and converts the phase information of the transmission modulation signal D3 in one chip into one chip. The information signals are combined and output as a signal corresponding to the PN code data D2.

[Second Embodiment] FIG. 1 is an explanatory diagram of a second embodiment showing a specific configuration of the signal extraction circuit 10 described above. 11 is a signal distributor composed of a strip line or the like for distributing the transmission modulation signal D3 to a plurality of paths,
Reference numerals 121 to 124 denote sample / hold circuits which output the input signal D3 as it is while the sample signals SH1 to SH4 are active, and hold and output the signal D3 at the time of transition from active to inactive. This is an adder that adds up the signals D41 to D44 output from the signal 124 and outputs the result as a signal D5. The timing generator 14 generates sample signals SH1 to SH4.

FIG. 2 is a timing chart for explaining the operation of the signal extraction circuit 10 of FIG. Here, in order to simplify the explanation, the transmission modulation signal D3 is set to 5 cycles per chip, and the sample and hold circuits
The number is represented by four. The sample signals SH1 to SH4 are P
The signal has a cycle of one chip of the N-code data D2, becomes active ("1") for one cycle of the transmission modulation signal D3, and is inactive ("0") in other periods. The phases of the sample signals SH1 to SH4 are sequentially shifted by one cycle of the transmission modulation signal D3.

Therefore, the sample and hold circuit 121
The addition signal D5 obtained by adding the output signals D41 to D44 to the output signals D41 to D44 by the adder 13 is the transmission modulation signal D
3 has a positive peak value at a timing corresponding to "1" of the PN code data D2 while having a ripple of 3,
The signal exhibits a negative peak value at the timing corresponding to “0”. Note that the phase is slightly shifted from the PN code data D2. From the above, for example, if a comparator in which the positive threshold value p1 and the negative threshold value p1 ′ are set to values slightly smaller than those peak values is provided at the subsequent stage of the adder 13, the PN
Positive peaks corresponding to "1" and "0" of the code data D2,
A signal with a negative peak can be obtained. It should be noted that a ripple component can be removed by inserting an integrating circuit between the comparator and the adder 13 described above.

In the above description, the case where the transmission modulation signal D3 has 5 cycles per chip of the PN code data D2 has been described for simplicity. Can be. At this time, the positive and negative peak values of the output signal of the adder 13 are n times the positive peak value of the transmission modulation signal D3 and -n times the negative peak value if a margin is provided in the power supply voltage range. In the above description, the sample and hold signals SH1 to SH4 hold the positive or negative peak value of the transmission modulation signal D3. However, any point other than the zero cross point of the transmission modulation signal D3, that is, any positive or negative value It is only necessary to be able to hold the level of The period during which the sample and hold signals SH1 to SH4 are active is not limited to the period of one cycle of the transmission modulation signal D3, but may be a shorter period. By doing so, the ripple component of the addition output signal D5 decreases.

[Third Embodiment] FIG. 3 is a diagram showing a configuration of a signal extraction circuit 10 'according to a third embodiment. This signal extraction circuit adds sample and hold circuits 121 'to 124', an adder 13 'and a differential amplifier 15 to the signal extraction circuit 10 shown in FIG.
Is replaced with a distributor 11 'having an eight distribution function. Here, the sample signals SH1 'to SH4' of the sample and hold circuits 121 'to 124' are controlled by the timing generator 14 'controlled by the synchronization signal generator 5 of FIG.
Is a signal whose phase is delayed from the sample signals SH1 to SH4 by a half cycle of the transmission modulation signal D3.

Therefore, the signals D41 'to D4 obtained by the added sample and hold circuits 121' to 124 '
4 'is a signal whose phase is inverted by 180 degrees with respect to the signals D41 to D44 obtained by the sample and hold circuits 121 to 124. Therefore, the signal D obtained by the adder 13
5 and the signal D5 'obtained by the adder 13' have a phase of 18
The signal is shifted by 0 degrees, and this difference is
, The signals D5 and D5 'are substantially added to the absolute values. Therefore, the signal extraction circuit 10 'of the second embodiment can obtain a signal D6 having a level twice that of the signal D5 obtained by the signal extraction circuit 10 shown in FIG. 2 times better.

[Fourth Embodiment] FIG. 4 is a diagram showing a configuration of a signal extraction circuit 20 according to a fourth embodiment. The signal extraction circuit 20 cascade-connects sample-and-hold circuits 211 to 214 sequentially to the input section of the transmission modulation signal D3, and adds the outputs of the second to fourth-stage sample-and-hold circuits 212 to 214. The output is added in the device 22. 23 is a transmission modulation signal D
A sample signal SH having the same frequency as that of No. 3 and a duty of 50
Which is controlled by the synchronization signal generator 5 shown in FIG. Reference numeral 24 denotes an inverter for generating an inverted sample signal SHN of the sample signal SH.

The odd-numbered sample-and-hold circuits 211,
Reference numeral 213 is active when the sample signal SH is "1" and inactive when it is "0". The even-numbered sample hold circuits 212 and 214 become active when the inverted sample signal SHN is “1”, and become “0”.
It becomes inactive when.

Therefore, the rising edge of the sample signal SH /
If the falling edge is determined as shown in FIG. 5 so that the falling edge corresponds to the positive or negative peak value of the transmission modulation signal D3, the output of the sample-hold circuit 211 at the first stage is the transmission modulation signal D3.
A signal obtained by sampling and holding 3 is output. From the next and subsequent sample hold circuits 212 to 214, rectangular signals whose phases are successively delayed by a half cycle of the sample signal SH are output. Then, these sample and hold circuits 212
D5 obtained by adding the outputs of.
Is a signal corresponding to the PN code data D2.

The number of sample hold circuits is not limited to four. Although the transmission modulation signal D3 has five cycles per chip of the PN code data D2, six or more sample-and-hold circuits can be used. Also, in the above description, the positive and negative peak values of the transmission modulation signal D3 are held by the sample and hold signal SH in the first stage sample and hold circuit 211,
Any positive or negative level other than the zero cross point of the transmission modulation signal D3 may be held.

[Fifth Embodiment] FIG. 6 is a diagram showing a configuration of a signal extraction circuit 20 'according to a fifth embodiment. This signal extraction circuit 20 'is the same as the signal extraction circuit 20 shown in FIG.
, A splitter 25 for splitting the transmission modulation signal D3 into two is provided, and one output of the splitter 25 is connected to the sample and hold circuits 211 to 211.
214 is cascaded, and the other output is input to the cascade-connected sample-hold circuits 211 'to 214'.
To 214 are added by an adder 22 similarly to the signal extraction circuit 20 shown in FIG.
The outputs of 2 ′ to 214 ′ are added by a newly provided adder 22 ′, and the output signals D5, D5 ′ of both adders 22, 22 ′ are added.
Is obtained by the differential amplifier 26.

In the signal extraction circuit 20 ', the sample signal SH is input to the sample hold circuits 211, 213, 212', and 214 ', and the sample hold circuit 212,
214, 211 ', and 213' are inverted sample signals SHN.
Enter.

Therefore, the adder 22 outputs signals from FIGS.
As described above, a signal D5 corresponding to the PN code data D2 is obtained, but a signal D5 'obtained by inverting the signal D5 obtained from the other adder 22 is obtained from the adder 22'. Since the difference between these signals D5 and D5 'is calculated by the differential amplifier 26, their output signals D5 and D5' are substantially added in absolute value. That is,
In the signal extraction circuit 20 'of the fifth embodiment, a signal D6 having a level twice that of the signal obtained by the signal extraction circuit 20 of FIG. 4 can be obtained, and the S / N is improved twice.

[Sixth Embodiment] FIG. 7 is a diagram showing a configuration of a signal extraction circuit 30 according to a sixth embodiment. The signal extraction circuit 30 is obtained by cascade-connecting a switch circuit 31, an integration circuit 32, and a sample-and-hold circuit 33 to an input section of a transmission modulation signal D3. The switch circuit 31 has the same frequency as that of the transmission modulation signal D3 and a duty of 50.
Clock signal CLK, the clock signal CLK
Is "1", the input signal is passed. Integration circuit 32
Is a reset signal R that becomes "1" for only one cycle period of the transmission modulation signal D3 at a period corresponding to the chip rate of the PN code data D2, that is, at the start timing of each chip.
Until reset by ST, the signal from the switch circuit 31 is integrated. The sample hold circuit 33 captures and holds the data immediately before the reset of the integration circuit 32 by a sample hold signal SH similar to the reset signal RST. The clock signal CLK, the reset signal RST, and the sample-and-hold signal SH are generated based on the synchronization signal obtained by the synchronization signal generator 5 in FIG.

As described above, in the signal extraction circuit 30, if the phase is determined so that the rising / falling edge of the clock signal CLK corresponds to the zero cross point of the transmission modulation signal, as shown in FIG. Positive (or negative) of signal D3
The signal D41 of the half cycle is extracted by the switch circuit 31 and integrated by the integration circuit 32. The integration signal D42 immediately before the integration circuit 32 is reset is extracted by the sample and hold circuit 33 and output as a signal D5 to the subsequent stage. Therefore, the signal D5 is a signal of the opposite phase corresponding to "1" or "0" of the PN code data D2.

In the above description, the switch circuit 31 accurately captures the positive or negative half cycle of the transmission modulation signal D3 by the clock signal CLK. The captured half cycle is positive to negative or negative to positive. The signal may change to However, the level at the start of capture and the level at the end of capture must not be the same in positive and negative.

[Seventh Embodiment] FIG. 9 is a diagram showing a configuration of a signal extraction circuit 30 'according to a seventh embodiment. This signal extraction circuit 30 'is similar to the signal extraction circuit 30 shown in FIG.
A switch 34, an integration circuit 32, and a sample-and-hold circuit 33, which are provided with a distributor 34 for distributing the transmission modulation signal D3 into two parts, and having one output of which is configured in the same manner as the circuit shown in FIG. The signal is input to a cascade connection circuit, and the other output is input to a cascade connection circuit including a similar switch circuit 31 ', integration circuit 32', and sample hold circuit 33 ', and the output signal D5 of both sample hold circuits 33, 33' is output. , D5 'are input to the differential amplifier 35. The switch circuit 3
1 'performs a switching operation by using an inverted clock signal CLKN obtained by inverting the clock signal CLK by the inverter 36.

Therefore, in the signal extracting circuit 30 ', the transmission modulation signal D3 is acquired by the switch circuit 31 and the signal D41 acquired by the switch circuit 31'.
The polarity of 41 ′ is reversed, and this is reflected to the integration circuits 32, 3
The polarities of the signals D42 and D42 'integrated at 2' are also reversed. Then, the difference between the output signals D5 and D5 'of the sample and hold circuits 33 and 33' which sample and hold these signals D42 and D42 'is calculated by the differential amplifier 26, so that the output signals D5 and D5 are substantially obtained. 'Will be added to the absolute value. That is, in the signal extraction circuit 30 'of the seventh embodiment, the sixth signal extraction circuit 30'
Can obtain a signal D6 whose level is twice that of the signal obtained by the above, and the S / N is improved twice.

[Other Embodiments] The signal extraction circuit according to each of the above embodiments is applied to a correlator in spread spectrum communication, and converts PN code data D3 from transmission modulation signal D3.
2 is obtained, but the present invention is not limited to this. The signal extraction circuit of the present invention directly extracts phase information from an input signal in which binary values of code data are represented by phases of a plurality of cycles. It is applicable to all of the signal extraction circuits.

[0038]

As described above, according to the present invention, it is not necessary to convert the frequency of an input transmission modulation signal by a down converter or the like, so that the problem of distortion does not occur. Also,
When applied to a correlator that correlates with a spread code in spread spectrum communication, data at a speed corresponding to PN code data can be directly extracted from a signal extraction circuit. It can be operated at the same speed as the chip rate of PN code data,
The number of cells in the signal transfer unit can be made to correspond to the chip length, so that power consumption can be reduced and the circuit can be downsized. Further, when the input transmission modulation signal is converted into a digital signal, the number of bits of the A / D converter is limited at a high frequency, so that the number of bits is low and the dynamic range is small. However, the present invention can directly handle an analog signal. So there is no problem.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a signal extraction circuit according to a second embodiment of the present invention.

FIG. 2 is a waveform diagram of each signal of the circuit of FIG.

FIG. 3 is a block diagram illustrating a configuration of a signal extraction circuit according to a third embodiment of the present invention.

FIG. 4 is a block diagram illustrating a configuration of a signal extraction circuit according to a fourth embodiment of the present invention.

FIG. 5 is a waveform diagram of each signal of the circuit of FIG.

FIG. 6 is a block diagram illustrating a configuration of a signal extraction circuit according to a fifth embodiment of the present invention.

FIG. 7 is a block diagram illustrating a configuration of a signal extraction circuit according to a sixth embodiment of the present invention.

8 is a waveform chart of each signal of the circuit of FIG. 7; You.

FIG. 9 is a block diagram illustrating a configuration of a signal extraction circuit according to a seventh embodiment of the present invention.

FIG. 10 is a block diagram of a correlator according to the first embodiment of this invention.

FIG. 11 is a waveform diagram of a signal on the transmission side of spread spectrum communication.

FIG. 12 is a block diagram of a conventional correlator.

[Explanation of symbols]

1: signal transfer unit, 1a: cell, 2: multiplication unit, 2a: multiplier, 3: addition unit, 4: clock generation unit, 5: synchronization signal generation unit, 10, 10 ': signal extraction circuit, 11: distribution Container, 1
21 to 124, 121 'to 124': sample and hold circuit, 13, 13 ': adder, 14, 14': timing generator, 15: differential amplifier, 20, 20 ': signal extraction circuit, 211 to 214, 211 'to 214': sample and hold circuit, 23: timing generator, 24: inverter, 25: distributor, 26: differential amplifier, 30, 3
0 ': signal extraction circuit, 31, 31': switch circuit, 3
2, 32 ': integration circuit, 33, 33': sample and hold circuit, 34: distributor, 35: differential amplifier, 36: inverter.

Claims (5)

[Claims] 1. A signal extraction circuit for directly extracting phase information from an input signal in which a binary value of code data is represented by a phase of a plurality of cycles, comprising: a plurality of sample and hold circuits for individually sampling and holding the input signal; An adder for adding output signals of the plurality of sample and hold circuits, wherein each of the sample and hold circuits is activated at a timing shifted by one or more units with respect to one cycle of the input signal as a unit. A signal extraction circuit which samples and holds points other than a zero cross point of the input signal, and wherein the adder generates a signal representing the phase by polarity. 2. A signal extraction circuit for directly extracting phase information from an input signal representing a binary value of code data by a plurality of cycles of phase, comprising: a plurality of cascade-connected sample-hold circuits;
An adder for adding outputs from the second stage to the final stage of the plurality of sample and hold circuits, wherein an odd-numbered stage of the plurality of sample and hold circuits is controlled by a sample and hold signal having the same frequency as the input signal. A signal extraction circuit that samples and holds the input signal at a timing excluding a zero cross point and controls an even-numbered stage with a sample and hold signal having a phase opposite to that of the sample and hold signal. 3. A signal extraction circuit for directly extracting phase information from an input signal in which binary of code data is represented by a phase of a plurality of cycles, wherein the input / output circuit is opened and closed by a clock signal having the same frequency as the input signal. A switch circuit that takes in a signal of a half cycle of the integrator, an integrator that integrates a signal passed through the switch circuit and is reset every period corresponding to a bit rate of the code data, and a signal immediately before the reset of the integrator. A signal extraction circuit comprising: a sample and hold circuit for holding. 4. An input section of the signal extraction circuit according to claim 1, which has the same configuration as that of the signal extraction circuit of claim 1, and wherein a sample hold signal is used as a sample hold signal of the signal extraction circuit of claim 1. On the other hand, another signal extraction circuit that operates with a sample and hold signal shifted by a half cycle of the input signal is connected in parallel, and the difference between the output signals of both signal extraction circuits is calculated and output by a differential amplifier, or For the input section of the signal extraction circuit of claim 2,
Another signal extraction circuit having the same configuration as that of the signal extraction circuit of the second aspect and operating with a sample-and-hold signal whose sample-and-hold signal is shifted by a half cycle from the sample-and-hold signal of the signal extraction circuit of the second aspect is connected in parallel. Connected, and the difference between the output signals of the two signal extraction circuits is calculated and output by a differential amplifier.
Another signal extraction circuit having the same configuration as the signal extraction circuit of claim 3 and operating in parallel with a clock signal whose clock signal is shifted by a half cycle from the clock signal of the signal extraction circuit of claim 3 is connected in parallel; A difference between output signals of the two signal extraction circuits is calculated by a differential amplifier and output. 5. A signal extraction circuit for directly extracting phase information from an input signal in which a binary value of code data is represented by a phase of a plurality of cycles, and a signal transfer unit for transferring the phase information obtained by the signal extraction circuit. A multiplication unit having a plurality of multipliers for multiplying a signal obtained from each cell of the signal transfer unit by a predetermined coefficient, and an addition unit for adding a result obtained by each multiplier of the multiplication unit. In the correlator, the signal extraction circuit is constituted by the signal extraction circuit according to any one of claims 1 to 4, and based on a signal obtained from the addition unit, the sample hold signal or the signal A correlator for generating a clock signal.