JPH10107632A - Two-stage analog digital converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the A/D converter that converts an analog input signal into an n-bit digital output code. SOLUTION: A reference voltage generator 540 generates a plurality of reference voltages being equal division voltages of an input voltage range with minimum resolution. A plurality of most significant bits and a plurality of least significant bits are included in n-bits. The most significant bits are produced by encoding a set of digital signals generated by a set of rough comparators 520 that compare analog input signals with rough reference voltages 547. The digital output code of the rough comparators 520 is used to select an accurate reference voltage 549. The least significant bits are produced by encoding a set of digital signals generated by a set of accurate comparators 530 that compare analog input signals with accurate reference voltages 547. The most significant bit of the digital code is corrected and the corrected code is encoded with the least significant bit into a digital output code 575.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

FIELD OF THE INVENTION The present invention relates generally to analog-to-digital (A / D) converters and methods, and more particularly, to use a first stage of conversion to reduce the coarse range of the input voltage. The subsequent stages relate to a multi-stage parallel converter that resolves the analog input signal into finer increments.

[0002]

BACKGROUND OF THE INVENTION Applying digital processing and transmission methods to analog information requires that signals be converted from their analog form to a digital representation. Known types of A /
The D converter uses a digital-to-analog converter to repeat a continuous trial and error approximation to the input to generate a digital output, and a plurality of reference voltages are compared with the input voltage to be closest to the input voltage. A parallel comparator type or flash (FLA) that outputs a digital code representing a reference voltage from the encoding logic circuit in one operation.
SH) converter. FIG. 1 shows a flash type A / D converter. Typically the output is the encoder logic 30
, So that an n-bit resolution of the input signal can be obtained. This structure typically requires 2 ⁿ levels of reference voltage 10 and 2 ⁿ comparators 20. Attempts to improve the resolution of this type of converter (increasing the number of output bits) add to the complexity of the design.

[0003] Two techniques are known for simplifying the design of flash A / D converters. Both of these techniques achieve A / D conversion using a multi-stage conversion. First
No. 5,302,869 (Hosotani et al.)
U.S. Pat.No. 5,389,929 (Nayebi et al.); U.S. Pat.
No. 53,027 (Vorenkamp et al.), U.S. Pat.No. 5,369,309 (B
acrania et al.) and U.S. Pat.No. 5,387,914 (Mangelsdo
rf), the first stage is a coarse-resolution flash A / D converter, and the second stage with a digital-to-analog converter adjusts the reference voltage of the voltage comparator to achieve the final resolution conversion. ing. The results of the two converters are encoded and formed into a digital output word representing the magnitude of the analog input voltage. No. 5,291,198 (Dingwall et al.), US Pat. No. 5,223,836 (Komatsu), US Pat. No. 5,400,029
(Kobayashi), U.S. Patent No. 4,733,217 (Dingwall
), As disclosed in U.S. Pat.No. 5,349,354 (Ho et al.), Where there are multiple conversion stages and the decision logic circuit appropriately adjusts the reference voltage to each stage based on the results of the pre-comparison stage. Switch.

[0004] In the circuit of the multi-stage transform second U.S. Patent No. 4,903,028 shown in Figure 2 as an example of the technique (Fukashima), a value that increases incrementally from _V refbot (minimum value) to _V reftop (maximum value) The range of conversion of the voltage input (V _in ) is determined by providing a set of voltage sources 1 with Voltage input a set of applied in crude Subrange comparator 2, also the set of reference coarse subranges voltage discrete intervals being applied to crude sub-range comparator 2 V _in 1
a and 1b are determined. The output 5 of the coarse sub-range comparator is the input to the steering logic and switch unit 3, which comprises a set of fine sub-range comparators 4.
To the appropriate subrange of the set of reference voltages 1. 1 set of reference voltages 1a is divided in fine increments, the digital output from the _{V in (D0, D1, D2} , ···, Dn)
Determines the maximum resolution for conversion to. If V _in is changed, the output code 5, i.e. the value of the crude sub-range comparator changes, steering logic and the switch unit 3 is seminal Subrange comparator 4 Next subrange (from 1a to 1b)
Move.

[0005] Due to component selection tolerances and process variations, the output code 5 of the coarse subrange comparator 2 can produce errors. To detect this error, V
Gokusei Subrange comparators 4a and 4b are provided on the upper and lower sub-range 1a or 1b which has been determined by _in. The outputs of the extreme comparators 4a and 4b form an error code 7. Seminal Subrange output codes 6,1 set of error codes 7 comparators, and a set of coarse sub range code 5 is interpreted by the output encoding logic circuit 8, the output digital representation of the voltage input V _in (D0,
D1, D2,..., Dn) are determined. In the above description, there are two sets of error detection circuits. Error correction operations during each comparison cycle of the fine subrange comparator are commanded from only one side of the coarse subrange. This type of configuration consumes additional power and adds additional complexity to the physical structure. In order to reduce the number of special comparators and simplify the physical structure, Patent Application Serial No. 081 497 881, assigned to the same assignee as the present application, provides a set of embedded molds as shown in FIG. Coarse subrange comparator 14
Use 0. The reference codes generated by these embedded coarse sub-range comparators determine the appropriate reference voltage range for fine sub-range comparator 160. Code 170 from coarse subrange comparator 120, code 18 from embedded coarse subrange comparator 140
The 0 and the code 190 from the fine subrange comparator 160 are encoded and formed into an output digital code. The reference voltage 131 for selecting the connection position of the embedded coarse sub-range comparator 140 is set by the embedded coarse sub-range selection switch and the logic circuit 130.
It is determined from the output code 170 of the coarse subrange comparator 120. Fine subrange comparator reference voltage 15
The connection position of 1 is determined by the fine subrange selection switch and logic circuit 150 using the input 170 from the coarse subrange comparator and the input 180 from the embedded coarse subrange comparator.

[0006]

SUMMARY OF THE INVENTION It is an object of the present invention to reduce the complexity of the physical structure of a parallel analog-to-digital converter. Another object of the invention is to reduce power consumption by eliminating unnecessary circuitry. FIG. 9 is a timing chart of the present invention. The coarse A / D converter 730 and the fine A / D converter 760 perform the first clock cycle.
The input signal is sampled during half clock cycle 705 of, respectively, to generate input data samples 735 and 765. Second half cycle 7 of first clock cycle
During 10, coarse A / D converter 730 performs a comparison operation 740 of input data samples 735. This comparison operation 7
As a result of 40, the coarse digital code of the input data sample 735 is determined and the required reference voltage for the fine A / D converter 760 is selected. In the second half of the second half cycle 710 of the first clock cycle, a fine A / D converter 760
Compares the input data samples 765 to determine a fine digital code. Thus, “data 1” 805
(The combination of the coarse digital code and the input data samples 735 and 765) can be determined in one clock cycle. Coarse A / D converter 730 and fine A / D
The converter 760 provides a second sample 745, 7 of the input signal during the first half cycle 715 of the second clock cycle.
75, respectively, and a second refinement A
No / D converter is required.

In order to achieve the above-mentioned object, a two-stage A / D converter according to the present invention has a coarse resolution A / D converter and a fine A / D converter. The sample and hold circuit samples the applied analog input voltage at discrete points in time, and
Hold as an input signal source for the converter and the fine A / D converter. A reference voltage generator is connected between the two reference voltage sources and generates a plurality of reference voltages.

[0008] The sampled analog input signal is a coarse A /
It is applied to a D-converter and compared to a coarse set of reference voltages from a reference voltage generator to generate a coarse digital code. The coarse digital code is applied to the reference voltage selection logic. This means comprises a set of a plurality of reference voltages (fine reference voltages)
Is connected to a reference voltage selection switch for selecting The sampled analog input signal is also applied to a fine A / D converter and compared with a fine reference voltage to generate a fine digital code. The coarse digital code and the fine digital code are converted in output encoding means, and the coarse digital code is modified to form an output digital code.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. The analog input voltage (V _in ) 500 is applied to the sample and hold circuit 505. Circuit 505, a V _in 500 periodically samples and holds it as an analog input voltage 510 samples. Reference voltage generator 540 provides a reference voltage source V _RB
541 and V _RT 546. Reference voltage generator 540 generates a plurality of reference voltages 544 that increase incrementally between reference voltage sources V _RB 541 and V _RT 546. The increment of the reference voltage 544 is determined as (V _RT -V _RB ) / 2 ⁿ . Here, n is the number of bits in the digital output code 575. The plurality of reference voltages 544 are
It is connected to a reference voltage switching network consisting of a plurality of switches 543. These plurality of reference voltages 544
, A coarse set of reference voltages 547 is extracted and permanently connected to the coarse set of voltage comparators 520. The sampled analog input voltage 510 is compared to a coarse set of reference voltages 547. The result of this comparison is the coarse thermometer code 527. The thermometer code 527 is a binary code, and each binary digit of the code changes to “1” as the code increases, for example, the lowest value of the 0000 code, 0001 0011 0111 1111 the highest value of the code. It is supposed to.

The coarse thermometer code 527 is used to cause the appropriate switch select line 545 to be selected. Switch select line 545 is connected to a reference voltage switching network comprising a plurality of switches
3 is operated to connect a set of a plurality of reference voltages 544 to supply a fine reference voltage 549. Coarse digital code 5
55 and the fine digital code 565 are output encoder 5
The output encoder 570 converts them to output digital codes 575. This output digital code 575 is a binary number representing the magnitude of the analog input voltage (V _in ) 500. Coarse digital code 555
Is assigned to the most significant bit of a set of binary numbers, and the fine digital code 565 is assigned to the least significant bit of a set of binary numbers. The fine digital code 565 also provides an error correction factor for the most significant bit.

FIG. 5 shows a reference voltage generator (540 in FIG. 4). The reference voltage source V _RB 541 is connected to a resistor 542a, and the reference voltage source V _RT 546 is connected to a resistor 542b. A plurality of resistors 542 are connected in series as a voltage divider, and the voltage generated at each junction of the resistors 542 is one of the reference voltages (544 in FIG. 4). The reference voltage for the coarse comparator (520 in FIG. 4) is taken from the junction of the even column 580 and the odd column 585, and these reference voltages are permanently applied to the coarse comparator 520. Reference voltage 549 to be applied to fine comparator
Are taken from each junction of the individual resistors 542. The selection of these reference voltages 549 is determined by the coarse thermometer code 527, and the selected reference voltage is applied to a fine comparator (530 in FIG. 4) through a reference voltage switching network consisting of a plurality of switches 543.

FIG. 6 shows an example of selecting a junction in the odd-numbered branch 585 of the reference voltage generator 540 of FIG. One set of the fine comparator 539 (530 in FIG. 4) is connected to the fine reference voltage 577 through the reference voltage selection switch 543 in FIG. Sample is V _in 510 was the fine voltage references 577
It is compared with, for generating a thermometer code 537 depends on the magnitude of V _in 510, which is a sample. Precision thermometer code 5
Based on 37, the fine encoder 560 of FIG. 4 forms the fine digital code 590 of FIG. If the even-numbered branch 580 is selected (see FIG. 7), the fine reference voltage 579 is set.
Is applied to the fine comparator 539. As described above, the fine comparator 53 for the fine thermometer code 537
9, these fine voltage references 579 and sampled V _in
Compare with 510. In this case, the thermometer code 53
7, the fine encoder 560 of FIG. 4 forms the fine digital code 595 of FIG.

FIG. 8 shows the fine encoder 560 of FIG. As shown in FIG. 8, fine set of reference voltage 549 is compared to V _in 510, which is sampled at the comparator 535, seminal thermometer code 537 is generated. These thermometer codes are applied to the inputs of NAND gate array 600. One gate in NAND gate array 600 logically combines two adjacent bits of thermometer code 537. The output of NAND gate array 600 is a logic "0" if two adjacent bits of thermometer code 537 are equal, and a logic "1" if they are not equal. The structure of this code is thermometer code 53
Since only one set of two adjacent bits of 7 is not equal, the logic "0" of the thermometer code 537 which makes the output of the NAND gate array 600 a logic "1"
All outputs of the NAND gate array 600 other than the boundary between the logic "1" and the logic "1" become logic "0".

Lines B0, B1, and B2 610 contain the basic ROM code for the output of fine encoder 560 of FIG. The code selection circuit 650 uses the basic ROM
The code is modified to form the modified output digital code 565 of FIG. The code selection circuit 650 uses the line B
0, B1, and B2 610 including a plurality of N-channel metal oxide semiconductor transistors (NMOSTs) configured to change logic values. If the thermometer code 537 has a value that causes the output of NAND gate 605 to be a logical "1", NMOSTs 632,6
36 and 640 are made conductive. If the odd branch 620 is selected as a result of the evaluation of the coarse thermometer code 527 of FIG. 4, the NMOSTs 630 and 634 are turned on, and the fine encoder (560 of FIG.
A value <100> of 90 is output. However, if the evaluation of the coarse thermometer code 527 of FIG. 4 indicates that the even branch 625 is selected, the NMOST 638 is turned on and the fine encoder (560 of FIG. 4) sets the value of the even branch code 595 <011> is output. These codes 590 and 595 are the final fine digital codes 565 of FIG.

Referring to FIG. The clock 700 is shown in FIG.
Of the sample-and-hold circuit 505 of FIG. 4 and the time when the coarse comparator 520 and the fine comparator 530 of FIG. 4 perform the comparison. During the first half cycle 705 of the first clock cycle, input voltage samples 735 and 765 are applied to coarse A / D converter 730 and fine A / D converter 760. Rough A / D converter 7
Thirty comparison operations 740 are performed in the first half of the second half cycle 710 of the first clock cycle. The result of this comparison is used to determine the coarse digital code 555 of FIG. 4 and to set a plurality of switches 543 of FIG. Thus, so fine A / D converter 760 may compare the fine reference voltage 549 V _in 510 and 4, which is a sample. This comparison 770 is performed in the second half of the second half cycle 710 of the first clock cycle, and the result is the fine digital code 565 of FIG. The fine digital code 565 and the coarse digital code 555 of FIG. 4 are combined and corrected (79) in the output coding and error correction logic 570 of FIG. 4 during the first half cycle 715 of the second clock cycle.
0) is output to the output digital code 575 of FIG. This output digital code 575 is the "data 1" 805 after the second half cycle 720 of the second clock cycle.
Will be available as

This process can overlap the coarse A / D converter sampling 745 and the fine A / D converter sampling 775 performed during the first half cycle 715 of the second clock cycle. Performing the coarse comparison 750 and the fine comparison 780 to generate the fine and coarse digital codes 555, 565 of FIG. 4 is performed in the second half cycle 720 of the second clock cycle. The fine and coarse digital codes 555 and 565 of FIG. 4 are 795 during the first half cycle 725 of the third clock cycle.
4 are combined and modified to form the output digital code 575 of FIG. This output digital code "data 2" 810 is available after the next half cycle, the second half cycle of the third clock cycle.

The sampling, comparison, and output correction and encoding are performed in every clock cycle 700 after the first clock cycles 705 and 710.
The output digital codes overlap so that they can be used. Although the present invention has been described with reference to preferred embodiments, it will be understood that those skilled in the art can devise various modifications in shape and detail without departing from the spirit and scope of the invention.

[Brief description of the drawings]

FIG. 1 shows a parallel or flash A / D according to the prior art.
It is a circuit diagram of a converter.

FIG. 2 is a circuit diagram of a conventional two-stage A / D converter.

FIG. 3 shows a conventional embedded subranging A /
It is a circuit diagram of a D converter.

FIG. 4 is a circuit diagram of a two-stage A / D converter according to the present invention.

FIG. 5 is a circuit diagram of a reference voltage generator according to the present invention.

FIG. 6 is a diagram illustrating odd branch selection of the reference voltage network of FIG. 6;

FIG. 7 is a diagram illustrating even branch selection of the reference voltage network of FIG. 6;

FIG. 8 is a circuit diagram of a fine encoder according to the present invention.

FIG. 9 is a timing diagram of a conversion cycle according to the present invention.

[Explanation of symbols]

500 Input analog voltage (V _in ) 505 Sample hold circuit 520 Coarse comparator 530 Fine comparator 540 Reference voltage generator 541, 546 Reference voltage source 542 Resistance 543 Reference voltage selection switch 544 Reference voltage 547 Coarse set reference voltage 549 Fine set Reference voltage 550 Coarse comparator 560 Fine comparator 570 Output coding and error correction logic circuit 575 Output digital code 600 NAND gate array

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Claims (29)

[Claims] 1. A two-stage analog-to-digital converter for converting an analog input signal voltage into an output digital code whose magnitude is represented by x bits: a) converting said analog input signal voltage during a first half clock cycle Input sampling means for obtaining and holding the instantaneous sample; b) comparing the instantaneous sample of the analog input signal voltage with a plurality of coarse reference voltages during the first half of a second half clock cycle period; Coarse comparison means for generating a coarse digital thermometer code representing a coarse estimate of the magnitude of the instantaneous sample of voltage; c) in the second half of said second half clock cycle period, an instantaneous sample of said analog input signal voltage and a plurality of Compare with the subset of the fine reference voltage and display the fine division of the coarse estimation of the magnitude of the instantaneous sample of the analog input signal voltage. Fine comparison means for generating a fine digital thermometer code; d) connected between the first reference voltage source and the second reference voltage source to generate a plurality of coarse reference voltages and a plurality of fine reference voltages. A reference voltage generator; e) a reference voltage selection switch network for selectively connecting an appropriate subset of the plurality of fine reference voltages to the fine comparison means; f) as determined by the coarse digital thermometer code. Reference voltage switch logic means for activating a portion of the reference voltage selection switch network; g) a coarse encoder for converting the coarse digital thermometer code into a most significant portion of the output digital code; A fine encoder for converting the digital thermometer code into the least significant part of the output digital code; and i) adjusting the most significant part of the output digital code to perform the coarse comparison. Output code correcting means for correcting any error generated by the stage and transferring the adjusted output digital code to an external circuit of the two-stage analog-digital converter. vessel. 2. The input sampling means acquires and holds the instantaneous sample at a regular period of a clock pulse, wherein the period of the clock pulse is a first half cycle preceding and a second half cycle following. 2. The analog to digital converter according to claim 1, comprising a cycle. 3. The coarse comparison means comprises a plurality of coarse voltage comparators, each of which comprises a sample input port to which an instantaneous sample of the analog input signal voltage is applied, and a reference to which the coarse reference voltage is applied. A voltage port and a comparison output port, wherein the comparison output port outputs a first logic state when an instantaneous sample of the analog input signal voltage is greater than the coarse reference voltage; 2. The analog-to-digital converter according to claim 1, wherein the second logic state is output if the instantaneous sample of the second reference signal is smaller than the coarse reference voltage. 4. The analog-to-digital converter according to claim 3, wherein said plurality of coarse voltage comparators further comprise 2 ⁿ comparators, ^{where n is the} number of bits of a most significant part of said output digital code. 5. The fine comparison means comprises a plurality of fine voltage comparators, each of the voltage comparators being a sample input port to which an instantaneous sample of the analog input signal voltage is applied, and a reference to which the fine reference voltage is applied. A voltage port, and a comparison output port, wherein the comparison output port outputs a first logic state when an instantaneous sample of the analog input signal voltage is greater than the fine reference voltage; 2. The analog-to-digital converter according to claim 1, wherein the second logic state is output when the instantaneous sample of the second reference signal is smaller than the fine reference voltage. 6. The plurality of fine voltage comparators, wherein n-
^6. A circuit according to claim 5, further comprising 2 ^nx comparators, wherein ^{x is the} number of bits of the least significant part of said output digital code.
2. An analog-to-digital converter according to claim 1. 7. The reference voltage generator comprises a plurality of resistors connected in series to form a voltage divider network between a first reference voltage source and a second reference voltage source. 2. The method of claim 1, wherein one of the plurality of coarse reference voltages and the plurality of fine reference voltages is generated at each junction of the plurality of resistors.
2. An analog-to-digital converter according to claim 1. 8. The resistance of each of the plurality of resistors has an equal magnitude so that the voltage generated at each junction of the plurality of resistors has the same magnitude. Analog-to-digital converter as described. 9. The analog-to-digital converter according to claim 7, wherein the number of resistors in said plurality of resistors is 2 ^× . 10. The analog-to-digital converter of claim 1, wherein the coarse reference voltages are separated by 2 ⁿ increments by the voltage divider network. 11. The analog-to-digital converter according to claim 1, wherein said fine reference voltage is separated by 2 ^nx increments between each said coarse reference voltage. 12. The plurality of resistors are organized in a plurality of resistor columns, the coarse reference voltage is taken from the top and bottom of each column, and the fine voltage is provided in each column of the plurality of resistor columns. 2. The analog according to claim 1, which is distributed over
Digital converter. 13. The analog amplifier according to claim 12, wherein said plurality of resistor columns further comprise a set of even columns and a set of odd columns, wherein said even columns and said odd columns are alternately arranged. Digital converter. 14. The reference voltage selection switch network comprises a plurality of switches, each of said switches being connected to one of said fine reference voltages, wherein said switches are responsive to a determination by said reference voltage selection logic circuit means. 1 of fine reference voltage
2. The analog-to-digital converter according to claim 1, wherein one of the plurality of voltage comparators is selectively applied to one of the plurality of fine voltage comparators. 15. The analog digital thermometer code of claim 1, wherein said coarse digital thermometer code determines a selection of a column among said plurality of columns connected to said fine comparison means by said reference voltage selection switch network. Digital converter 16. The fine digital encoder comprises: a) a plurality of thermometer code inputs to which the fine digital thermometer code is applied; a first logic state and a second logic state of the fine digital thermometer code. B) a thermometer code interpreter having an array of logic determining means for determining the boundary bits between: and an output transmitting said boundary bits; b) storing all possible least significant parts of said output digital code. The analog-to-digital converter of claim 1, comprising a read-only memory, wherein said boundary bits and even or odd selection bits select an appropriate least significant portion of said output digital code. 17. An analog-to-digital converter for converting a sampled analog input signal voltage into an output digital code whose magnitude is represented in x bits in two steps: a) during a first half clock cycle, Input sampling means for obtaining and holding the sampled analog input signal voltage instantaneously from the analog input signal voltage at a period of: b) in the first half of the second half clock cycle, A coarse analog-to-digital converter that compares the signal voltage with a plurality of coarse reference voltages and generates a coarse digital thermometer code representing a coarse estimate of the magnitude of the sampled analog input signal voltage; In the second half of the half clock cycle of the above, the sampled analog input signal voltage is compared with a part of a plurality of fine reference voltages, and A fine analog-to-digital converter that produces a fine digital thermometer code representing the coarse fraction of the coarse estimate of the sampled analog input signal voltage; and d) between a first reference voltage source and a second reference voltage source. A plurality of resistors connected in series so as to form a voltage-dividing network, and a junction between the two resistors connected in series is connected to the plurality of coarse reference voltages and the plurality of fine reference voltages. A reference voltage generator for generating one of the voltages; and e) a plurality of switches, the switches being connected to a junction of two of the plurality of serially connected resistors. A reference voltage selection switch network for selectively connecting one of the plurality of fine reference voltages to the fine analog to digital converter; f) the reference voltage selection switch, as determined by the coarse digital thermometer code. Reference voltage selection switch logic means for activating selected portions of the network; g) a coarse analog-to-digital converter encoder for converting the coarse digital thermometer code into a most significant portion of the output digital code; A) a fine analog-to-digital converter encoder for converting said fine digital thermometer code to the least significant part of said output digital code, said fine analog-to-digital converter encoder receiving said fine digital thermometer code; A plurality of thermometer code inputs, an array of logic determining means for determining a boundary bit between the first logic state and the second logic state of the fine digital thermometer code, and transferring the boundary bit. Thermometer code interpreter array having an interpreter output, and possible output digital code A read-only memory storing all least significant parts of the output digital code, wherein said boundary bits and even or odd select bits select an appropriate least significant part of said output digital code. A converter encoder; i) adjusting the most significant part of the output digital code to correct any errors generated by the coarse analog-to-digital converter;
Output code correcting means for transferring the output code to an external circuit of the step analog-to-digital converter. 18. The input sampling means obtains and holds the instantaneous sample at a regular period of a clock pulse, wherein the clock pulse includes a preceding first half cycle and a succeeding second half cycle. The analog-to-digital converter according to claim 1, comprising: 19. The coarse analog-to-digital converter comprises a plurality of coarse voltage comparators, wherein each of the voltage comparators has a sample input port to which an instantaneous sample of the analog input signal voltage is applied, and a coarse input voltage to which the coarse reference voltage is applied. A reference voltage port, and a comparison output port, wherein the comparison output port outputs a first logic state when an instantaneous sample of the analog input signal voltage is greater than the coarse reference voltage; 18. The analog-to-digital converter according to claim 17, wherein a second logic state is output if the instantaneous sample of the input signal voltage is less than the coarse reference voltage. 20. The plurality of coarse voltage comparators, wherein n
20. The analog-to-digital converter according to claim 19, further comprising 2 ⁿ comparators, ^{where is the} number of bits of the most significant part of the output digital code. 21. The fine analog-to-digital converter comprises a plurality of fine voltage comparators, wherein each of the voltage comparators has a sample input port to which an instantaneous sample of the analog input signal voltage is applied, and a fine reference voltage applied thereto. A reference voltage port, and a comparison output port, wherein the comparison output port outputs a first logic state when an instantaneous sample of the analog input signal voltage is greater than the fine reference voltage; 18. The analog-to-digital converter according to claim 17, wherein a second logic state is output if the instantaneous sample of the input signal voltage is less than the fine reference voltage. 22. The plurality of fine voltage comparators, wherein n
22. The analog-to-digital converter according to claim 21, further comprising ^2nx comparators, where -x is the number of bits of the least significant part of the output digital code. 23. The method according to claim 17, wherein each of the plurality of resistors has an equal resistance value such that voltages generated at respective junctions of the plurality of resistors have the same magnitude. Analog-to-digital converter as described. 24. The analog-to-digital converter according to claim 17, wherein the number of resistors in said plurality of resistors is 2 ^× . 25. The analog-to-digital converter according to claim 17, wherein the coarse reference voltages are separated by 2 ⁿ increments by the voltage divider network. 26. The analog-to-digital converter according to claim 17, wherein the fine reference voltages are spaced by 2 ^nx increments between each of the coarse reference voltages. 27. The plurality of resistors are organized in a plurality of resistor columns, the coarse reference voltage is taken from the top and bottom of each column, and the fine voltage is provided in each column of the plurality of resistor columns. 18. The analog-to-digital converter according to claim 17, which is distributed over 28. The analog circuit according to claim 17, wherein said plurality of resistor columns are composed of one set of even columns and one set of odd columns, and wherein said even columns and said odd columns are alternately arranged.
Digital converter. 29. The analog digital thermometer of claim 17, wherein said coarse digital thermometer code determines a selection of a column in said plurality of columns connected to said fine comparator by said reference voltage selection switch network. Digital converter.