CN115642914B - Pipelined analog-to-digital converter correction circuit, analog-to-digital conversion circuit and method - Google Patents
Pipelined analog-to-digital converter correction circuit, analog-to-digital conversion circuit and method Download PDFInfo
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Abstract
The invention discloses a correction circuit of a pipeline type analog-digital converter, an analog-digital conversion circuit and a method, wherein M trimming register units are arranged, the M trimming register units correspond to quantization results of the pipeline type analog-digital converter in different output sections, and then the characteristic that the pipeline type analog-digital converter generates digital codes according to the quantization results is utilized, so that trimming parameters in a target trimming register unit can be automatically selected from the M trimming register units, and further, an addition circuit is utilized to finish automatic trimming of an analog-digital conversion result directly output by the pipeline type analog-digital converter on the basis. The pipeline analog-to-digital converter correction circuit of the embodiment of the invention adopts a digital circuit trimming mode, realizes automatic trimming, and is simpler compared with the traditional analog circuit trimming mode, thereby effectively reducing the cost.
Description
Technical Field
The present invention relates to the field of analog-to-digital conversion, and in particular, to a correction circuit, an analog-to-digital conversion circuit, and a method for a pipelined analog-to-digital converter.
Background
An analog-to-digital converter (ADC) is a bridge connecting an analog world and a digital world, but due to the requirement of a manufacturing process and a requirement of an enterprise to reduce design cost, the designed ADC inevitably has errors such as gain (gain), offset (offset) and Non-linearity (Non-linearity).
The pipeline analog-to-digital converter, as a common analog-to-digital converter, also faces the problem, and the existing solution mainly solves the problem by modifying the analog circuit, but the modification of the analog circuit requires additional correction analog circuit to be embedded into the original design circuit, and not only the error problem of the design itself but also the error problem newly introduced by the additional circuit need to be considered, and the design method is complex and occupies a large area, which leads to excessive increase of the overall cost, and deviates from the original purpose of reducing the design cost.
Disclosure of Invention
The present invention is directed to solving at least one of the problems of the prior art. Therefore, the invention provides a pipeline analog-to-digital converter correction circuit which can solve the problem of precision trimming on the premise of lower cost.
The invention also discloses an analog-to-digital conversion circuit and an analog-to-digital conversion method.
According to the embodiment of the first aspect of the present invention, the pipelined analog-to-digital converter correction circuit comprises a first bus port for outputting a digital code, a second bus port for outputting an analog-to-digital conversion result, wherein the digital code is used for representing the current segment number of an output segment where the pipelined analog-to-digital converter is located, the number of the output segments is M, the number M of the output segments is determined according to the number of bits of each sub-converter in the pipelined analog-to-digital converter,
the pipelined analog-to-digital converter correction circuit includes:
m trimming register units, wherein each trimming register unit is used for storing preset trimming parameters, and the M trimming parameters correspond to the M output sections one by one;
the selection circuit is provided with a selection input bus port, a trimming parameter output bus port and M trimming parameter input bus ports, wherein the M trimming parameter input bus ports are respectively connected with the M trimming register units, the selection input bus port is connected with the first bus port, and the selection circuit is used for acquiring the trimming parameters in the trimming register units according to digital codes output by the first bus port and outputting the trimming parameters through the trimming parameter output bus port;
the addition circuit is provided with a first addition input bus port, a second addition input bus port and an addition output bus port, the first addition input bus port is connected with the second bus port, the second addition input bus port is connected with the trimming parameter output bus port, and the addition circuit is used for adding an analog-to-digital conversion result output by the second bus port and the trimming parameter output by the trimming parameter output bus port to obtain a correction conversion result and outputting the correction conversion result through the addition output bus port.
The pipeline analog-to-digital converter correction circuit according to the embodiment of the invention has at least the following beneficial effects:
the pipeline analog-digital converter correction circuit provided by the embodiment of the invention is provided with M trimming register units, wherein the M trimming register units correspond to quantization results of the pipeline analog-digital converter in different output sections, and the characteristic that the pipeline analog-digital converter generates digital codes according to the quantization results is utilized, so that trimming parameters in a target trimming register unit can be automatically selected from the M trimming register units, and further, the addition circuit is utilized to automatically trim analog-digital conversion results directly output by the pipeline analog-digital converter on the basis. The pipeline analog-to-digital converter correction circuit adopts a digital circuit trimming mode, and is simpler compared with the traditional analog circuit trimming mode, so that the cost can be effectively reduced. In addition, the pipeline analog-to-digital converter correction circuit of the embodiment of the invention realizes automatic trimming according to a hardware circuit, does not need a controller to participate in control operation, further controls trimming cost and improves trimming efficiency.
According to some embodiments of the invention, the pipelined analog-to-digital converter correction circuit further comprises:
and the result register is connected with the addition output bus port of the addition circuit.
According to some embodiments of the invention, the selection circuit comprises:
a decoding circuit having a decoding information input bus and M decoding output control lines;
the M selective bus switches are arranged in one-to-one correspondence with the M trimming register units, one end of each selective bus switch is connected with the corresponding trimming register unit, the other end of each selective bus switch is connected with the second addition input bus port, each selective bus switch is provided with a controlled end, and the controlled ends of the M selective bus switches are connected with the M decoding output control lines in one-to-one correspondence.
According to some embodiments of the present invention, the adder circuit includes N adders, a number N of the adders being determined according to a number of bits of the pipelined analog-to-digital converter, the N adders corresponding to different bits of the output analog-to-digital conversion result, each of the adders having a first addition input, a second addition input, a carry value output, and an addition output, the N first addition inputs being connected to the second bus port, the N second addition inputs being connected to the trimming parameter output bus port, and the N addition outputs being used together to output a correction conversion result, wherein a carry value input of a highest-order adder in two adders in adjacent orders is connected to a carry value output of a lowest-order adder.
According to some embodiments of the present invention, there are S pipelined adc correction circuits, S pipelined adc correction circuits corresponding to different sub-converters of the pipelined adc, and S pipelined adc correction circuits connected in series.
According to some embodiments of the present invention, the number of bits in the sub-converter in the pipelined analog-to-digital converter is Q, M =2^ Q +1; the trimming parameters stored in the M trimming register units are sorted from small to large, and the trimming parameters stored in the trimming register unit at the middle position are zero.
According to some embodiments of the present invention, the trimming parameter stored in the pth trimming register unit is opposite in polarity to the trimming parameter stored in the M + 1-pth trimming register unit.
An analog-to-digital conversion circuit according to an embodiment of the second aspect of the present invention includes a pipeline analog-to-digital converter and the pipeline analog-to-digital converter correction circuit as described above. Since the analog-to-digital conversion circuit adopts all the technical solutions of the pipeline analog-to-digital converter correction circuit of the above embodiment, at least all the advantages brought by the technical solutions of the above embodiments are achieved.
According to an embodiment of the third aspect of the present invention, the analog-to-digital conversion method includes the steps of:
obtaining analog data to be converted through a pipeline type analog-to-digital converter, and converting to obtain an analog-to-digital conversion result and a digital code; the pipelined analog-to-digital converter is provided with a first bus port for outputting the digital code and a second bus port for outputting the analog-to-digital conversion result, the digital code is used for representing the number of current sections of an output section where the pipelined analog-to-digital converter is located, the number of the output sections is M, and the number M of the output sections is determined according to the number of bits of each sub-converter in the pipelined analog-to-digital converter;
selecting a target trimming register unit from M trimming register units according to the digital code, wherein each trimming register unit is used for storing trimming parameters, and the M trimming parameters correspond to the M output sections one by one;
and utilizing an addition circuit to add the trimming parameters stored in the target trimming register unit and the analog-to-digital conversion result to obtain a correction conversion result.
The analog-to-digital conversion method provided by the embodiment of the invention has at least the following beneficial effects:
the analog-to-digital conversion method of the embodiment of the invention is provided with M trimming register units, wherein the M trimming register units correspond to the quantization results of the pipeline analog-to-digital converter in different output sections, and the characteristic that the pipeline analog-to-digital converter generates digital codes according to the quantization results is utilized, so that trimming parameters in a target trimming register unit can be automatically selected from the M trimming register units, and then the addition circuit is utilized to finish automatic trimming of the analog-to-digital conversion result directly output by the pipeline analog-to-digital converter. The analog-to-digital conversion method of the embodiment of the invention realizes trimming based on the digital circuit, and is simpler compared with the traditional analog circuit trimming mode, thereby effectively reducing the cost.
According to some embodiments of the invention, further comprising the steps of:
and outputting the correction conversion result to a result register.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
fig. 1 is a schematic structural diagram of a correction circuit of a pipelined analog-to-digital converter according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a correction circuit of a pipelined ADC according to another embodiment of the present invention;
FIG. 3 is a schematic diagram illustrating a calibration effect of a calibration circuit of a pipelined analog-to-digital converter according to an embodiment of the present invention;
fig. 4 is a flowchart of an analog-to-digital conversion method according to an embodiment of the invention.
Reference numerals:
a pipelined analog-to-digital converter 100,
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.
In the description of the present invention, if there are first, second, etc. described, it is only for the purpose of distinguishing technical features, and it is not understood that relative importance is indicated or implied or that the number of indicated technical features is implicitly indicated or that the precedence of the indicated technical features is implicitly indicated.
In the description of the present invention, it should be understood that the orientation or positional relationship referred to, for example, the upper, lower, etc., is indicated based on the orientation or positional relationship shown in the drawings, and is only for convenience of description and simplification of description, but does not indicate or imply that the device or element referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and thus should not be construed as limiting the present invention.
In the description of the present invention, it should be noted that unless otherwise explicitly defined, terms such as arrangement, installation, connection and the like should be broadly understood, and those skilled in the art can reasonably determine the specific meanings of the above terms in the present invention in combination with the specific contents of the technical solutions.
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the embodiments described below are some, but not all embodiments of the present invention.
For better describing the pipelined analog-to-digital converter correction circuit of the embodiment of the present invention, a brief description is given of the relevant characteristics of the pipelined analog-to-digital converter 100. The pipelined adc 100 includes a plurality of sub-converters connected in sequence, and an output of a sub-converter at a previous stage is used as an input of a sub-converter at a next stage, for example, for an 8-bit pipelined adc 100, it can be regarded as a two-stage 4-bit sub-converter. When the pipelined analog-to-digital converter 100 completes the conversion of the input analog data, digital codes are synchronously output in addition to the analog-to-digital conversion result, and the digital codes are obtained according to the quantization result of the pipelined analog-to-digital converter 100, specifically, for the 8-bit pipelined analog-to-digital converter 100, the quantization result is in any one of 17 output segments, and the digital codes also have the possibility of outputting 0 to 16, which are seventeen output possibilities. Therefore, the digital code output by the pipelined analog-to-digital converter 100 can be used to determine the output segment where the quantization result of the pipelined analog-to-digital converter 100 is located, thereby realizing accurate trimming when the quantization result is located in each segment.
Based on the pipelined analog-to-digital converter 100, various embodiments of the pipelined analog-to-digital converter correction circuit according to the embodiments of the present invention are provided. The embodiments of the present invention will be further explained with reference to the drawings.
As shown in fig. 1, fig. 1 is a schematic structural diagram of a correction circuit of a pipelined analog-to-digital converter according to an embodiment of the present invention, where the pipelined analog-to-digital converter 100 has a first bus port for outputting a digital code, and a second bus port for outputting an analog-to-digital conversion result, the digital code is used to characterize the number of current segments of an output segment where the pipelined analog-to-digital converter 100 is located, the number of output segments is M, and the number M of output segments is determined according to the number of bits of each sub-converter in the pipelined analog-to-digital converter 100;
the pipelined analog-to-digital converter correction circuit comprises M trimming register units 210, a selection circuit 220 and an addition circuit 230;
the trimming register units 210 are arranged in a row, and each trimming register unit 210 is used for storing preset trimming parameters which correspond to the output sections one by one;
a selection circuit 220 having a selection input bus port, a trimming parameter output bus port, and M trimming parameter input bus ports, where the M trimming parameter input bus ports are respectively connected to the M trimming register units 210, the selection input bus port is connected to the first bus port, and the selection circuit 220 is configured to obtain the trimming parameters in the trimming register unit 210 according to the digital codes output by the first bus port, and output the trimming parameters through the trimming parameter output bus port;
and an adding circuit 230 having a first adding input bus port, a second adding input bus port and an adding output bus port, the first adding input bus port being connected to the second bus port, the second adding input bus port being connected to the trimming parameter output bus port, the adding circuit 230 being configured to add the analog-to-digital conversion result output by the second bus port and the trimming parameter output by the trimming parameter output bus port to obtain a correction conversion result, and output the correction conversion result through the adding output bus port.
The analog-to-digital conversion result and the digital code output by the pipelined analog-to-digital converter 100 can be output through different bus ports, that is, if the pipelined analog-to-digital converter 100 is an 8-bit pipelined analog-to-digital converter 100, eight lines are output synchronously when outputting the conversion result, and similarly, when the pipelined analog-to-digital converter 100 is composed of two-stage 4-bit sub-converters, the digital code output includes four lines with valid bits and one line with a sign bit, and 5 lines are included in total, and the digital code is 5 bits; at this time, the output segment of pipelined ADC 100 is 2^4+1, and there are 17 output segments in total.
The selection circuit 220 has one trimming parameter output bus port and M trimming parameter input bus ports, and the M trimming parameter input bus ports are respectively connected to the M trimming register units 210, so that the selection circuit 220 can select any one of the trimming parameters stored in the M trimming register units 210 to be output through the trimming parameter output bus port every time, and the specific selection is completed according to the numerical value code input by the selected input bus port. Therefore, after the first bus port of the pipelined adc 100 outputs the digital code to the selective input bus port of the selection circuit 220, the selection circuit 220 selects the corresponding trimming register unit 210 according to the decoding result of the digital code to read the trimming parameter and output the trimming parameter. For example, when the output section of the pipelined adc 100 is 17 output sections, there are 17 trimming parameter input bus ports connected to the 17 trimming register units 210, and the selection circuit 220 selects the trimming parameter output in the trimming register unit 210 according to the value (0 to 16) corresponding to the digital code.
The trimming parameters outputted from the selection circuit 220 will reach the adder circuit 230 through the trimming parameter output bus port, and will be added with the analog-to-digital conversion result outputted from the pipelined analog-to-digital converter 100, thereby completing the correction of the analog-to-digital conversion result. It should be noted that the number of bits of the trimming parameter is the same as the number of bits of the analog-to-digital conversion result, and the bus is used to complete the simultaneous output of each bit of data, so that the addition circuit 230 can be used to quickly complete the addition operation of the trimming parameter and the analog-to-digital conversion result, and obtain the corrected conversion result after trimming. It should be further noted that, when the analog-to-digital conversion result is in different output segments after quantization, the modification parameter corresponding to the output segment is used for modification, that is, the hardware circuit is used to implement the segmented correction of the analog-to-digital conversion result.
The pipeline analog-to-digital converter correction circuit of the embodiment of the invention is provided with M trimming register units 210, wherein the M trimming register units 210 correspond to quantization results of the pipeline analog-to-digital converter 100 in different output sections, and the characteristic that the pipeline analog-to-digital converter 100 generates digital codes according to the quantization results is utilized, so that trimming parameters in a target trimming register unit can be automatically selected from the M trimming register units 210, and further, the automatic trimming of an analog-to-digital conversion result directly output by the pipeline analog-to-digital converter 100 is completed by utilizing the addition circuit 230 on the basis. The pipeline analog-to-digital converter correction circuit adopts a digital circuit trimming mode, and is simpler compared with the traditional analog circuit trimming mode, so that the cost can be effectively reduced. In addition, the pipeline analog-to-digital converter correction circuit of the embodiment of the invention realizes automatic trimming according to a hardware circuit, does not need a controller to participate in control operation, further controls trimming cost and improves trimming efficiency.
In some embodiments, as shown in fig. 1 and 2, the pipelined adc correction circuit further includes a result register 240, and the result register 240 is connected to the summing output bus port of the summing circuit 230. The result register 240 may implement buffering of the correction conversion result, which is convenient for subsequent devices to read.
In some embodiments, the selection circuit 220 includes: a decoding circuit 221 and M select bus switches 222,
a decoding circuit 221 having a decoding information input bus and M decoding output control lines;
the M selection bus switches 222 are arranged in a one-to-one correspondence with the M trimming register units 210, one end of each selection bus switch 222 is connected with the corresponding trimming register unit 210, the other end of each selection bus switch 222 is connected with the second addition input bus port, each selection bus switch 222 is provided with a controlled end, and the controlled ends of the M selection bus switches 222 are connected with the M decoding output control lines in a one-to-one correspondence manner.
Referring to fig. 2,M selection bus switches 222 are respectively connected between the adder circuit 230 and the M trimming register units 210, and therefore, the trimming parameters in the corresponding trimming register unit 210 can be read to the adder circuit 230 by closing any one of the selection bus switches 222. The decoding circuit 221 can decode the digital code, so as to output a decoding control signal corresponding to the digital code through M decoding output control lines, and control the closing of a corresponding one of the M selection bus switches 222 by using the decoding control signal, so as to transmit the trimming parameter in the trimming register unit 210 corresponding to the selection bus switch 222 to the adding circuit 230.
As shown in fig. 2, in some embodiments, the adder circuit 230 includes N adders 231, a number N of the adders 231 is determined according to a number of bits of the pipelined analog-to-digital converter 100, the N adders 231 correspond to different bits of the output analog-to-digital conversion result, each of the adders 231 has a first addition input, a second addition input, a carry value output, and an addition output, the N first addition inputs are connected to the second bus port, the N second addition inputs are connected to the trimming parameter output bus port, and the N addition outputs are used together for outputting the corrected conversion result, wherein the carry value input of the adder 231 with the highest bit in two adders 231 of adjacent bits is connected to the carry value output of the adder 231 with the lowest bit.
The N adders 231 may perform addition of the analog-to-digital conversion result and the trimming parameter of the pipelined analog-to-digital converter 100. The number of adders 231 needs to be the same as the number of bits of the analog-to-digital conversion result (for example, 8 adders 231 need to be selected for an 8-bit ADC), each adder 231 completes the calculation of one bit of the analog-to-digital conversion result and the trimming parameter, and the lower data after completing the addition operation transfers the carry result to the higher adder 231, so that the higher adder 231 completes the addition operation, and by using the way of adding step by step, the addition of the logarithmic conversion result and the trimming parameter can be completed by using a hardware circuit, and a correction conversion result that is the same as the number of bits of the analog-to-digital conversion result is output.
In some embodiments, there are S pipelined adc correction circuits, where the S pipelined adc correction circuits correspond to different sub-converters in pipelined adc 100, and the S pipelined adc correction circuits are connected in series.
In practical use, since the pipelined adc 100 includes a plurality of sub-converters, each sub-converter has a possibility of error occurrence, and therefore, when two or more sub-converters have errors, a pipelined adc correction circuit needs to be provided for each sub-converter, that is, each pipelined adc correction circuit only completes the correction for one sub-converter, and when there are a plurality of sub-converters needing to be corrected, the pipelined adc correction circuits need to be used to complete the correction one by one. Specifically, for the 8-bit ADC pipelined ADC analog-to-digital converter 100 with two stages and four bits, if both the first-stage sub-converter and the second-stage sub-converter have errors, a pipelined analog-to-digital converter correction circuit is respectively disposed for the two sub-converters, and is sequentially connected in series to the output end of the pipelined analog-to-digital converter 100, so that the pipelined analog-to-digital converter correction circuit corresponding to the first-stage sub-converter can be used to complete the correction of the error introduced to the first-stage sub-converter in the analog-to-digital conversion result, and the corrected conversion result is further input to the pipelined analog-to-digital converter correction circuit corresponding to the second-stage sub-converter to complete the correction of the error introduced to the second-stage sub-converter, so as to obtain the final corrected conversion result.
In some embodiments, the number of bits in sub-converters in pipelined analog-to-digital converter 100 is Q, M =2^ Q +1; the trimming parameters stored in the M trimming register units 210 are sorted from small to large, and the trimming parameter stored in the trimming register unit 210 located at the middle position is zero. If the trimming parameter in the trimming register unit 210 at the middle position is zero, the polarity of the first half section and the polarity of the second half section in the pipelined adc 100 will be opposite, so that the front and rear half sections can be better adjusted.
In some embodiments, the trim parameters stored in the pth trim register unit 210 are opposite in polarity to the trim parameters stored in the M + 1-pth trim register unit 210. In general, the deviations of the pipeline adc 100 at each output stage are symmetrical about the middle output terminal, and therefore, the trimming parameters stored in the pth trimming register unit 210 and the trimming parameters stored in the M + 1-pth trimming register units 210 may be set with polarities opposite to each other and keep the magnitudes close to each other. Specifically, assuming that the jump value of each segment is equal, with respect to the 9 th segment at the middle position, the 1 st segment needs to be shifted up (or down) by an offset value of 8x, the 2 nd segment needs to be shifted up (or down) by an offset value of 7x, …, and the 8 th segment needs to be shifted up (or down) by an offset value of 1 x; segment 10 requires a 1x offset down (or up) shift, segment 11 requires a 2x offset down (or up) shift, …, and segment 17 requires an 8x offset down (or up) shift; therefore, compared with the reference of the 1 st segment or the 17 th segment (the offset value which needs to be shifted by 16x at most), the trimming range of the trimming parameter can be halved based on the bit of the 9 th segment (the middle segment), and the bit number of the trimming register unit 210 can be reduced, thereby saving the hardware resource.
In order to better describe the pipeline analog-to-digital converter correction circuit of the embodiment of the present invention, a specific embodiment is further described herein.
Referring to fig. 2, in the embodiment, the pipelined adc 100 employs an 8-bit adc, which is divided into two stages of sub-converters, each stage is 4 bits, and only the first stage of sub-converter needs to be modified. Thus, in this embodiment, the digital code is 5 bits and the output segment has 17 terminals.
The pipelined adc 100 has a first bus port for outputting the 5-bit digital code to the decoding circuit 221 in parallel and a second bus port for outputting the 8-bit adc results of the pipelined adc 100 to the first summing input a of the 8 adders 231, respectively.
The decoding circuit 221 has 17 decoding output control lines CT0 to CT16, which correspond to 17 output segments of the pipelined analog-to-digital converter 100, and the 17 decoding output control lines respectively control the on-off of 17 selection bus switches 222; one end of each selection bus switch 222 is connected to one trimming register unit 210, and the other end is output to the second addition input B of the 8 adders 231 in a bus manner. The decoding circuit 221 may perform control of the 17 decoding output control lines according to the decoding result of the digital code so that one of the 17 selection bus switches 222 corresponding to the decoding result is turned on.
The 8 adders 231 adopt a bit-by-bit addition mode, the carry value input end CI at the lowest bit is directly grounded, the addition output end SUM outputs the result of adding the analog-to-digital conversion result of the current bit and the trimming parameters, the carry value output end CO outputs the carry result to the carry value input end CI at the last bit, according to the mode, the addition operation of the analog-to-digital conversion results and the trimming parameters of all the bits can be finally completed, and the 8 adders 231 output the 8-bit correction conversion results in parallel to the result register 240 for the subsequent modules to read. It should be noted that the carry value output terminal CO of the most significant adder 231 outputs the carry result to the arbitration circuit. It should be noted that the arbitration circuit is mainly used to prevent the output of an erroneous result when the result after the addition operation exceeds the maximum and minimum ranges, and when the operation result exceeds the maximum and minimum ranges, the addition circuit is forced to output the maximum range (i.e., all 1) and the minimum range (i.e., all 0).
The operation principle of the correction circuit of the pipelined analog-to-digital converter of the above embodiment is described with a specific acquisition process modification procedure. Assuming that the voltage range of the pipelined analog-to-digital converter 100 is 0 to 3.3V, and the voltage value of the current sampling is 0.825V, the 0.825V is in a fifth output segment of 0 to 3.3V.
After the pipelined analog-to-digital converter 100 collects the voltage of 0.825V, the voltage of 0.825V is converted into an 8-bit analog-to-digital conversion result, and a digital code corresponding to the fifth segment is output. It should be noted that when the analog-to-digital conversion result of the ADC is detected to be in the 1 st segment, the 5-bit digital code output is 00000, and when the ADC is detected to be in the 2 nd segment, the 5-bit digital code output is 00001, …, and when the ADC is detected to be in the 17 th segment, the 5-bit digital code output is 10000; therefore, in this embodiment, the digital code output is 00100.
After the decoding circuit 221 receives the digital code 00100, the fifth one of the sequentially sequenced 17 decoding output control lines is processed to a high level, so that the selection bus switch 222 corresponding to the digital code 00100 is turned on, and the trimming parameters in the trimming register unit 210 corresponding to the fifth trimming segment are output to the second addition input B of the 8 adders 231 through the selection bus switch 222. Meanwhile, since the analog-to-digital conversion result is input to the first addition input end a of the 8 adders 231, the 8 adders 231 can complete the addition operation of the 8-bit analog-to-digital conversion result and the 8-bit trimming parameter, and a final correction output result is obtained.
In the pipeline adc correction circuit according to this embodiment, the plurality of trimming register units 210 are arranged, the plurality of trimming register units 210 correspond to quantization results of the pipeline adc 100 in different output stages, and then the characteristic that the pipeline adc 100 generates a digital code according to the quantization result is utilized, so that the trimming parameters in the target trimming register unit can be automatically selected from the plurality of trimming register units 210, and then the adder 231 is utilized to complete automatic trimming of the adc result directly output by the pipeline adc 100. The pipeline analog-to-digital converter correction circuit adopts a digital circuit trimming mode, and is simpler compared with the traditional analog circuit trimming mode, so that the cost can be effectively reduced. In addition, the pipeline analog-to-digital converter correction circuit of the embodiment of the invention realizes automatic trimming according to a hardware circuit, does not need a controller to participate in control operation, further controls trimming cost and improves trimming efficiency.
In some embodiments, the trimming parameters of the embodiments of the present invention are obtained by theoretically correcting the actual sampling results of each output section of the pipelined adc 100. Because the trimming parameters are preset values, the invention does not specifically limit how the trimming parameters are obtained.
In some embodiments, the trimming parameters are determined by:
correcting the gain (k) and the offset (b) of the pipelined analog-to-digital converter 100, and correcting the fitting straight line of the pipelined analog-to-digital converter 100 into an ideal straight line;
determining ideal positions of a plurality of trip points of the pipelined analog-to-digital converter 100;
determining a test interval according to the ideal position of each jumping point, and determining the actual position of each jumping point and a corresponding jumping value based on the test interval;
and finishing the division of the output end of the quantization result of the streamline analog-to-digital converter 100 according to the actual positions and the jump values of the plurality of jump points, and finishing the setting of the trimming parameters corresponding to each output section.
In order to better explain the trimming parameter determining method of the present embodiment, the method takes 16 trip points and 17 output ends as examples, and further describes the following specific steps:
step 1: the correction of the gain (k) and the offset (b) of the whole pipeline analog-to-digital converter 100 is performed first, so that the linear fitting straight line k =1 and b =0 of the pipeline analog-to-digital converter 100 can be understood as the correction of the fitting straight line of the pipeline analog-to-digital converter 100 to be an ideal straight line.
Step 2: the ideal positions (W) of the 16 transition points of pipelined ADC 100 are determined according to the structural characteristics of pipelined ADC 100 m ) Input full amplitude (V) to pipelined analog-to-digital converter 100 FS ) The relationship is as follows:
wherein m is equal to or greater than 1 and equal to or less than 16, and m is an integer, such as the 1 st ideal position of the trip point (W) 1 ) V is 1/32 FS At the 2 nd ideal position of the trip point (W) 2 ) V is 3/32 FS …, 16 th trip point ideal position (W) 16 ) V is 31/32 FS To (3).
And step 3: based on the processing in step 1, the error between the actual position and the ideal position of the 16 trip points of the pipelined adc 100 is not very large, so that only the test interval (y) corresponding to the mth trip point is needed m ) Setting the position of the ideal jump point within a certain range, and then according to the actual ADC precision (n bits) and jump values (x) corresponding to 16 jump points m ) Determining 16 test intervals corresponding to the 16 jump points and the step value (V) of the test input voltage STEP ). The specific constraint formula is as follows:
and 4, step 4: since the calculation formula in step 3 utilizes x m But x m And is the value to be tested, so a smaller initial x can be set according to experience m Values, then an iterative operation is performed, namely: the initial x is set m After the value is reached, a jump point is searched in the test interval based on the step value, and if the jump point is not found in the test interval, the initial x is set m And (5) repeating the iteration operation after multiplying the value by 2, and if a jump point is found in the test interval, entering the step 5 and ending the iteration operation.
And 5: after step 4 is completed, the actual positions of 16 transition points of the pipelined adc 100 and the transition value corresponding to each transition point can be found through testing, and this step is based on the conclusion of step 4, taking the output of the pipelined adc 100 in the 9 th stage as the reference (i.e. setting the modification parameter in the ninth stage to 0), and making the slope of the output of each stage of the actual pipelined adc 100 smaller than 1 (as shown in fig. 3), then the modification parameter x stored in the modification register unit 210 corresponding to the eighth stage is stored in the modification register unit 210 corresponding to the eighth stage 8 Converting into corresponding binary original codes; the trimming parameter x stored in the trimming register unit 210 corresponding to the seventh segment 7 +x 8 Converting into corresponding binary original codes; …; the trimming parameter x stored in the trimming register unit 210 corresponding to the first segment 1 + x 2 +…+ x 8 Converting into corresponding binary original codes; the back 8-segment trimming parameters with opposite polarity to the front 8-segment trimming parameters are respectively: trimming parameter x stored in trimming register unit 210 corresponding to the tenth section 10 Converting into corresponding binary complement codes; trimming parameter x stored in trimming register unit 210 corresponding to the eleventh section 10 +x 11 Converting into complement codes after corresponding binary system; …; the trimming parameter x stored in the trimming register unit 210 corresponding to the sixteenth segment 10 + x 11 +…+ x 16 Converted to the complement of the corresponding binary. It should be noted that, since the adding circuit 230 is composed of a plurality of adders 231, it is necessary to implement an adding logic operation using an original code and a subtracting logic operation using a complement code. In addition, it should be noted that, if the slope of each segment output of the actual pipeline adc 100 is greater than 1, the first 8 segments of the trimming parameters are the skip values and are converted into the complement codes after the corresponding binary system, and the last 8 segments of the trimming parameters are the skip values and are converted into the original codes after the corresponding binary system.
In the method for determining the trimming parameters in this embodiment, the test interval of the whole pipelined analog-to-digital converter 100 is not required, and only the test interval near the ideal trip point is required, so that the time and the calculation force for determining the actual trip point can be greatly reduced.
The embodiment of the present invention further provides an analog-to-digital conversion circuit, which includes the pipeline analog-to-digital converter correction circuit. Since the analog-to-digital conversion circuit adopts all the technical solutions of the pipeline analog-to-digital converter correction circuit of the above embodiment, at least all the advantages brought by the technical solutions of the above embodiments are achieved.
Referring to fig. 4, fig. 4 is a flowchart of an analog-to-digital conversion method according to an embodiment of the present invention, where the analog-to-digital conversion method includes the following steps:
the analog-to-digital conversion method comprises the following steps:
obtaining analog data to be converted through the pipelined analog-to-digital converter 100, and converting to obtain an analog-to-digital conversion result and a digital code; the pipelined analog-to-digital converter 100 has a first bus port for outputting digital codes and a second bus port for outputting analog-to-digital conversion results, the digital codes are used for representing the number of current segments of output segments where the pipelined analog-to-digital converter 100 is located, the number of the output segments is M, and the number M of the output segments is determined according to the number of bits of each sub-converter in the pipelined analog-to-digital converter 100;
selecting a target trimming register unit from the M trimming register units 210 according to the digital code, wherein each trimming register unit 210 is used for storing trimming parameters, and the M trimming parameters are in one-to-one correspondence with the M output sections;
the addition circuit 230 is used to add the trimming parameters stored in the target trimming register unit and the analog-to-digital conversion result to obtain the correction conversion result.
Referring to fig. 1 and 2, the analog-to-digital conversion result and the digital code output by the pipelined analog-to-digital converter 100 are output through different bus ports, that is, if the 8-bit ADC is implemented, eight lines are output synchronously when outputting the conversion result, and similarly, when the 8-bit ADC is implemented by two stages of sub-converters, the digital code output includes four lines with valid bits and one line with a sign bit, and 5 lines are provided in total, and the digital code is 5 bits; at this time, the output segment of pipelined ADC 100 is 2^4+1, and there are 17 output segments in total.
The selection circuit 220 has one trimming parameter output bus port and M trimming parameter input bus ports, and the M trimming parameter input bus ports are respectively connected to the M trimming register units 210, so that the selection circuit 220 can select any one of the trimming parameters stored in the M trimming register units 210 to be output through the trimming parameter output bus port every time, and the specific selection is completed according to the data input by the selected input bus port. Therefore, after the first bus port of the pipelined adc 100 outputs the digital code to the selective input bus port of the selection circuit 220, the selection circuit 220 selects the corresponding trimming register unit 210 according to the decoding result of the digital code to read the trimming parameter and output the trimming parameter. For example, when the output section of the pipelined adc 100 is 17 output sections, there are 17 trimming parameter input bus ports connected to the 17 trimming register units 210, and the selection circuit 220 selects the trimming parameter output in the trimming register unit 210 according to the value (0 to 16) corresponding to the digital code.
The trimming parameters outputted from the selection circuit 220 will reach the adder circuit 230 through the trimming parameter output bus port, and will be added with the analog-to-digital conversion result outputted from the pipelined analog-to-digital converter 100, thereby completing the correction of the analog-to-digital conversion result. It should be noted that the number of bits of the trimming parameter is the same as the number of bits of the analog-to-digital conversion result, and the bus is used to complete the simultaneous output of each bit of data, so that the addition circuit 230 can be used to quickly complete the addition operation of the trimming parameter and the analog-to-digital conversion result, and obtain the corrected conversion result after trimming. It should be further noted that, when the analog-to-digital conversion result is in different output segments after quantization, the modification parameter corresponding to the output segment is used for modification, that is, the hardware circuit is used to implement the segmented correction of the analog-to-digital conversion result.
The analog-to-digital conversion method of the embodiment of the present invention sets M trimming register units 210, where the M trimming register units 210 correspond to the quantization results of the pipeline analog-to-digital converter 100 in different output sections, and then utilizes the characteristic that the pipeline analog-to-digital converter 100 generates digital codes according to the quantization results, so as to automatically select trimming parameters in the target trimming register unit from the M trimming register units 210, and further utilize the adding circuit 230 to complete automatic trimming of the analog-to-digital conversion result directly output by the pipeline analog-to-digital converter 100 on this basis. The analog-to-digital conversion method of the embodiment of the invention realizes trimming based on the digital circuit, and is simpler compared with the traditional analog circuit trimming mode, thereby effectively reducing the cost.
In some embodiments, the analog-to-digital conversion method further comprises the steps of:
the corrected conversion result is output to the result register 240.
The result register 240 is connected to the addition output bus port of the addition circuit 230. The result register 240 may implement buffering of the correction conversion result, which is convenient for subsequent devices to read.
The embodiments of the present invention have been described in detail with reference to the drawings, but the present invention is not limited to the embodiments, and various changes can be made within the knowledge of those skilled in the art without departing from the gist of the present invention.
Claims (10)
1. A pipelined analog-to-digital converter correction circuit is characterized in that the pipelined analog-to-digital converter is provided with a first bus port for outputting digital codes and a second bus port for outputting analog-to-digital conversion results, the digital codes are used for representing the current segment number of an output segment where the pipelined analog-to-digital converter is located, the number of the output segments is M, the number M of the output segments is determined according to the bit number of each sub-converter in the pipelined analog-to-digital converter, the bit number of the sub-converter in the pipelined analog-to-digital converter is Q, and M =2^ Q +1;
the pipelined analog-to-digital converter correction circuit includes:
m trimming register units, wherein each trimming register unit is used for storing preset trimming parameters, and the M trimming parameters correspond to the M output sections one by one;
the selection circuit is provided with a selection input bus port, a trimming parameter output bus port and M trimming parameter input bus ports, wherein the M trimming parameter input bus ports are respectively connected with the M trimming register units, the selection input bus port is connected with the first bus port, and the selection circuit is used for acquiring the trimming parameters in the trimming register units according to digital codes output by the first bus port and outputting the trimming parameters through the trimming parameter output bus port;
the addition circuit is provided with a first addition input bus port, a second addition input bus port and an addition output bus port, the first addition input bus port is connected with the second bus port, the second addition input bus port is connected with the trimming parameter output bus port, and the addition circuit is used for adding an analog-to-digital conversion result output by the second bus port and the trimming parameter output by the trimming parameter output bus port to obtain a correction conversion result and outputting the correction conversion result through the addition output bus port.
2. The pipelined analog-to-digital converter correction circuit of claim 1, further comprising:
and the result register is connected with the addition output bus port of the addition circuit.
3. The pipelined analog-to-digital converter correction circuit of claim 1, wherein the selection circuit comprises:
a decoding circuit having a decoding information input bus and M decoding output control lines;
the M selective bus switches are arranged in one-to-one correspondence with the M trimming register units, one end of each selective bus switch is connected with the corresponding trimming register unit, the other end of each selective bus switch is connected with the second addition input bus port, each selective bus switch is provided with a controlled end, and the controlled ends of the M selective bus switches are connected with the M decoding output control lines in one-to-one correspondence.
4. The pipelined adc-correcting circuit of claim 1, wherein the adder circuit comprises N adders, the number N of the adders being determined according to the number of bits of the pipelined adc, the N adders corresponding to different bits of the output adc result, each of the adders having a first add input, a second add input, a carry value output, and an add output, the N first add inputs being connected to the second bus port, the N second add inputs being connected to the trim parameter output bus port, the N add outputs being used together to output a corrected conversion result, wherein the carry value inputs of two adders with a highest order in adjacent orders are connected to the carry value outputs of adders with a lowest order.
5. The pipelined analog-to-digital converter correction circuit of claim 1, wherein there are S pipelined analog-to-digital converter correction circuits, S of the pipelined analog-to-digital converter correction circuits corresponding to different sub-converters in the pipelined analog-to-digital converter, S of the pipelined analog-to-digital converter correction circuits being connected in series.
6. The pipelined adc correction circuit of claim 1, wherein the trim parameters stored in M of the trim register units are ordered from small to large, and the trim parameter stored in the trim register unit in the middle position is zero.
7. The pipelined adc correcting circuit of claim 6, wherein the trim parameters stored in the pth trim register unit are opposite in polarity to the trim parameters stored in the M + 1-pth trim register unit.
8. An analog-to-digital conversion circuit comprising a pipelined analog-to-digital converter and the pipelined analog-to-digital converter correction circuit of any of claims 1 to 7.
9. An analog-to-digital conversion method, characterized by comprising the steps of:
obtaining analog data to be converted through a pipeline type analog-to-digital converter, and converting to obtain an analog-to-digital conversion result and a digital code; the pipelined analog-to-digital converter is provided with a first bus port for outputting the digital code and a second bus port for outputting the analog-to-digital conversion result, the digital code is used for representing the current segment number of an output segment where the pipelined analog-to-digital converter is located, the number of the output segments is M, the number M of the output segments is determined according to the bit number of each sub-converter in the pipelined analog-to-digital converter, the bit number of the sub-converter in the pipelined analog-to-digital converter is Q, and M =2^ Q +1;
selecting a target trimming register unit from M trimming register units according to the digital code, wherein each trimming register unit is used for storing trimming parameters, and the M trimming parameters correspond to the M output sections one by one;
and utilizing an addition circuit to add the trimming parameters stored in the target trimming register unit and the analog-to-digital conversion result to obtain a correction conversion result.
10. The analog-to-digital conversion method according to claim 9, further comprising the steps of:
and outputting the correction conversion result to a result register.
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| DE69426819T2 (en) * | 1993-05-12 | 2001-07-19 | Analog Devices Inc., Norwood | ALGORITHMIC ANALOG / DIGITAL CONVERTER WITH DIGITAL CALIBRATED OUTPUT |
| WO2003084071A1 (en) * | 2002-04-02 | 2003-10-09 | Telefonaktiebolaget Lm Ericsson (Publ) | Comparator offset calibration for a/d converters |
| US7035756B2 (en) * | 2003-12-17 | 2006-04-25 | Texas Instruments Incorporated | Continuous digital background calibration in pipelined ADC architecture |
| KR100845134B1 (en) * | 2006-11-06 | 2008-07-09 | 삼성전자주식회사 | Digitally self-calibrating pipeline analog-to-digital converter and method of calibrating the same |
| US7378999B1 (en) * | 2007-03-06 | 2008-05-27 | Xilinx, Inc. | Method and apparatus for digital calibration of an analog-to-digital converter |
| US7688238B2 (en) * | 2007-03-27 | 2010-03-30 | Slicex, Inc. | Methods and systems for calibrating a pipelined analog-to-digital converter |
| CN101582696B (en) * | 2009-06-22 | 2012-06-27 | 中国电子科技集团公司第二十四研究所 | Single redundant bit digital correction method used for assembly line A/D converter |
| KR101685011B1 (en) * | 2010-12-09 | 2016-12-14 | 한국전자통신연구원 | Pipelined analog digital convertor |
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