JPH10106855A - Low parasitic capacitance transformer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a low parasitic capacitance transformer which can reduce the parasitic capacitance between its primary coil and secondary coil. SOLUTION: A transformer 3 is constructed by forming a first coil layer by winding a winding 14 around a core 10 and second soil layer by winding another winding 14 around an insulator 11 after coating the first coil layer with the insulator 11, and then, successively forming an insulator 12, a third coil layer, an insulator 13, and a fourth coil layer on the second coil layer. The primary coil N1 of the transformer is constituted of the second and fourth coil layers and the secondary coil N2 is constituted of the first and third coil layers. The thickness of the insulator 13 between the fourth coil layer of the primary coil N1 and the third coil layer of the secondary coil N2 across which the hourly fluctuation of the electric flux density becomes the largest is made thicker than. those of the insulators between the other coil layers. Therefore the interval between the third and fourth coil layers becomes larger and the parasitic capacitance between the primary and secondary coils N1 and N2 becomes smaller.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a low parasitic capacitance transformer incorporated in a device such as a switching power supply.

[0002]

2. Description of the Related Art A transformer has a primary coil and a secondary coil. A voltage applied to the primary coil has a winding ratio (N2) of the number of turns of the secondary coil N2 to the number of turns N1 of the primary coil.
/ N1) is output from the secondary coil. Such transformers include various types of transformers having different structures.

For example, a winding-type transformer in which a primary coil winding is wound around a core and a secondary coil winding is wound above the core via an insulator, or a coil pattern of the primary coil is formed. Core transformer, in which a substrate with a coil pattern of a secondary coil is formed, or a substrate in which a coil pattern of a secondary coil is formed with a substrate in which a coil pattern of a secondary coil is formed, and a core is formed in the laminate. There is a transformer mounted.

FIG. 9 shows an example of using a transformer. The transformer 3 is incorporated in a resonance reset single-stone forward converter used in a switching power supply device or the like, and the resonance reset single-stone forward converter incorporates a transformer having any of the above-described plural types of transformer structures. Can be. As shown in FIG.
On the primary coil N1 side of the transformer 3, an input circuit including a DC power supply 1, a switch element 2, and a control circuit 4 for performing switching control of the switch element 2 is formed.
On the second side, an output circuit including an output rectifying element 5, an output flywheel element 6, a choke coil 7 for smoothing, and a smoothing capacitor 8 is formed, and a load resistor 9 is connected to the smoothing capacitor 8 in parallel.

When the switching element 2 is turned on by the switching control of the control circuit 4, the current flows through the primary coil N1 and the switching element 2 in order from the positive electrode of the DC power supply 1. Then, energy is output from the C end side of the secondary coil N2 to charge the smoothing capacitor 8, and the DC voltage Vc8 smoothed by the smoothing capacitor 8 is supplied to the load resistor 9.

When the switch element 2 is turned off, the energy charged in the smoothing capacitor 8 is conducted through a path passing through the smoothing choke coil 7 and the output flywheel element 6 in order, and the voltage Vc8 of the smoothing capacitor 8 is applied to the load resistor 9. Supplied.

The control circuit 4 turns on the switch element 2 at a predetermined switching frequency, detects the voltage Vc8 of the smoothing capacitor 8, and supplies a predetermined output voltage to the load resistor 9 based on the detected value. In this case, the ON period of the switch element 2 is variably controlled.

[0008]

By the way, the transformer 3
The primary coil N1 is connected to the parasitic capacitance of the primary coil N1 alone.
The parasitic capacitance Cp to which the parasitic capacitance between the secondary coil N2 and the secondary coil N2 is added is generated in parallel with the primary coil N1. The drain of the switching element 2 - the parasitic capacitance C _s is generated between the source, the parasitic capacitance is generated in the output rectifier element 5 outputs the flywheel device 6 or the like. In the circuit of FIG. 9, the parasitic capacitances are charged when the switch element 2 is turned off, and the charge energy is discharged when the switch element 2 is turned on.
The charge and discharge are repeatedly performed in synchronization with the ON / OFF operation of the switch element 2.

The energy discharged by each of the parasitic capacitances when the switching element 2 is turned on is lost, and a short-circuit loss Psh expressed by the following equation (1) occurs.

Psh = (１ ／) · C · (Vin) ² · Fsw (1)

Here, C shown in the above equation (1) represents the total capacitance obtained by summing the respective parasitic capacitances generated in the circuit of FIG. 9, and the parasitic capacitance C of the transformer 3 with respect to the total parasitic capacitance C
The ratio occupied by p (Cp / C) is large. Also,
Vin represents the DC power supply voltage, and Fsw is the switching frequency of the switch element 2.

In recent years, the switching frequency of the switching element 2 has been increased from the viewpoint of reducing the size of the switching power supply device, and the short-circuit loss Psh has been markedly increased with the switching frequency of the switching element 2. As a result, the power loss of the circuit becomes very large.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to reduce the parasitic capacitance of a transformer and reduce the power loss of a circuit in which the transformer is incorporated. To provide a transformer.

[0014]

Means for Solving the Problems In order to achieve the above object, the present invention has the following structure to solve the above problems. That is, the first invention has a primary coil and a secondary coil, each of which has a plurality of coil layers in which a coil conductor is formed in one or more turns, and an insulator between the coil layers. A transformer in which a plurality of coil layers of a primary coil and a secondary coil are laminated in a predetermined order with the coil layer of the primary coil and the coil of the secondary coil having the largest temporal flux density variation The above-mentioned problem is solved by a configuration in which a predetermined low-parasitic capacitance method is applied to a region facing the layer.

According to a second aspect of the present invention, in the low parasitic capacitance method according to the first aspect of the present invention, an insulator between a coil layer of a primary coil and a coil layer of a secondary coil having the largest variation in electric flux density over time is provided. In order to solve the above-mentioned problem, the thickness is made larger than the thickness of the insulator between the other coil layers.

According to a third aspect of the present invention, there is provided the low parasitic capacitance method according to the first aspect of the invention, wherein the insulation between the coil layer of the primary coil and the coil layer of the secondary coil having the largest variation in electric flux density over time is provided. Means for solving the above-mentioned problem is that the body is formed of an insulating material having a dielectric constant smaller than that of the insulator between the other coil layers.

According to a fourth aspect of the present invention, there is provided a low parasitic capacitance method according to the first aspect of the invention, wherein the primary parasitic coil located in a region opposed to the coil layer of the primary coil and the coil layer of the secondary coil having the largest temporal flux density variation. Means for solving the above-mentioned problem is a configuration in which the coil conductors of the respective coils are formed so as to be shifted from each other in a direction in which the facing areas of the coil conductors of the coils and the secondary coil are reduced.

According to a fifth aspect of the present invention, a composite low parasitic capacitance method combining two or more low parasitic capacitance methods among the low parasitic capacitance methods implemented in the second, third, and fourth inventions is used. The above-mentioned problem is solved by a configuration in which the coil layer of the primary coil and the coil layer of the secondary coil have the largest variation in electric flux density.

In the invention having the above-described structure, for example, the low parasitic capacitance transformer may be configured such that the thickness of the insulator between the coil layer of the primary coil and the coil layer of the secondary coil, which has the largest fluctuation of the electric flux density over time, is other than that. Is formed thicker than the thickness of the insulator between the coil layers.

As described above, the thickness of the insulator between the coil layer of the primary coil and the coil layer of the secondary coil, which has the largest variation in the electric flux density over time, is greater than the thickness of the insulator between the other coil layers. By doing so, the distance between the coil layer of the primary coil and the coil layer of the secondary coil, which has the largest fluctuation of the electric flux density over time, is increased, and the parasitic capacitance between the coil layers is suppressed. For this reason, the parasitic capacitance between the primary coil and the secondary coil is reduced, and the overall parasitic capacitance of the transformer is reduced.

By incorporating this low parasitic capacitance transformer into, for example, the resonant reset single-pole forward converter shown in the conventional example, short-circuit loss when the switch element is turned on due to the reduction of the parasitic capacitance of the low parasitic capacitance transformer is obtained. Can be reduced, and the power loss of the resonance reset one-stone forward converter can be reduced.

[0022]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a cross-sectional structure of the low parasitic capacitance transformer according to the first embodiment in a state where it is incorporated in a resonance reset monolithic forward converter. Note that the configuration of the resonance reset monolithic forward converter other than the low parasitic capacitance transformer 3 is the same as the configuration in FIG. 9 described above, and the same components as those in the circuit configuration in FIG.

The transformer 3 shown in FIG. 1 comprises a primary coil N1, a secondary coil N2, a core 10, insulators 11, 12,
13. As shown in FIG. 1, a winding 14 which is a coil conductor is wound around a core 10, a first coil layer is formed, and an insulator 1- is formed on the coil layer.
A two-layer insulator 11 is provided.
1, a winding 14 is further wound to form a second coil layer, a 2-3 interlayer insulator 12 as an insulator is further formed thereon, and a third coil A coil layer, a 3-4 interlayer insulator 13 which is an insulator, and a fourth coil layer around which the winding 14 is wound are sequentially formed in the same manner as described above.

One end b of the winding 14 of the second coil layer
Is connected to one end c of the winding 14 of the fourth coil layer, and a primary coil N1 is formed by the series connection of the second and fourth coil layers. 1
4 is connected to the A end shown in FIG.
The other end d of the winding 14 of the fourth coil layer is connected to the end B shown in FIG. 1, that is, connected to the drain side of the switch element 2.

One end e of the winding 14 of the first coil layer
Is connected to one end g of the winding 14 of the third coil layer, and the other end f of the winding 14 of the first coil layer and the other end h of the winding 14 of the third coil layer. The secondary coil N2 is formed by the parallel connection of the first and third coil layers, and the winding end e of the first coil layer and the winding end of the third coil layer are formed. g is connected to the end C (the cathode side of the output flywheel element 6) shown in FIG. 1 and the winding end f of the first coil layer and the winding end h of the third coil layer. Is connected to the D end (the cathode side of the output rectifying element 5) shown in FIG.

In this embodiment, ten windings are wound on each of the first to fourth coil layers, and the second and fourth coil layers are connected in series to form the primary coil N1.
, The number of turns of the primary coil N1 is 20 turns (20T). On the other hand, the first and third coil layers are connected in parallel to form the secondary coil N2. The number of turns of the coil N2 is 10T, and the ratio of the number of turns between the primary coil N1 and the secondary coil N2 is 2: 1.

In this embodiment, the coil layer of the primary coil N1 having the larger number of turns is formed so as to be the outermost layer.
The winding end d of the outermost coil layer is connected to the drain side of the switch element 2.

As shown in FIG. 2B, the voltage at the A end of the primary coil N1 does not fluctuate even when the switch element 2 is turned on and off, but the voltage at the A end of the primary coil N1 is not changed. When the switch element 2 is turned off, the voltage starts to fluctuate as shown in FIGS. 2C and 2D, and the fluctuation width (the voltage when the switch element 2 is on). Of the primary coil N1 increases from the end A to the end B of the primary coil N1.

As shown in FIG. 2E, the voltage on the other end of the secondary coil N2 is also switched to the switch element 2 as shown in FIG.
Does not fluctuate even if the secondary coil N2
As the switch element 2 is turned off, the voltage starts to fluctuate as shown in FIG. 2 (f) from the C end to the D end of the secondary coil N2. It becomes larger as going from the part side to the D end part side.

The voltage fluctuation width of the primary coil N1 at the end B where the voltage fluctuation is the largest is the secondary coil N1 since the turn ratio between the primary coil N1 and the secondary coil N2 is 2: 1.
2 is twice as large as the voltage fluctuation width on the D end side where the voltage fluctuation is the largest.

As described above, when the voltage applied to the coil winding 14 fluctuates, the density of the electric flux generated from the winding 14 fluctuates due to the voltage fluctuation. Becomes greater as the temporal variation of the voltage applied to the winding 14 increases. For this reason, in this embodiment, the temporal change in the electric flux density is the largest on the B end side of the primary coil N1 having the largest voltage fluctuation range when the switch element 2 is turned off.

That is, in the transformer 3, the insulator between the coil layer of the primary coil N 1 and the coil layer of the secondary coil N 2 having the largest variation of the electric flux density over time is the 3-4 interlayer insulator 13.

In this embodiment, the following low parasitic capacitance method is applied to the 3-4 interlayer insulator 13. The low parasitic capacitance method is that the thickness of the 3-4 interlayer insulator 13 is larger than the thicknesses of the other insulators 11 and 12.

As described above, by increasing the thickness of the 3-4 interlayer insulator 13, the third coil layer (secondary coil N
The distance between 2) and the fourth coil layer (primary coil N1) is increased, which reduces the parasitic capacitance between the third and fourth coil layers. That is, the parasitic capacitance generated between the primary coil N1 and the secondary coil N2 is reduced, and the overall parasitic capacitance Cp of the transformer 3 can be reduced. For this reason, by incorporating the low-capacity transformer of this embodiment into the resonance reset single-switch forward converter shown in FIG. 1, the switching element 2 of the resonance reset single-switch forward converter is reduced due to the reduction of the parasitic capacitance Cp of the transformer 3. It is possible to reduce the short-circuit loss Psh at the time of ON.

According to this embodiment, since the thickness of the 3-4 interlayer insulator 13 having the largest variation in the electric flux density over time is made larger than the thicknesses of the other insulators 11 and 12, the primary coil N1 And the third coil layer of the secondary coil N2
, The parasitic capacitance between the third and fourth coil layers can be reduced, and the parasitic capacitance Cp of the transformer 3 can be reduced. From this,
By using the low parasitic capacitance transformer 3 of this embodiment, in the resonance-reset one-switch forward converter shown in FIG. 1, the energy that is discharged and lost when the switch element 2 is turned on is reduced, that is, when the switch element 2 is turned on. Short-circuit loss Psh can be reduced, and power loss in the circuit can be reduced.

In this embodiment, since only the thickness of the 3-4 interlayer insulator 13 is increased, the size of the transformer 3 is increased as compared with the case where the thickness of all the insulators 11, 12, 13 is increased. Can be prevented. Further, as described above, when the thicknesses of all the insulators 11, 12, and 13 are increased, a problem that the degree of electromagnetic coupling between the primary coil N1 and the secondary coil N2 is reduced occurs, but as in this embodiment. In addition, by increasing only the thickness of the insulator (3-4 interlayer insulator 13) between the coil layer of the primary coil N1 and the coil layer of the secondary coil N2 having the largest variation in the electric flux density over time, the primary A decrease in the degree of electromagnetic coupling between the coil N1 and the secondary coil N2 can be avoided as compared with a case where the thicknesses of all the insulators 11, 12, 13 are increased.

Further, in this embodiment, since only the thickness of the 3-4 interlayer insulator 13 is increased, the amount of insulating material forming the insulator is slightly increased, and the material cost is not greatly increased. It is possible to provide the low parasitic capacitance transformer 3 which exhibits the above-described excellent effects at low cost.

Hereinafter, a second embodiment will be described. FIG. 3 shows a cross-sectional structure of a low parasitic capacitance transformer according to the second embodiment. The transformer 3 is formed by laminating first to fourth coil layers each formed by winding a coil pattern as a coil conductor in a planar shape with insulators 11, 12, and 13 interposed between the coil layers. is there.

In this embodiment, the first coil layer has 1
A wound coil pattern 15 is formed, a five-turn coil pattern 15 is formed on the second coil layer, a two-turn coil pattern is formed on the third coil layer, and a fourth coil layer is formed on the fourth coil layer. Four turns of the coil pattern 15 are formed.

The coil pattern 15 of the first coil layer
Is connected to one end (center end) of the coil pattern 15 of the third coil layer, and the first and third coil layers constitute a secondary coil N2. I have. One end (center end) of the coil pattern 15 of the second coil layer is connected to one end (center end) of the coil pattern 15 of the fourth coil layer. The primary coil N1 is constituted by the coil layers. The number of turns of the primary coil N1 is 9T, the number of turns of the secondary coil N2 is 3T, and the turn ratio of the primary coil N1 to the secondary coil N2 is 3: 1.

The end of the coil pattern of the first coil layer on the end side is connected to the C end shown in FIG. 1, and the end of the coil pattern of the second coil layer on the side of A shown in FIG. The end of the coil pattern of the third coil layer is connected to the D end shown in FIG. 1, and the end of the coil pattern of the fourth coil layer is shown in FIG. By connecting to the B end shown, the transformer of FIG. 3 can be incorporated into the resonant reset single-piece forward converter shown in FIG.

In this embodiment, as described above, the primary coil N1 has a larger number of turns than the secondary coil N2, and is formed such that the coil layer of the primary coil N1 having the larger number of turns is the uppermost layer. The end of the coil layer of the primary coil N1, which is the uppermost layer, is connected to the drain side of the switch element 2 in FIG.

Further, as described in the first embodiment, the fluctuation range of the voltage increases from the end A to the end B of the primary coil N1, and the voltage of the secondary coil N2 increases. Since the fluctuation range of the voltage increases from the C end side to the D end side, and the electric flux density fluctuates according to the voltage fluctuation, in the transformer shown in FIG. The insulator between the coil layer of the large primary coil N1 and the coil layer of the secondary coil N2 is the 3-4 interlayer insulator 13, and in this embodiment, the 3-4 interlayer insulator 1
No. 3 employs a low parasitic capacitance method as described below.

The above-mentioned low parasitic capacitance method is that the thickness of the 3-4 interlayer insulator 13 is made larger than the thicknesses of the other insulators 11 and 12. As described above, by increasing the thickness of the 3-4 interlayer insulator 13, the distance between the third and fourth coil layers is increased, and the parasitic capacitance between the third and fourth coil layers is reduced. That is, the primary coil N1 and the secondary coil N
The parasitic capacitance between the transformers 3 becomes smaller, and the parasitic capacitance Cp of the transformer 3 can be reduced.

According to this embodiment, since the thickness of the 3-4 interlayer insulator 13 is made larger than the thicknesses of the other insulators 11 and 12, the parasitic capacitance of the transformer 3 is the same as in the first embodiment. The capacitance Cp can be reduced. From this,
By incorporating the low parasitic capacitance transformer 3 of this embodiment in the circuit shown in FIG. 1, as described in the first embodiment, the short-circuit loss P
sh can be reduced, and power loss of the circuit can be reduced.

Also, since only the thickness of the 3-4 interlayer insulator 13 is increased, it is possible to prevent the transformer 3 from increasing in size as compared with the case where the thicknesses of all the insulators 11, 12, 13 are increased. it can. Furthermore, since only the thickness of the 3-4 interlayer insulator 13 is increased as described above, all the insulators 1
It is possible to avoid a decrease in the degree of electromagnetic coupling between the primary coil N1 and the secondary coil N2 as compared with a case where the thicknesses of the coils 1, 12, and 13 are increased.

Hereinafter, a third embodiment will be described. FIG. 4 shows a cross-sectional structure of a low parasitic capacitance transformer according to the third embodiment. This transformer 3 has a coil pattern 1
The first to eighth coil layers 5 are wound in a plane, and are laminated with an insulator 16 interposed between the coil layers, and a core 10 is mounted on the laminated body.

In this embodiment, one turn, one turn, two turns, two turns,
The coil pattern 15 of one winding, one winding, one winding, two windings, and two windings is formed. The center-side ends of the coil patterns 15 of the first and second coil layers are connected to each other, and the end-side ends of the coil patterns 15 of the first and second coil layers are connected to each other. Similarly, the fifth and sixth
Of the coil patterns 15 of the respective coil layers are connected to each other, and the coil patterns 1 of the fifth and sixth coil layers are connected to each other.
5 are connected to each other.

Further, the center connection portions of the coil patterns 15 of the first and second coil layers and the center connection portions of the coil patterns 15 of the fifth and sixth coil layers are connected. , The second, the fifth and the sixth coil layers constitute a secondary coil N2, and the number of turns of the secondary coil N2 is 2
T.

The ends of the coil patterns 15 on the center side of the third and fourth coil layers are connected to each other.
And the end of the coil pattern 15 of the eighth coil layer on the center side is connected to the end of the coil pattern 15 of the fourth coil layer and the end of the coil pattern 15 of the seventh coil layer. The part side end is connected. The third, fourth, seventh and eighth coil layers constitute a primary coil N1, and the number of turns of the primary coil N1 is 8T.

The first and second coil layers (secondary coil N
The end side connection part of the coil pattern 15 of 2) is connected to the C end shown in FIG. 1, and the third coil layer (primary coil N1)
The end of the coil pattern 15 is connected to the end A shown in FIG. 1 and the fifth and sixth coil layers (secondary coil N2)
1 is connected to the D end shown in FIG. 1, and the end of the coil pattern 15 of the eighth coil layer (primary coil N1) is the B end shown in FIG. And the transformer 3 of FIG. 4 is incorporated in the resonance reset one-stone forward converter of FIG.

As described above, in this embodiment, the number of turns of the primary coil N1 is larger than the number of turns of the secondary coil N2, and the coil layer of the primary coil N1 having the larger number of turns is the uppermost layer. The winding end of the eighth coil layer of the primary coil N1 which is the uppermost layer is the switch element 2 of FIG.
Connected to the drain side.

Further, as described in the first embodiment, the fluctuation range of the voltage increases from the end A to the end B of the primary coil N1. Since the fluctuation range of the voltage increases from the C end side to the D end side, and the electric flux density fluctuates according to the voltage fluctuation width, in this embodiment, the temporal electric flux density fluctuation The insulator between the coil layer of the largest primary coil N1 and the coil layer of the secondary coil N2 is the insulator between the sixth and seventh coil layers. In this embodiment, the same low-parasitic-capacity method as that of the above-described embodiments is applied to the insulator 16 between the sixth and seventh coil layers.

That is, the thickness of the insulator 16 between the sixth and seventh coil layers was formed larger than the thickness of the insulator 16 between the other coil layers. As described above, by increasing the thickness of the insulator 16 between the sixth and seventh coil layers, the sixth and seventh coil layers are formed.
The distance between the coil layers is widened, and the parasitic capacitance between the sixth and seventh coil layers can be reduced. As a result, the parasitic capacitance between the primary coil N1 and the secondary coil N2 can be reduced, and the parasitic capacitance Cp of the transformer 3 can be reduced.

According to this embodiment, the thickness of the insulator 16 between the seventh coil layer of the primary coil N1 and the sixth coil layer of the secondary coil N2 having the largest variation in the electric flux density over time is reduced. Since it was thicker than the other coil layers,
As in the above embodiments, the parasitic capacitance between the primary coil N1 and the secondary coil N2 can be reduced, and the parasitic capacitance Cp of the transformer 3 can be reduced. Accordingly, when the low parasitic capacitance transformer 3 of this embodiment is incorporated in the circuit shown in FIG. 1, the short-circuit loss Psh generated when the switch element 2 is turned on can be reduced, and the power loss of the circuit can be reduced. .

The insulator 1 between the sixth and seventh coil layers
6, the transformer 3 can be prevented from increasing in size as compared with a case where the thickness of the insulator 16 between all coil layers is increased, and the primary coil N1 and the secondary coil N
It is possible to prevent a decrease in the degree of electromagnetic coupling between the two.

Hereinafter, a fourth embodiment will be described. This embodiment is different from the above-described embodiments in that the primary coil N having the largest variation in the electric flux density over time.
The insulator between the coil layer of the first coil N1 and the coil layer of the secondary coil N2 is not formed to be thicker than the other insulators. The configuration is such that the insulator between the coil layers of the next coil N2 is formed of an insulating material having a dielectric constant smaller than the dielectric constant of the other insulator and a low parasitic capacitance method is applied. The other configurations are the same as those of the above-described embodiments, and the description thereof will not be repeated.

According to this embodiment, the insulator between the coil layer of the primary coil N1 and the coil layer of the secondary coil N2, which has the largest temporal change in the electric flux density, is used as the insulator between the other coil layers. Since it is formed of an insulating material having a dielectric constant smaller than the dielectric constant, it is possible to reduce the parasitic capacitance between the coil layers of the primary coil N1 and the secondary coil N2, which have the largest temporal flux density variation. From this,
The parasitic capacitance between the primary coil N1 and the secondary coil N2 is reduced, and the parasitic capacitance Cp of the transformer 3 can be reduced.

Therefore, as in each of the above embodiments, by incorporating the low-parasitic capacitance transformer of this embodiment into the circuit shown in FIG. 1, the energy that is discharged and lost when the switch element 2 is turned on is reduced. 2 can reduce the short-circuit loss Psh at the time of ON.

Hereinafter, a fifth embodiment will be described. What is characteristic in this embodiment is that the primary coil N in the opposing region between the coil layer of the primary coil N1 and the coil layer of the secondary coil N2, which has the largest variation in the electric flux density over time.
As shown in the coil patterns 15a and 15b of FIG.
In this case, the configuration is such that a low parasitic capacitance method is employed in which the respective coil conductors are formed shifted from each other. Other configurations are the same as those of the above-described embodiments, and the description thereof will not be repeated.

According to this embodiment, the primary coil N1 located in the opposing area between the coil layer of the primary coil N1 and the coil layer of the secondary coil N2 having the largest variation in the electric flux density over time.
Since the coil conductors of the respective coils are shifted from each other in a direction to reduce the facing area of the coil conductor of the secondary coil N2 and the coil conductor of the secondary coil N2, the facing area of the coil conductors of the primary coil N1 and the secondary coil N2 is reduced, It is possible to reduce the parasitic capacitance between the coil conductors whose formation positions are shifted, thereby reducing the parasitic capacitance between the primary coil N1 and the secondary coil N2.

As described above, the parasitic capacitance Cp of the transformer 3 can be reduced in the same manner as in each of the above embodiments. By incorporating the low parasitic capacitance transformer 3 of this embodiment into the circuit of FIG. It is possible to reduce the short-circuit loss Psh at the time of ON.

The present invention is not limited to the above embodiments, but can take various forms. For example, in each of the above embodiments, the number of turns of the primary coil N1 is larger than the number of turns of the secondary coil N2.
The present invention can also be applied to a transformer in which the number of turns of the secondary coil N2 is larger than the number of turns of the primary coil N1.

In each of the above embodiments, the transformer 3 is incorporated in an anode common connection type resonance reset one-stone forward converter in which the anodes of the output rectifying element 5 and the output flywheel element 6 shown in FIG. 1 are connected to each other. Although shown, as shown in FIG. 6, the output rectifying element 5 and the output flywheel element 6 may be incorporated in a cathode common connection type resonance reset monolithic forward converter in which the cathodes are connected to each other. Also in this case, by incorporating the transformer 3 as in each of the above-described embodiments,
The short-circuit loss Psh when the switch element 2 is turned on can be reduced. Further, it may be incorporated in a flyback converter as shown in FIG. 7 or FIG. 8, and excellent effects can be obtained as described above.

Further, the low parasitic capacitance method combining two or more low parasitic capacitance methods described in the above embodiments is combined with the coil layer of the primary coil N1 and the secondary coil N2 having the largest temporal flux density variation. May be applied to the facing region of the coil layer.

For example, the thickness of the insulator between the coil layer of the primary coil N1 and the coil layer of the secondary coil N2 having the largest variation in the electric flux density with time is made larger than the thickness of the other insulators. An insulator between the coil layer of the primary coil N1 and the coil layer of the secondary coil N2, which has the largest variation in electric flux density over time, is formed of an insulating material having a dielectric constant smaller than that of the other insulators. You may do so. In this way, by combining a plurality of low parasitic capacitance methods, it is possible to further reduce the parasitic capacitance between the primary coil N1 and the secondary coil N2.

[0068]

According to the present invention, a predetermined low-parasitic capacitance method is applied to a region where the coil layer of the primary coil and the coil layer of the secondary coil have the greatest temporal flux density variation. In addition, the parasitic capacitance between the coil layer of the primary coil and the coil layer of the secondary coil to which the low parasitic capacitance method has been applied can be reduced, and the parasitic capacitance between the primary coil and the secondary coil can be reduced. As a result, the overall parasitic capacitance of the transformer is reduced. By incorporating this transformer into a circuit such as a switching power supply, the energy that is discharged and lost due to the switching operation of the switching element can be reduced, and the power of the circuit can be reduced. Loss can be reduced.

A low parasitic capacitance in which the thickness of the insulator between the coil layer of the primary coil and the coil layer of the secondary coil having the greatest temporal flux density variation is greater than the thickness of the insulator between the other coil layers. In the configuration that applies the method, the distance between the coil layer of the primary coil and the coil layer of the secondary coil, which has the largest temporal flux density fluctuation, increases, and the parasitic capacitance between the coil layers of the primary coil and the secondary coil decreases. Can be reduced. Thus, the overall parasitic capacitance of the transformer can be reduced as described above.

As described above, since only the insulator between the coil layer of the primary coil and the coil layer of the secondary coil, which has the largest variation in the electric flux density over time, is thickened, all the coil layers It is possible to avoid a decrease in the degree of electromagnetic coupling between the primary coil and the secondary coil, an increase in the size of the transformer, and an increase in cost, as compared with a case where the thickness of the transformer is increased.

The insulator between the coil layer of the primary coil and the coil layer of the secondary coil, which has the largest variation in the electric flux density over time, is made of an insulating material having a dielectric constant smaller than that of the insulator between the other coil layers. In the configuration in which the low parasitic capacitance method is applied, the dielectric constant of the insulator between the coil layers of the primary coil and the secondary coil subjected to the low parasitic capacitance method is the dielectric constant of the insulator between the other coil layers. Since it is smaller than this, the parasitic capacitance between the coil layers of the primary coil and the secondary coil is reduced, and the overall parasitic capacitance of the transformer can be reduced. Although an insulating material having a smaller dielectric constant is expensive, as described above, only the insulating material between the coil layers of the primary coil and the coil layer of the secondary coil, which has the largest temporal flux density fluctuation, is more dielectric. Since the transformer is formed with a small ratio, it is possible to suppress an increase in the cost of the transformer.

In the direction in which the opposing area of the coil conductor of the primary coil and the coil conductor of the secondary coil in the region where the coil layer of the primary coil and the coil layer of the secondary coil have the largest temporal fluctuation of the electric flux density is reduced. In the configuration in which the low parasitic capacitance method of forming the coil conductors of the respective coils so as to be shifted from each other, the facing area between the coil conductor of the primary coil and the coil conductor of the secondary coil is reduced, and the distance between the primary coil and the secondary coil is reduced. Can be reduced. From this, it is possible to reduce the overall parasitic capacitance of the transformer, as described above.

Among the above low parasitic capacitance methods, a composite low parasitic capacitance method combining two or more low parasitic capacitance methods is applied to a coil layer of a primary coil and a coil layer of a secondary coil having the greatest temporal flux density variation. In this configuration, the parasitic capacitance between the coil layer of the primary coil and the coil layer of the secondary coil, which has the largest variation in the electric flux density over time, can be further reduced. Can be reduced.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram showing a first embodiment example.

FIG. 2 is a waveform diagram showing a temporal change of a voltage at each point in the transformer of FIG. 1;

FIG. 3 is an explanatory diagram showing a second embodiment example.

FIG. 4 is an explanatory diagram showing a third embodiment.

FIG. 5 is an explanatory diagram showing a fifth embodiment.

FIG. 6 is a circuit diagram showing another example of a circuit in which the transformer according to the present invention is incorporated.

FIG. 7 is a circuit diagram showing still another example of a circuit in which the transformer according to the present invention is incorporated.

FIG. 8 is a circuit diagram showing still another example of a circuit in which the transformer according to the present invention is incorporated.

FIG. 9 is a circuit diagram showing a conventional example.

[Explanation of symbols]

 3 Transformer 13 3-4 Interlayer insulator 14 Winding 15 Coil pattern 16 Insulator

Claims (5)

[Claims] 1. A coil having a primary coil and a secondary coil, each of which has a plurality of coil layers in which a coil conductor is formed one or more turns, with an insulator interposed between the coil layers. A transformer in which a plurality of coil layers of a primary coil and a secondary coil are laminated in a predetermined order, and the coil layer of the primary coil and the coil layer of the secondary coil having the largest temporal flux density variation are opposed to each other. A low parasitic capacitance transformer characterized in that a predetermined low parasitic capacitance method is applied to a region. 2. The low parasitic capacitance method is to reduce the thickness of the insulator between the coil layer of the primary coil and the coil layer of the secondary coil, which has the largest temporal flux density variation, by changing the thickness of the insulator between the other coil layers. 2. The low parasitic capacitance transformer according to claim 1, wherein the transformer is configured to be thicker than the thickness. 3. The low-parasitic-capacity method uses an insulator between a coil layer of a primary coil and a coil layer of a secondary coil, which has the largest variation in electric flux density with time, and an insulator between other coil layers. 2. The low parasitic capacitance transformer according to claim 1, wherein the low parasitic capacitance transformer is formed of an insulating material having a dielectric constant smaller than the dielectric constant. 4. The low-parasitic-capacitance method uses a coil conductor of a primary coil and a coil conductor of a secondary coil in an area where the coil layer of the primary coil and the coil layer of the secondary coil have the largest variation in electric flux density over time. 2. The low parasitic capacitance transformer according to claim 1, wherein the coil conductors of the respective coils are formed so as to be shifted from each other in a direction to reduce the facing area. 5. A composite low parasitic capacitance method combining two or more low parasitic capacitance methods among the low parasitic capacitance methods applied to the low parasitic capacitance transformer according to claim 2, 3, and 4. 2. The low parasitic capacitance transformer according to claim 1, wherein the step (c) is performed on a region where the coil layer of the primary coil and the coil layer of the secondary coil have the largest temporal change in electric flux density.