JPH10105379A - Three-input adding and subtracting circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the three-input adding and subtracting circuit which can obtain an arithmetic result with high precision when plural input data including both a value represented as a complement of 2 and a value represented as an absolute value are added and subtracted. SOLUTION: Two input data are added by an adder 1 and then added by an adder 2 to 3rd input data, and the result is outputted to a selector 3. This selector 3 inputs two fixed data of OOH and FFH in addition to the output from the adder 2. A logic circuit 4 judges whether the addition result outputted from the adder 1 is a numeral represented as an absolute value or a complement of 2. Then a logic circuit 5 and a selection signal output circuit 6 outputs a selection signal for selecting one of the three data supplied to the selector 3 according to the judgement result and a carry signal from the adder 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a three-input addition / subtraction circuit for performing addition / subtraction of three input data, and more particularly to a three-input addition / subtraction circuit used in a color space conversion technique for converting a color difference signal of a moving image processing in image processing into a color signal of three primary colors. It relates to a suitable three-input addition / subtraction circuit.

[0002]

2. Description of the Related Art Color expression methods in image processing include a YUV method used for recording video data and the like and an RGB method used on a personal computer. Here, “Y”, “U”, and “V” in the YUV system represent Y, brightness, U, red color difference, and V, blue color difference, respectively. In the RGB system, "R", "G", and "B" represent R for red, G for green, and B for blue, and the numerical ranges of these three signals are all positive numerical values.

In the moving image processing, when converting from YUV to RGB, R = α1V + α2Y, B = β1U + β2
Y, G = γ1U + γ2V + γ3Y (α1, α2, β1, β2,
γ1, γ2, and γ3 are constants). According to this conversion equation, two-input addition is performed for the R signal and the B signal, and three-input addition is performed for the G signal. In the above conversion formula, the value of the term relating to “U” and “V”, that is, the value of α1V, β1U, γ1U, and γ2V takes a positive or negative value, and the value of the term relating to “Y”, that is, , Α2Y,
β2Y and γ3Y take only positive values. Furthermore, the conversion operation is
Usually, it is performed by an adder having the same bit length.

Here, a conventional example of an adder which can perform three-input addition as in the case of performing conversion to a G signal in the above-described conversion operation will be described with reference to FIG. The adder shown in FIG. 5 increases the calculation accuracy at the time of overflow by performing a pasting process when an odd number of overflows occur during the calculation. here,
The paste process means that when the operation result overflows, if the overflow exceeds the upper limit value of the output numerical value range of the adder, the upper limit value is output as the operation result, and the lower limit value of the output numerical value range is output. If the value is lower than, the process of outputting the lower limit value as the calculation result is called.

In FIG. 5, reference numeral 401 denotes an adding circuit.
It is composed of four full adders, stored in the accumulation register 407, and the augmented data terminals 412, 41
The addition data input from the addition data input terminals 408, 409, 410, 411 is added to the data to be added output to 3, 414, 415. Further, the addition circuit 410
Are output by the addition result output terminals 416, 417,
The signals are output to 418 and 419 and stored in the accumulation register 407. In this figure, the addition data input terminal 4
08, the augmented data terminal 412, and the addition result output terminal 416 are respectively
And the MSB of the addition result.

Reference numeral 402 denotes a single overflow detector 402 which is an exclusive OR gate, and determines whether or not the operation result of the adding circuit 401 is an overflow. 403
Is an overflow state memory, which stores whether the number of times the single overflow detector 402 has become "1" is an even number or an odd number. A polarity code memory 404 is a D flip-flop. The overflow state memory 403 indicates an even number, and stores the most significant bit of the addition circuit 401 every time the single overflow detector 402 becomes “1” again. Further, the output of the polarity code memory 404 is output when the addition result of the addition circuit 401 overflows.
The overflow code is output to the overflow polarity terminal 422 as a polarity code signal for determining whether the overflow exceeds the upper limit of the addition result range (plus overflow) or falls below the lower limit (minus overflow).

An overflow occurrence memory 405 is an RS flip-flop. The output of the single overflow detector 402 and the output of the overflow state memory 403 are both "1".
Most significant bit of addition result by 1 and polarity code memory 40
Set when the contents of the bits stored in 4 are equal. Reference numeral 406 denotes an overflow detection circuit which outputs a logical sum of an output of the overflow state memory 403 and an output of the overflow occurrence memory 405 to the overflow terminal 425. 420, 421, 42
Reference numerals 3 and 424 denote clear terminals for clearing the contents of the accumulation register 407, the polarity code memory 421, the overflow occurrence memory 405, and the overflow state memory 403, respectively.

The adder described above clears the accumulation register 407, the overflow state memory 403, the overflow occurrence memory 405, and the polarity code memory 404 before performing the continuous addition or subtraction, and performs the overflow after performing the continuous addition or subtraction. "1" from the detection circuit 406
Is output, it is detected that overflow has occurred in the result of continuous addition or subtraction, and the polarity code memory 40 is detected.
5 is an arithmetic circuit with an overflow detector for detecting the overflow on the plus side or the minus side. This adder is described in
This is disclosed in detail in Japanese Patent Publication No. -30467.

[0009]

Conventionally, color space conversion in moving image processing has been performed with full bits. That is, for example, in the case of the above-described adder, the most significant bit is used as a sign flag indicating the sign of the numerical value.
128 to 127. In such a case, YU
When the conversion from V to RGB is performed, if the overflow occurs at the time of calculating γ1U + γ2V in the conversion calculation of the G signal, the calculation accuracy of the R signal and the B signal is significantly different, and the image before conversion is different from the image before conversion. There is a problem that the converted images are different.

For example, when converting into a G signal, the values of γ1U and γ2V are both 100 (0110010 in binary).
0), the value of γ3Y is 50 (00110010 in binary)
In this case, when the value of γ1U + γ2V is calculated, the value becomes 200, and an overflow occurs on the plus side. Then, the value of γ3Y is successively added, and the conversion operation ends.
Since the overflow occurs only once and the output of the polarity code memory 404 becomes “0”, it is determined that the overflow on the positive side has occurred. As a result, the pasting process is performed and the operation result is 127 (01 in binary number).
111111), which is far from the original value of 250 (11111010 in binary).

SUMMARY OF THE INVENTION The present invention has been made in view of such circumstances, and is intended to be used when adding or subtracting a plurality of input data in which a value represented by a two's complement and a value represented by an absolute value are mixed. It is another object of the present invention to provide a three-input addition / subtraction circuit capable of obtaining a highly accurate operation result.

[0012]

According to a first aspect of the present invention, there is provided a three-input addition / subtraction circuit configured to add at least three pieces of data including data represented by two's complement and configured in units of a plurality of bits. The first data and the second data of at least three data bits
Adding means for adding the first data and the second data for adding the output of the first adding means and the third data of at least three pieces of data composed of a plurality of bits. Means, and an addition result of the first adding means,
It is determined whether the value is represented by an absolute value or a value represented by a two's complement, and according to the result of the determination, a paste process is performed on the addition result of the second addition means. And a sticking processing means for performing.

According to a second aspect of the present invention, in the three-input addition / subtraction circuit according to the first aspect, each of the first and second adding means is provided when the addition result exceeds a maximum value which can be output. Adding means for outputting a carry signal, wherein the pasting processing means includes: a state of each most significant bit of the first and second data input to the first adding means; The first signal based on the carry signal from
Determining whether the addition result obtained by the addition means is a value represented by an absolute value or a value represented by a two's complement, and a determination result by the first determination means. And, based on the carry signal from the second addition means, the addition result in the second addition means exceeds the upper limit or the lower limit of the numerical range of the operation result output by the three-input addition / subtraction circuit. Second determining means for determining whether the value is lower than the maximum value and the minimum value of the numerical values output by the three-input addition / subtraction circuit, and the addition result of the second adding means; Selecting means for outputting any one of the values based on the determination result.

According to a third aspect of the present invention, in the three-input addition / subtraction circuit according to the second aspect, the first judging means comprises:
When the most significant bits of the first and second data input to the first addition means are both "1", or
The most significant bits of the second data are “0” and “1”, respectively.
Alternatively, if the carry signal is "1" or "0" and no carry signal is output from the first adding means, it is determined that the addition result of the first adding means is a value expressed in two's complement. , The first and second signals inputted to the first adding means.
When the most significant bits of the second data are both “0”,
Alternatively, when the most significant bits of the first and second data are “0” and “1” or “1” and “0”, respectively, and the carry signal is output from the first adding means, It is characterized in that it is determined that the result of the addition by the first adding means is a value expressed as an absolute value.

According to a fourth aspect of the present invention, in the three-input addition / subtraction circuit according to the second aspect, the second determination means includes:
If the first determining means determines that the result of addition in the first adding means is a value represented by a two's complement, and the carry signal is not output from the second adding means, It is determined that the result of the addition by the adding means of 2 is below the lower limit of the numerical range of the operation result output by the three-input addition / subtraction circuit, and the result of addition by the first adding means is determined by the first determining means to be an absolute value. Is determined to be a value represented by the following expression, and when the carry signal is output from the second addition means, the addition result in the second addition means is a numerical range of the operation result output from the three-input addition / subtraction circuit. Is determined to exceed the upper limit.

According to a fifth aspect of the present invention, in the three-input addition / subtraction circuit according to any one of the first to fourth aspects, all of the at least three data composed of a plurality of bits have the same bit length. It is characterized by being comprised from.

According to a sixth aspect of the present invention, in the three-input addition / subtraction circuit according to any one of the first to fifth aspects, the first data, the second data, and the third
Are image data and color difference signals.

According to the three-input addition / subtraction circuit of the present invention, YU
In the color space conversion from V to RGB, in the conversion operation of the G signal, that is, the conversion operation of G = γ1U + γ2V + γ3Y, when the addition result of γ1U + γ2V is positive, the absolute value expression is used as a result, and when the addition result is negative, two's complement expression is used. (Sign flag) is provided, and at the time of addition of the Y signal, overflow processing after addition of the Y signal is performed by taking the logic of the carry signal and the sign flag bit. Thereby, for example, the conversion operation accuracy of the G signal after the addition of the Y signal can be matched with the conversion operation accuracy of the R signal and the B signal.

[0019]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a three-input addition / subtraction circuit to which the present invention is applied. FIG. 2 shows a YUV data conversion circuit. FIG.
In the figure, reference numeral 201 denotes a YUV data conversion circuit which adds constants α1, α2, β1, β2, γ1, γ to the Y, U, V data input to the input terminals 202, 203, 204, respectively.
2, γ3 and output terminals 205, 206, 20
7, 208, 209, 210, 211, α1V, α2
Y, β1U, β2Y, γ1U, γ2V, and γ3Y data are output. Here, γ1U output from the output terminal 209
Is input to the input terminal 101 of FIG.
Γ2V data output from the input terminal 10 shown in FIG.
2, the γ3Y data output from the output terminal 211 is output to the input terminal 107 in FIG.

In FIG. 1, reference numerals 1 and 2 denote 8-bit adders (hereinafter simply referred to as adders) each having 8 input / output bits.
The γ1U data input to the input terminal 101 and the γ2V data input to the input terminal 102 are added, and the result of the addition is output to the input terminal 106 of the adder 2. The adder 2 is the adder 1 input to the input terminal 106.
And the γ3Y data input to the input terminal 107 are added. Further, when the addition result in the adder 1 exceeds FFH, a carry signal is output. Here, the input / output numerical value range of the adder 1 is -128 to 127, and when the most significant bit of the input / output data is "0", it indicates a positive value, and when "1", it indicates a negative value. I have. The numerical value range of the input and output of the adder 2 is 0 to 255.
When the addition result exceeds FFH, a carry signal is output.

Reference numeral 3 denotes a selector, and three input terminals 11
3, 114 and 115, and outputs data input to any one of the input terminals from an output terminal 116 in accordance with a selection signal from a selection signal output circuit 6 (described later).
Here, it is assumed that the addition result of the adder 2 is input to the input terminal 113, the data FFH is input to the input terminal 114, and the data 00H is input to the input terminal 115.

Reference numeral 4 denotes a first logic circuit having three input terminals 103, 104, and 105, each of which has an adder 1
, The most significant bit of the γ1U data, the most significant bit of the γ2V data, and the carry signal output from the adder 1. Here, the first logic circuit 4 determines whether the addition result in the adder 1 is a positive value or a negative value based on each of the input signals described above.

That is, as shown in the truth table of FIG.
If the logic of the most significant bit of the input terminal 103 and the logic of the most significant bit of the input terminal 104 do not match, and the carry signal is not output from the adder 1 (the carry signal is “0”), the adder 1 Is determined to be a negative value, and "1" is output. When the carry signal is output (the carry signal is "1"), it is determined that the addition result in the adder 1 is a positive value. To output "0".

If the logic of the most significant bit of the input terminal 103 and the logic of the most significant bit of the input terminal 104 are both "1", the addition result in the adder 1 is a negative value regardless of the presence or absence of the carry signal. And outputs "1".
When both are "0", it is determined that the addition result in the adder 1 becomes a positive value regardless of the presence or absence of the carry signal, and "0" is output.

Reference numeral 5 denotes a second logic circuit, based on the output of the first logic circuit 4 and the carry signal of the adder 2, determines whether or not to output the addition result of the adder 2 as a final output. Make a decision. That is, as shown in the truth table of FIG. 4, when "1" is output from the first logic circuit 4 (the addition result in the adder 1 is determined to be negative), the carry signal is output from the adder 2. Then, the addition result in the adder 2 is output as a final output. If no carry signal is output from the adder 2, the addition result in the adder 2 is not output as the final output.

When "0" is output from the first logic circuit 4 (the addition result in the adder 1 is determined to be positive), and if the carry signal is not output from the adder 2,
The addition result in the adder 2 is output as a final output, and when the carry signal is output from the adder 2, the addition result in the adder 2 is not output as the final output.

The selection signal output circuit 6 includes inverters 7 and 8
And AND gates 9 and 10.
The carry signal of the adder 2 is input to one input terminal of each of the AND gates 9 and 10, and the AND gate 9
An inverted signal of the output of the second logic circuit 5 output from the inverter 8 is supplied to the other input terminal of the AND gate 1.
To the other input terminal of 0, an inverted signal of the carry signal of the adder 2 output from the inverter 7 is input.

Based on the carry signal of the adder 2 and the output of the second logic circuit 5, the selection signal output circuit 6 outputs the data input to either the input terminal 114 or 115 of the selector 3 to the final Output as output. That is, as shown in the truth table of FIG. 4, when “0” is output from the second logic circuit 5 and the carry signal is output from the adder 2, the input to the input terminal 114 of the selector 3 is performed. The output data FFH is output as the final output. If no carry signal is output, the input terminal 11 of the selector 3 is output.
The data 00H input to 5 is output as the final output.

Next, the operation of the above-described three-input adder will be described. When the Addition Result of Adder 1 has a Positive Value First, when the data input to adder 1 are both positive values, the highest order of the data input to input terminals 101 and 102 of adder 1 Since both bits are "0", the first
Logic circuit 4 outputs “0” regardless of the carry signal from the adder 1. When one of the data input to the adder 1 is a positive value (the most significant bit is “0”) and the other is a negative value (the most significant bit is “1”), When the carry signal is output, the addition result becomes a positive value. At this time, the first logic circuit 4 outputs “0”.

Then, the adder 2 adds the addition result of the adder 1 and the data input to the input terminal 107 of the adder 2 and outputs the result to the selector 3. Here, when the addition result in the adder 2 does not cause an overflow, the carry signal is not output, and the first logic circuit 4 outputs “0”, so that the second logic circuit 5 Outputs “1”. As a result, the output signal “1” from the second logic circuit 5 is output from the selection signal output circuit 6 to the selector 3, and “0” is output from both the AND gates 9 and 10. , Selector 3 is adder 2
Is output as the final output.

On the other hand, when the result of the addition in the adder 2 causes an overflow, the adder 2 outputs a carry signal. Further, since the first logic circuit 4 outputs “0”, the second logic circuit 5 outputs “0”. As a result, the selection signal output circuit 6 sends A
Since "1" is output from the ND gate 9 and "0" is output from the AND gate 10, the selector 3 has its input terminal 1
Then, the data FFH input to the terminal 14 is output as a final output.

As described above, when the addition result of the adder 1 is a positive value, the addition result of the adder 2 is output as a final output unless the addition result of the adder 2 causes an overflow. That is, in the three-input addition / subtraction circuit shown in FIG. 1, when it is determined that the addition result in the adder 1 is a positive value, the addition result is represented by a value represented by an absolute value (a numerical value range of 0 to 255). Therefore, when a carry signal is output from the adder 2, it is assumed that an overflow has occurred on the plus side, and the pasting process is performed.

When the Addition Result of Adder 1 is Negative First, if the data input to adder 1 are both negative values, the data input to input terminals 101 and 102 of adder 1 Are both "1", the first bit of
The logic circuit 4 outputs “1” regardless of the carry signal from the adder 1. When one of the data input to the adder 1 is a positive value (the most significant bit is “0”) and the other is a negative value (the most significant bit is “1”), When no carry signal is output,
The addition result in the adder 1 becomes a negative value. At this time, the first logic circuit 4 outputs "1".

The adder 2 adds the result of the addition performed by the adder 1 to the data input to the input terminal 107 of the adder 2 and outputs the result to the selector 3. Here, when the addition result in the adder 2 overflows,
Since the carry signal is output and the first logic circuit 4 outputs "1", the second logic circuit 5 outputs "1".
Is output. As a result, the output signal “1” from the second logic circuit 5 is output from the selection signal output circuit 6 to the selector 3, and “0” is output from both the AND gates 9 and 10. , The selector 3 outputs the addition result of the adder 2 as a final output.

On the other hand, if the addition result in the adder 2 does not cause an overflow, the carry signal is not output from the adder 2. Further, since the first logic circuit 4 outputs “1”, the second logic circuit 5 outputs “0”. As a result, “1” is output from the AND gate 10 to the selector 3 from the selection signal output circuit 6 and the AND gate 9 is output.
Is output from the selector 3, and the selector 3 outputs the data 00H input to the input terminal 115 as a final output.

As described above, when the addition result in the adder 1 becomes a negative value, the addition result of the adder 2 is output as the final output only when the addition result in the adder 2 overflows. . That is, 3 shown in FIG.
In the input addition / subtraction circuit, when it is determined that the addition result in the adder 1 is a negative value, the addition result is treated as a value represented by a two's complement (a numerical value range is -128 to 127). If the adder 2 does not output a carry signal, it is assumed that an overflow has occurred on the minus side, and the attaching process is performed.

[0037]

According to the three-input addition / subtraction circuit according to the first to fourth aspects of the present invention, the first and second data are stored in the first and second data.
After the addition by the adding means of
Is added by the second addition means, and it is determined whether the addition result by the first addition means is represented by an absolute value or a two's complement.
Based on the determination, the pasting process is performed on the addition result in the second addition means, so that addition and subtraction of a plurality of input data in which a value represented by a two's complement and a value represented by an absolute value are mixed are performed. In such a case, it is possible to output a finally obtained operation result as a value represented by an absolute value, and as a result, it is possible to improve the operation accuracy by one bit.

According to the three-input addition / subtraction circuit according to the fifth aspect of the present invention, since the bit length of data input to the three-input addition / subtraction circuit is unified, the arithmetic processing speed can be increased. It is suitable for image processing requiring high speed.

According to the three-input addition / subtraction circuit of the invention, since the input data is image data and a color difference signal, for example, conversion from YUV to RGB in a color space conversion technique is performed. Becomes possible.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a three-input addition / subtraction circuit according to an embodiment of the present invention.

FIG. 2 is a YU that outputs data to the 3-input addition / subtraction circuit.
FIG. 4 is an explanatory diagram for explaining input / output data of a V data conversion circuit.

FIG. 3 is a diagram showing a truth table showing an input / output relationship of a first logic circuit used in the three-input addition / subtraction circuit.

FIG. 4 is a diagram showing a truth table indicating an input / output relationship of a second logic circuit used in the three-input addition / subtraction circuit.

FIG. 5 is a block diagram illustrating a configuration of a conventional addition circuit that performs continuous addition.

[Explanation of symbols]

 1, 2 adder 3 selector 4, 5 logic circuit 6 selection signal output circuit 7, 8 inverter 9, 10 AND gate

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H04N 9/67 G06F 7/00 101U

Claims (6)

[Claims] 1. A three-input addition / subtraction circuit configured to add at least three pieces of data including data represented by a two's complement and configured in a plurality of bits, wherein: First adding means for adding the first data and the second data; an output of the first adding means; and a third data of at least three pieces of data composed of a plurality of bits. And a second addition means for adding the first and second addition means, and determines whether the addition result of the first addition means is a value represented by an absolute value or a value represented by a two's complement, A three-input addition / subtraction circuit, comprising: a pasting processing unit that performs a pasting process on the addition result of the second addition unit according to the result of the determination. 2. The three-input addition / subtraction circuit according to claim 1, wherein each of said first and second addition means outputs a carry signal when an addition result exceeds a maximum value which can be output. In the pasting processing means, the state of each most significant bit of the first and second data input to the first adding means and the carry signal from the first adding means The result of the addition by the first addition means is a value represented by an absolute value,
First determining means for determining whether the value is expressed in two's complement, based on a result of the determination by the first determining means, and a carry signal from the second adding means, Second determining means for determining whether the result of the addition by the adding means exceeds the upper limit or below the lower limit of the numerical value range of the operation result output by the three-input adding / subtracting circuit; and outputting from the three-input adding / subtracting circuit. Selecting means for receiving the maximum value and the minimum value of the numerical value and the addition result of the second adding means, and outputting any one value based on the result of the judgment by the second judging means. Characteristic 3-input addition / subtraction circuit. 3. The three-input addition / subtraction circuit according to claim 2, wherein the first determination unit determines that both of the most significant bits of the first and second data input to the first addition unit are “1”. "Or the first,
The most significant bits of the second data are “0” and “1”, respectively.
Alternatively, if the carry signal is "1" or "0" and no carry signal is output from the first adding means, it is determined that the addition result of the first adding means is a value expressed in two's complement. The most significant bits of the first and second data input to the first addition means are both "0", or
The most significant bits of the second data are “0” and “1”, respectively.
Alternatively, when the carry signal is "1" or "0" and the carry signal is output from the first adding means, it is determined that the addition result in the first adding means is a value expressed as an absolute value. Characteristic 3-input addition / subtraction circuit. 4. The three-input addition / subtraction circuit according to claim 2, wherein said second judging means is configured such that, by said first judging means, an addition result in said first adding means is represented by a two's complement number. If the carry signal is not output from the second adder, the result of the addition by the second adder is set to the lower limit of the numerical range of the operation result output by the three-input addition / subtraction circuit. It is determined that the value is less than the above, and the first determining means determines that the addition result in the first adding means is a value expressed as an absolute value,
When the carry signal is output from the second addition means, it is determined that the addition result in the second addition means exceeds the upper limit of the numerical range of the operation result output from the three-input addition / subtraction circuit. 3 input addition / subtraction circuit. 5. The three-input addition / subtraction circuit according to claim 1, wherein at least three pieces of data composed of a plurality of bits have the same bit length. Characteristic 3-input addition / subtraction circuit. 6. The three-input addition / subtraction circuit according to claim 1, wherein the first data, the second data, and the third data are image data. A three-input addition / subtraction circuit, which is a color difference signal.