JPH10104321A - Integrated circuit and its testing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To test an analog core circuit and a digital core circuit quickly in an integrated circuit where they coexist. SOLUTION: A plurality of analog boundary scan cells 105 that are arranged at the outer periphery of an analog core circuit 102 are connected in series by an analog boundary scan path 107. A plurality of digital boundary scan cells 106 that are arranged at the outer periphery of a digital core circuit 103 are connected in series by a digital boundary scan path 108. The analog and digital boundary scan paths 107 and 108 are mutually independent. When the analog and digital core circuits 102 and 103 are tested, the dedicated boundary scan paths 107 and 108 are selected, test control data or test data are shifted only by a plurality of exclusive boundary scan cells 105 or 106 and are set.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement of an integrated circuit in which an analog circuit and a digital circuit are mixed, and an improvement of a test method thereof.

[0002]

2. Description of the Related Art Efficiently performing a connection test between a plurality of circuits on a printed circuit board is a very high priority in the industry today. Under such circumstances, the IEEE (The Institute of Electrical and Elect
ronics Engineers, Inc.) adopted the boundary scanning technology as a standard in 1990 (IEEE Std 1149.1-1990). This standard is a useful technique in digital circuits. However, a printed circuit board actually used as a product contains a mixture of analog circuits and digital circuits. For this reason, connection between all circuits on the printed circuit board is performed using the boundary scan technology. Testing was difficult.

Therefore, conventionally, a circuit test technique (analog / digital) under an analog or digital / analog mixed signal is used.
Boundary scan), for example, ITC 1993
Paper 15.2 Structure and
Metrology foran Analog Te
stability Bus, Kennet P .;
Parker et al., And JP-A-6-347517. With this technology, it is possible to test the interconnection of devices under mixed analog and digital signals, and the analog discrete components existing between devices without the need for a test probe or by reducing the number of probes. It became.

A conventional integrated circuit device 601 using the analog boundary scan technique is shown in FIG. In the figure, the integrated circuit is an analog core circuit 602
A digital core circuit 603 connected to this circuit by a connection line 608; and a plurality of analog boundary lease cells 6 arranged around the analog core circuit 602.
05 and a plurality of digital boundary lease cells 606 arranged around the digital core circuit 603.
A single scan path 607 in which analog and digital boundary lease scans 605 and 606 are connected in series, and an analog test for sending a test analog signal (analog test data) to the analog boundary lease scan 605 A bus 611, a test controller 604, a data input terminal 609, an output terminal 610 for outputting a test result, and analog test terminals 612 and 61 for inputting and outputting the analog test data.
And 3.

The digital core circuit 603 sets digital test data from a data input terminal 609 to a digital boundary scan cell 606 via a scan path 607, and inputs the test data to the digital core circuit 603. On the other hand, regarding the analog core circuit 602, the analog core circuit 602
Is input from the data input terminal 609 to the analog boundary lease cancel 605 via the scan path 607,
As a result, the analog core circuit 602 is set to the test state, and under this test state, the analog test data is input from the analog test terminals 612 and 613 to the analog boundary lease cancel 605 via the analog test bus 611. The analog test data is input from the analog boundary lease cancel 605 to the analog core circuit 602.

[0006]

However, in the conventional integrated circuit, for example, when testing only the analog core circuit 602, the analog and digital boundary lease cancel cells 605 and 606 are added to the scan path 607.
, Digital boundary lease cancellation 60
It is necessary to shift and set the test control data to the analog boundary lease cancel 605 via 6. That is, the test control data is written into the analog boundary lease cancel (input cell and output cell) 605 of the analog core circuit 602, and the digital boundary lease cancel 6
06 (input cell and output cell) must always be written simultaneously.

As described above, even when only a part of the integrated circuit (for example, the analog core circuit 602) is to be tested, a scan chain other than the test target (the digital boundary lease cancel of the digital core circuit 603) is used. Since it is necessary to set the scan test data for 606), the test pattern becomes longer, the test pattern becomes longer, the test time becomes longer, and the automatic test data generation for the boundary scan is performed. There is a problem that the processing becomes complicated and a long time is required.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems. It is an object of the present invention to perform a test of each circuit in an integrated circuit in which an analog circuit and a digital circuit are mixed in a short and minimum length. It is to perform efficiently with a simple test pattern.

[0009]

In order to achieve the above object, the present invention employs a configuration in which analog boundary lease cancellation and digital boundary lease cancellation are connected in series by separate scan paths.

That is, the integrated circuit according to the first aspect of the present invention includes an analog circuit and a digital circuit, and a plurality of test circuits connected to the analog circuit and receiving test control data for setting the analog circuit to a test state. And a plurality of digital boundary lease cancelers connected to the digital circuit for inputting test data to the digital circuit or outputting test results from the digital circuit. An analog boundary scan path for connecting only cancellation in series and a digital boundary scan path for connecting only the digital boundary scan only in series are provided.

According to a second aspect of the present invention, in the integrated circuit of the first aspect, the integrated circuit is connected to a data input terminal, and the data input terminal is connected to one of the start points of the analog or digital boundary scan path. It is characterized by comprising a first switch and a second switch connected to the test result output terminal and connecting the test result output terminal to one end of the analog or digital boundary scan path.

According to a third aspect of the present invention, in the integrated circuit according to the second aspect, a test controller for testing the analog circuit and the digital circuit is provided, wherein the test controller includes the first and second switches. Is controlled.

According to a fourth aspect of the present invention, there is provided a test method for an integrated circuit, wherein a plurality of test circuits are connected to the analog circuit and the digital circuit, and test control data for setting the analog circuit to a test state is inputted. An integrated circuit comprising: a plurality of analog boundary lease cells; and a plurality of digital boundary cell cells connected to the digital circuit, for inputting test data to the digital circuit or outputting test results from the digital circuit. The test method, wherein the test control data or test data is shifted only to the analog or digital boundary lease cancel,
The analog circuit is set to a test state by using the test control data, or the digital circuit is operated by using the test data.

According to a fifth aspect of the present invention, in the integrated circuit of the first aspect, another analog circuit and test control data connected to the other analog circuit for setting the analog circuit to a test state. A plurality of other analog boundary lease cancellations,
And another analog boundary scan path for connecting only the other analog boundary lease scan in series.

According to a sixth aspect of the present invention, in the integrated circuit according to the fifth aspect, a switch connected to each of the analog boundary scan path and the other analog boundary scan path is provided. And another switch connected to each end of the other scan path and the other analog boundary scan path.

The invention according to claim 7 is the integrated circuit according to claim 6, further comprising a test controller for testing the analog circuit and the digital circuit, wherein the test controller controls the switch and other switches. It is characterized by doing.

According to an eighth aspect of the present invention, in the integrated circuit according to the first aspect, another digital circuit is connected to the other digital circuit, and test data is input to the digital circuit or the digital circuit receives the test data from the digital circuit. A plurality of other digital boundary lease scans for outputting test results and another digital boundary scan path connecting only the other digital boundary lease scans in series are provided.

According to a ninth aspect of the present invention, in the integrated circuit according to the eighth aspect, a switch connected to each of the digital boundary scan path and the other digital boundary scan path is provided, and a switch connected to the digital boundary scan path. And another switch connected to each terminal of the other scan path and the other digital boundary scan path.

According to a tenth aspect of the present invention, in the integrated circuit according to the ninth aspect, a test controller for testing the analog circuit and the digital circuit is provided,
The test controller controls the switch and other switches.

According to an eleventh aspect of the present invention, in the integrated circuit of the first aspect, a first boundary scan path connecting the analog boundary lease cells in series and the digital boundary lease cell are connected in series. The second and third boundary scan paths that are connected and divided into two, and the first and second boundary scan paths that are respectively arranged in parallel with the first, second, and third boundary scan paths.
And the third bypass, wherein the analog boundary scan path is configured by connecting the first boundary scan path and the second and third bypasses in series, and the digital boundary scan path And the second and third boundary scan paths and the first
And a bypass connected in series.

The invention according to claim 12 is the invention according to claim 11.
3. The integrated circuit according to claim 1, wherein a switch is connected to each end of said first boundary scan path and bypass and each end of said second boundary scan path and bypass; It has another switch to which each other end of the bypass is connected to each of the third boundary scan path and one end of the bypass.

The invention according to claim 13 is the invention according to claim 12.
The integrated circuit according to claim 1, further comprising a test controller for testing the analog circuit and the digital circuit, wherein the test controller controls the switch and other switches, and performs the first bounce when testing the analog circuit. One end of the boundary scan path is connected to one end of the second bypass, and the other end of the first boundary scan path is connected to one end of the third bypass. And one end of the second boundary scan path is connected to one end of the first bypass, and the other end of the first bypass is connected to one end of the third boundary scan path.

According to a fourteenth aspect, in the eleventh aspect,
In the integrated circuit as described above, at least one of the second and third boundary scan paths is further divided into a plurality of boundary scan paths arranged in parallel, wherein each of the boundary scan paths includes one of the second and third boundary scan paths. The digital boundary lease cancel of the sections is connected in series.

According to a fifteenth aspect of the present invention, in the integrated circuit according to the first aspect, a first boundary scan path connecting the digital boundary scan cells in series and the analog boundary scan cell are connected in series. The second and third boundary scan paths that are connected and divided into two, and the first and second boundary scan paths that are respectively arranged in parallel with the first, second, and third boundary scan paths.
And a third bypass, wherein the digital boundary scan path is configured by connecting the first boundary scan path and the second and third bypasses in series, and the analog boundary scan path And the second and third boundary scan paths and the first
And a bypass connected in series.

The invention according to claim 16 is the invention according to claim 15.
3. The integrated circuit according to claim 1, wherein a switch is connected to each end of said first boundary scan path and bypass and each end of said second boundary scan path and bypass; It has another switch to which each other end of the bypass is connected to each of the third boundary scan path and one end of the bypass.

The invention according to claim 17 is the invention according to claim 16.
The integrated circuit according to claim 1, further comprising: a test controller for testing the analog circuit and the digital circuit, wherein the test controller controls the switch and other switches so as to test the first bounce when testing the digital circuit. One end of the Dally scan path is connected to one end of the second bypass, and the other end of the first boundary scan path is connected to one end of the third bypass. And one end of the second boundary scan path is connected to one end of the first bypass, and the other end of the first bypass is connected to one end of the third boundary scan path.

[0027] The invention according to claim 18 is the invention according to claim 15.
In the integrated circuit as described above, at least one of the second and third boundary scan paths is further divided into a plurality of boundary scan paths arranged in parallel, wherein each of the boundary scan paths includes one of the second and third boundary scan paths. The analog boundary lease cancel of the sections is connected in series.

[0028] The invention according to claim 19 is the invention according to claim 11.
16. The integrated circuit according to claim 15, wherein a plurality of wirings connecting the analog circuit and the digital circuit, a scan cell arranged in the middle of the wiring, and a fourth bounce connecting the scan cells in series. And a fourth boundary scan path, wherein the fourth boundary scan path forms a part of the analog boundary scan path or the digital boundary scan path.

The invention according to claim 20 is the invention according to claim 19.
4. The integrated circuit according to claim 1, wherein a fourth bypass disposed in parallel with the fourth boundary scan path, and one end of one of the fourth boundary scan path and the bypass is connected to the first boundary scan path. Or a switch connected to the first bypass, and the other end of one of the fourth boundary scan path and the bypass connected to the third bypass.
And a switch connected to the boundary scan path or the third bypass.

[0030] The invention according to claim 21 is the invention according to claim 20.
The integrated circuit according to claim 1, further comprising a test controller for testing the analog circuit and the digital circuit, wherein the test controller controls the switch and other switches.

With the above arrangement, according to the present invention, even when an analog circuit and a digital circuit are mixed, an analog boundary scan path is selected and the analog boundary scan path is selected when testing the analog circuit. Since it is sufficient to shift and set the test control data only for lease cancellation, there is no need to shift and set the test data for digital boundary lease cancellation. Also, when testing a digital circuit, it is only necessary to select the digital boundary scan path, shift the test data only to the digital boundary lease cancel and set it. No need to shift and set. Therefore, the test pattern can be shortened to an optimum length, and a test of a part of the circuit can be efficiently performed in a short time.

[0032]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
1 shows an integrated circuit according to an embodiment.

In FIG. 1, reference numeral 101 denotes an integrated circuit, which includes a data input terminal 110 and a test result output terminal 11.
One. Inside the integrated circuit 101, an analog core circuit (analog circuit) 102 and a digital core circuit (digital circuit) 103 are provided, and these two core circuits 102 and 103 are mutually interconnected by a plurality (three in the figure). 109 are connected.

Around the analog core circuit 102,
A plurality of analog boundary lease cancels 105 are arranged. Each analog boundary lease cancel 1
Reference numeral 05 is connected to an input terminal or an output terminal of the analog core circuit 102. The analog boundary lease cancels 105 are connected in series by an analog boundary scan path 107.

Similarly, around the digital core circuit 103, a plurality of digital boundary lease cells 1
06 is arranged. Each digital boundary lease cancel 106 is connected to an input terminal or an output terminal of the digital core circuit 103. The digital boundary lease cancels 106 are connected in series by a digital boundary scan path 108. The analog and digital boundary scan path 10
7, 108 are independent of each other.

Reference numerals 112 and 113 denote switches, respectively.
One switch (first switch) 112 is connected to the analog and digital boundary scan paths 107,
108, and the other switch (second switch) 113 is connected to the other end.

Reference numerals 116 and 117 denote analog test terminals, and reference numeral 118 denotes an analog test bus. Analog test data is input to the plurality of analog boundary lease cells 105 via the analog test bus 118.

A test controller 104 tests the inside of the analog core circuit 102, the inside of the digital core circuit 103, and the connection between the two core circuits. The switches 112, 1 are connected to the test controller 104 via connection lines 114, 115, respectively.
13 is connected and the data input terminal 110,
Test result output terminal 111 and analog test terminal 1
16 and 117 are connected.

FIG. 2 shows the internal configuration of the test controller 104 and the switches 112 and 113.

Referring to FIG.
Has an instruction register 116, a control circuit 117, a bypass register 118, and a selector 119 therein. The instruction register 116 stores an instruction code input from the data input terminal 110. The control circuit 117 inputs the instruction code stored in the instruction register 116, a test clock signal and a test mode selection signal input from the outside, and, based on these, the plurality of analog boundary lease cancels 105. And a switching signal is output to the digital boundary lease cancel 106 via the signal line 121 to control the switching of these signals,
The switching signals are supplied to the switches 112 and 113 respectively on the signal line 1.
The signals are output via the terminals 22 and 123, and are switched.
The switches 112 and 113 receive the switching signal, and according to the signal value, the wirings 114 and 115 connected thereto.
Analog and digital boundary scan path 1
07 or 108. The bypass register 118 stores data input from the data input terminal 110 and outputs the stored data from the test result output terminal 111 via the selector 119 as it is. The selector 119 receives the switch 1 from the digital boundary scan path 108.
13 and the output of the two registers 116 and 118 received through the wiring 115 and under control of the control circuit 117, one of them is selected to output the test result. It is output from the terminal 111.

FIG. 3 shows the internal configuration of the digital boundary lease cancel 106. In this figure, the digital scan cell 106 has a digital signal input terminal 106a and an output terminal 106b, a scan-in terminal 106c, and a scan-out terminal 106d. The digital scan cell 106 is provided on the digital boundary scan path 108 at both scan terminals 106c and 106d.

Further, two flip-flops 130,
131 and two selectors 132 and 133 are provided. The selector 132 is connected to the test controller 104.
, And one of the digital signal input terminal 106a and the scan-in terminal 106c is connected to the preceding flip-flop 130 according to the signal value. The output side of the preceding flip-flop 130 is connected to the scan-out terminal 106d and the subsequent flip-flop 1
31 is connected to the input side. Another selector 133 is
Upon receiving another switching signal, the digital signal input terminal 106a and the flip-flop 131
Of the digital signal output terminal 10
6b. Therefore, during the scan operation, the test value input to the scan-in terminal 106c is set to the selector 1
At 32, the signal is input to the flip-flop 130 at the previous stage, and its output is output from the scan-out terminal 106d to the scan-in terminal of the next stage digital boundary scan cell. The digital signal stored in the subsequent flip-flop 131 is output to the digital signal output terminal 106 b by the selector 133, and is input to the digital core circuit 103 from this output terminal.

Analog Boundary Lease Cancel 105
Although the internal configuration of this is not shown, the configuration is based on IEEE (The
Institute of Electrical and ElectronicsEngineer
s, Inc.) (D15 16 May 1997) 65 and 58
Page. This configuration is proposed by the IEEE but is not standardized. Briefly describing this configuration, the scan-in terminal includes a scan-in terminal, a scan-out terminal, a plurality of flip-flops disposed between the two terminals, control logic, and a plurality of switches. A value is set to each of the flip-flops from a terminal, each set value is decoded by the control logic, and each switch is switched according to a result of the decoding to input an external signal to an analog core circuit,
The input is prohibited, or the input line of the analog core circuit 102 is set to the power supply voltage level (High) or the ground potential level (Low).

FIG. 4 shows a main configuration for transmitting and receiving signals between the analog core circuit 102 and the digital core circuit 103. In the figure, the analog core circuit 102 includes two selectors 140 and 141 and a DA converter 14.
2 is provided. The DA converter 142 receives a digital signal from the digital core circuit 103 via the wiring 109, and converts the received signal into an analog signal. Each of the selectors 140 and 141 has an analog core circuit 1
02 and the D / A converter 14
2 and receives the converted analog signal, and selects one of the signals. The selection is performed based on a switching signal input from the digital core circuit 103 via the wiring 109.

Although FIG. 4 shows only the internal configuration of the analog core circuit 102, the analog signal of the analog core circuit 102 is AD-converted, and the converted digital signal is used in the digital core circuit 103. Therefore,
Although not shown, the digital core circuit 103 employs a configuration similar to the above-described internal configuration of the analog core circuit 102.

The operation of the integrated circuit according to the present embodiment configured as described above will be described below with reference to FIG. In this description, a case where the analog core circuit 102 is tested will be described as an example.

First, an instruction code is set in the instruction register 116 of the test controller 104, and the digital core circuit 103 is separated from the analog core circuit 102 in a signal manner so that the analog core circuit 102 can be tested independently.

Next, another instruction code is input from the data input terminal 110 to change the instruction register 116 of the test controller 104. According to the instruction code of the instruction register 116, the control circuit 117 causes the analog boundary lease cancel 105 and the two switches 112, 11
5 to output a switching signal. As a result, in each analog boundary lease cancel 105, a mode is set in which the test control data is input from the scan-in terminal and output from the scan-out terminal via the flip-flop, and the switches 112 and 113 are set to the analog boundary lease. Switch to campus 107 side.

Subsequently, after externally inputting test control data to the data input terminal 110, the switch 11
2 and shift to each analog boundary lease cancel 105 via the analog boundary scan path 107 to set test conditions for the analog core circuit 102, thereby setting the analog core circuit 102 to a predetermined test state. . Subsequently, the analog test terminal 11
6 and 117, the analog test data is input to the plurality of analog boundary lease cancel units 105 via the analog test bus 118, and the analog test data is further input to the analog core lease cancel unit 105 via the analog boundary lease cancel units 105. The signal is input to the circuit 102 and the test of the analog core circuit 102 is performed.

Similarly, the following test conditions are set, and
By repeating the above operation, the analog core circuit 1
02 is performed a plurality of times (multiple pins).

As described above, in the present embodiment, when only one of the analog and digital core circuits 102 and 103 is tested, only the dedicated analog or digital boundary scan paths 107 and 108 are selected. The other digital or analog core circuit 10
There is no need to shift and set the test data or test control data to the digital or analog boundary lease cancels 106 and 105 dedicated to 3, 102. Therefore, the test pattern can be shortened, and the test can be performed efficiently in a short time.

(Second Embodiment) FIG. 5 shows a second embodiment of the present invention.
1 shows the configuration of the embodiment. In this embodiment, an integrated circuit 201 including two analog core circuits will be described.
The same portions as those of the integrated circuit according to the first embodiment shown in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

In FIG. 5, reference numeral 203 denotes a second analog core circuit (other analog circuit) provided separately from the analog core circuit (first analog core circuit) 102;
Denotes a plurality of other analog boundary lease cells arranged on the outer periphery of the second analog core circuit 203. These analog boundary lease cancellation 207
Are connected to an input terminal or an output terminal of the second analog core circuit 203, respectively.

The plurality of analog boundary lease scans 207 are connected to a second analog boundary scan path (another analog boundary scan path) 210.
Are connected in series. The second analog boundary scan path 210 is independent of the analog boundary scan path (first analog boundary scan path) 107. The analog boundary lease cancel 207 is connected to the analog test bus 118.

The first and second analog core circuits 10
2 and 203 are mutually connected by a signal line 209.

The switch 216 is connected to the switch 112 via a connection line 211, and the connection line 211 is connected to the first and second analog boundary scan paths 10.
7 and 210. The switch 216 is connected to the signal line 22 from the test controller 104.
It is controlled by a switching signal received via 0. The other switch 217 is connected to the switch 113 via a connection line 212, and connects this connection line 212 to the other end of one of the first and second analog boundary scan paths 107 and 210. The switch 217 is also controlled by a switching signal received from the test controller 104 via the signal line 221.

The operation of the integrated circuit according to this embodiment is the same as the operation of the integrated circuit according to the first embodiment, and a description thereof will be omitted.

In the present embodiment, even if two analog core circuits 102 and 203 are provided, two switches 21
6 and 217, one of the first and second analog boundary scan paths 107 and 210 can be selected. Therefore, when testing the first analog core circuit 102, the analog boundary lease cancel 105
When only the second analog core circuit 102 is tested using only the analog boundary lease cancel 207,
By using only the test control data, the test control data can be shifted to the analog core circuit, and the test condition of each analog circuit can be set efficiently in a short time.

(Modification of Second Embodiment) FIG. 6 shows a modification of the second embodiment. Although two analog core circuits are provided in the second embodiment, two digital core circuits are provided in the present embodiment.

In the figure, reference numeral 213 denotes a second digital core circuit (other digital circuit) provided separately from the digital core circuit (first digital core circuit) 103
A plurality of other digital boundary lease scans 214 are arranged on the outer periphery thereof, and these digital boundary lease scans 214 are connected to a second digital boundary scan path (another digital boundary scan path) 218. Are connected in series. The first and second digital core circuits 103 and 213 are connected to each other by a signal line 215.

The operation of the integrated circuit according to this embodiment is the same as the operation of the integrated circuit according to the first embodiment, and a description thereof will be omitted.

(Third Embodiment) FIG. 7 shows a third embodiment of the present invention.
1 shows a configuration of an integrated circuit 301 according to the embodiment. The same parts as those of the integrated circuit according to the first embodiment are denoted by the same reference numerals, and description thereof will be omitted.

In the same figure, reference numeral 309 denotes a first boundary scan path for serially connecting a plurality of analog boundary lease cells 105 arranged on the outer periphery of the analog core circuit 102, and 310 denotes the first boundary scan path. This is a first bypass arranged in parallel with the low scan path 309.

Reference numeral 307 denotes a second boundary scan path for serially connecting a plurality of digital boundary lease cancel cells 106 arranged on the left side of the digital core circuit 103 in the figure, and reference numeral 308 denotes the second boundary lease path. This is a second bypass arranged in parallel with the campus 307. Reference numeral 311 denotes a third boundary scan path for serially connecting a plurality of digital boundary scan cells 106 arranged on the right side of the digital core circuit 103 in the figure, and reference numeral 312 denotes the third boundary scan path 311. Is a third bypass arranged in parallel with the third bypass.

The switch 112 connects the wiring 114 to the second
To one end of one of the boundary scan path 307 and the second bypass 308. Switch 317
Connects the other end of one of the second boundary scan path 307 and the second bypass 308 to the first boundary scan path 309 and the first bypass 3
10 to one end. Another switch 318 is connected to the first boundary scan path 30.
9 and the other end of one of the first bypasses 310 is connected to one end of one of the third boundary scan path 311 and the third bypass 312. The switch 113 is connected to the third boundary scan path 311.
And the other end of one of the third bypasses 312 is connected to the wiring 115.

Next, the operation of the integrated circuit according to the present embodiment will be described with reference to FIG. The basic test procedure is
Since it is the same as the integrated circuit of the first embodiment, 4
Switching of scan paths by the switches 112, 113, 317, and 318 will be described.

As shown in FIG. 8A, when testing the analog core circuit 102, each switch is switched as shown. By this switching, as shown by the thick line, the wiring 114, the second bypass 308, the first boundary scan path 309, the third bypass 312, and the wiring 115 are connected in series, and the analog boundary scan path 330 is connected. Be composed.

As shown in FIG. 9B, when testing the digital core circuit 103, each switch is switched as shown. By this switching, as shown by the thick line, the wiring 114, the second boundary scan path 307, the first bypass 310, the third boundary scan path 311 and the wiring 115 are connected in series,
A digital boundary scan path 331 is configured.

When the tests of the analog and digital core circuits 102 and 103 are performed at the same time, as shown by the bold lines in FIG. 9C, the switches are switched as shown. By this switching, the wiring 114, the second boundary scan path 307, the first boundary scan path 309, and the third boundary scan path 311
And the wiring 115 are connected in series.

Therefore, in the present embodiment, when testing the analog core circuit 102, the plurality of digital boundary lease cells 106 are connected to the two bypasses 308,
11, the test control data can be shifted to only the plurality of analog boundary lease cancels 105 and the test control data can be set, so that the test pattern can be simplified and the test of the analog core circuit 102 can be simplified. It can be performed in a short time. The same applies to the test of the digital core circuit 103.

(Modification of Third Embodiment) Next, a third embodiment will be described.
FIG. 9 shows a modification of the embodiment. In the third embodiment, the third boundary scan path 311 is:
All the digital boundary lease cells 106 located on the right side of FIG. 7 of the digital core circuit 103 are connected in series. In the present embodiment, as shown in FIG.
Is divided into a plurality of (two in the figure) boundary scan paths 311a and 311b arranged in parallel. The one boundary scan path 311a connects a part of the plurality of digital boundary lease scans 106 in series, and the other boundary scan path 311b connects the remaining two. Are connected in series.

In the above configuration, the digital core circuit 103
In the test, the test data is shifted and set through only the necessary digital boundary lease cancel 106, bypassing some digital boundary lease cancels 106 in addition to all the analog boundary lease cancels 105. It is possible. Therefore, compared to the third embodiment, the digital core circuit 10
Test 3 can be performed even more efficiently.

In this modification, the third digital boundary scan path 311 is divided into two, but it goes without saying that the third digital boundary scan path 311 may be divided into three or more.

(Another Modification of Third Embodiment) FIG. 10
Shows another modification of the third embodiment. In the third embodiment, the analog core circuit 102 is disposed above and the digital core circuit 103 is disposed below. In the present modification, on the contrary, the digital core circuit 10 is disposed above.
3 has an analog core circuit 102 disposed below.

In this modified example, as shown in FIG. 10, a plurality of digital boundary lease cells 106 arranged on the outer periphery of the digital core circuit 103 are connected by a first boundary scan path 309, and the analog core circuit 1
The analog boundary lease cancel 105 disposed on the outer periphery of the second and third boundary scan paths 3
Connections are made at 07 and 311. The other configuration is the same as that of the third embodiment.
The description is omitted.

Therefore, in the present modification, as shown by the thick line in FIG. 11A, the digital boundary scan path 340 includes the wiring 114, the second bypass 308, the first boundary scan path 309, and the third boundary scan path 309. Bypass 31
2 and the wiring 115. In addition, as shown by a thick line in FIG.
41 includes a wiring 114, a second boundary scan path 307, a first bypass 310, a third boundary scan path 311 and a wiring 115. When the analog circuit 102 and the digital circuit 103 are tested at the same time, they are the same as those in the third embodiment shown in FIG.

Note that the integrated circuit shown in FIG.
The third boundary scan path 311 is divided into two boundary scan paths 311a and 311 as shown in FIG.
Needless to say, the image data may be divided into 11b or three or more boundary scan paths.

(Fourth Embodiment) FIG. 13 shows a configuration of an integrated circuit according to a fourth embodiment.

This embodiment is obtained by adding the following configuration to the integrated circuit of FIG. 7 showing the third embodiment.
That is, the analog core circuit 102 and the digital core circuit 1
A scan cell 428 is arranged on each of a plurality (three in the figure) of the wirings 109 connecting to the wirings 03. These scan cells 428 are connected in series by a fourth boundary scan path 411. Further, a fourth bypass 412 is arranged so as to bypass the fourth boundary scan path 411. One end of each of the fourth boundary scan path 411 and the fourth bypass 412 is connected to a switch 420, and the other end is connected to another switch 42.
Connected to 1.

The switch 420 connects one end of the fourth boundary scan path 411 or the bypass 412 to the first
Boundary scan path 309 or bypass 310
The switch 421 connects the other end of the fourth boundary scan path 411 or the bypass 412 to the third boundary scan path 311 or the bypass 31.
Connect to 2. The test controller 104 controls the switches 420 and 421.

Therefore, in this embodiment, when testing the analog core circuit 102, each switch 11
2, 113, 317, 420 and 421 are switched as shown in FIG. As a result, the analog boundary scan path 500 has the wiring 11 as shown by the thick line.
4, the second bypass 308, the first boundary scan path 309, the fourth boundary scan path 41
1, the third bypass 312 and the wiring 115 are connected in series.

When the digital core circuit 103 is tested, each of the switches 112, 113, 317,
420 and 421 are switched as shown in FIG.
As a result, the digital boundary scan path 501
Indicates that the wiring 114, the second boundary scan path 307, the first bypass 310, the fourth boundary scan path 411, the third boundary scan path 311 and the wiring 115 are connected in series as indicated by a thick line. It is composed.

Therefore, in the present embodiment, even in the case of an integrated circuit that transmits a signal from the analog core circuit 102 to the digital core circuit 103 via the wiring 109, the scan cell 428 disposed on each wiring 109 has an analog bounce. When the analog core circuit 102 is tested, the analog core circuit 102 and the digital core circuit 103 are completely separated from each other by using only the analog boundary scan path 500 when the analog core circuit 102 is tested. Can be. This effect can be obtained similarly when the digital core circuit 103 is tested.

If a test pattern for testing the digital core circuit 103 by itself already exists, the parallel input data of the test pattern is converted into serial input data, and this data is converted to the test data input terminal 1.
By inputting the value to 10, a functional test of the digital core circuit 103 alone can be easily performed.

[0086]

As described above, according to the integrated circuit and the test method of the invention according to the first to twenty-first aspects, in an integrated circuit in which an analog circuit and a digital circuit are mixed, only the analog circuit is tested. When you do
Select or configure an analog boundary scan path,
When testing only digital circuits, a digital boundary scan path was selected or configured, so test control data or test data was shifted to one analog or digital boundary scan cell corresponding to circuits other than the circuit under test. , Setting is unnecessary, and the test pattern can be made short and optimal length.
Testing of some circuits can be performed efficiently in a short time.

In particular, according to the integrated circuit of the present invention, at least one of the analog circuit and the digital circuit to be tested bypasses the boundary scan cell unnecessary to scan. Since an analog or digital boundary scan path is formed, a part of the test target circuit can be more efficiently tested with a short test pattern.

According to the integrated circuit of the present invention, when testing an analog circuit or a digital circuit, the circuit to be tested is completely separated from the digital or analog circuit other than the test object. Therefore, a functional test can be easily performed on the test target circuit alone.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating an internal configuration of a test controller and a switch included in the integrated circuit according to the embodiment;

FIG. 3 is a diagram showing an internal configuration of digital boundary lease cancellation according to the embodiment.

FIG. 4 is a diagram showing a main configuration inside the analog core circuit according to the embodiment;

FIG. 5 is a diagram showing a configuration of an integrated circuit according to a second embodiment of the present invention.

FIG. 6 is a diagram showing a modification of the integrated circuit of the embodiment.

FIG. 7 is a diagram illustrating a configuration of an integrated circuit according to a third embodiment of the present invention.

FIG. 8A is a diagram illustrating an operation in which an analog boundary scan path is formed in the integrated circuit according to the embodiment, FIG. 8B is a diagram illustrating an operation in which a digital boundary scan path is formed, and FIG. FIG. 9 is an explanatory diagram of an operation in which a boundary scan path is formed when an analog core circuit and a digital core circuit are tested simultaneously.

FIG. 9 is a diagram showing a configuration of an integrated circuit according to a modification of the embodiment.

FIG. 10 is a diagram showing a configuration of an integrated circuit according to another modification of the embodiment.

11A is an operation explanatory diagram in which an analog boundary scan path is formed in the integrated circuit according to the embodiment, FIG. 11B is an operation explanatory diagram in which a digital boundary scan path is formed, and FIG. FIG. 9 is an explanatory diagram of an operation in which a boundary scan path is formed when an analog core circuit and a digital core circuit are tested simultaneously.

FIG. 12 is a diagram showing a modification of the embodiment.

FIG. 13 is a diagram illustrating a configuration of an integrated circuit according to a fourth embodiment of the present invention.

FIG. 14A is a diagram illustrating an operation in which an analog boundary scan path is formed in the integrated circuit according to the embodiment, and FIG. 14B is a diagram illustrating an operation in which a digital boundary scan path is formed;

FIG. 15 is a diagram showing a configuration of a conventional integrated circuit.

[Explanation of symbols]

Reference Signs List 102 Analog core circuit (analog circuit) 103 Digital core circuit (digital circuit) 104 Test controller 105 Analog boundary lease cancellation 106 Digital boundary lease cancellation 107 Analog boundary scan path 108 Digital boundary scan path 109 Connection line (wiring) 110 Data input terminal 111 Test result output terminal 112 Switch (first switch) 113 Switch (second switch) 114, 115 Wiring 203 Second analog core circuit (other analog circuit) 207 Other analog boundary lease cancel 209 Connection line 210 second analog boundary scan path 216 switch 217 other switch 213 second digital core circuit (other digital circuit) 21 4 Digital boundary lease cancel 215 Connection line 307 Second boundary scan path 308 Second bypass 309 First boundary scan path 310 First bypass 311 Third boundary scan path 311a, 311b Arranged in parallel A plurality of boundary scan paths 312 third bypass 317 switch 318 other switches 330, 341 analog boundary scan path 331, 340 digital boundary scan path 411 fourth boundary scan path 412 fourth bypass 420, 421 Switch 428 Scan cell 500 Analog boundary scan path 501 Digital boundary scan path

Claims (21)

[Claims] 1. An analog circuit and a digital circuit, a plurality of analog boundary scan cells connected to the analog circuit and receiving test control data for setting the analog circuit to a test state; A plurality of digital boundary lease cancellers connected to the digital circuit for inputting test data or outputting test results from the digital circuit; and an analog boundary lease connecting only the analog boundary lease canceller in series. An integrated circuit comprising: a campus; and a digital boundary scan path for connecting only the digital boundary lease cancel in series. A first switch connected to a data input terminal and connecting the data input terminal to one of the start ends of the analog or digital boundary scan path; and a test result output terminal connected to the first switch. 2. The integrated circuit according to claim 1, further comprising: a second switch for connecting a result output terminal to one end of the analog or digital boundary scan path. 3. The integrated circuit according to claim 2, further comprising a test controller for testing the analog circuit and the digital circuit, wherein the test controller controls the first and second switches. 4. An analog circuit and a digital circuit; a plurality of analog boundary scan cells connected to the analog circuit and receiving test control data for setting the analog circuit to a test state; A test circuit for inputting test data to the digital circuit or outputting a test result from the digital circuit. Shifting test control data or test data only to the Dally scan, setting the analog circuit to a test state using the test control data, or operating the digital circuit using the test data. Circuit Strike method. 5. Another analog circuit, a plurality of other analog boundary scan cells connected to the other analog circuit and receiving test control data for setting the analog circuit to a test state; 2. The integrated circuit according to claim 1, further comprising another analog boundary scan path connecting only the other analog boundary lease scan in series. 6. A switch connected to each start end of the analog boundary scan path and the other analog boundary scan path, and a switch connected to each end of the analog boundary scan path and the other analog boundary scan path. 6. The integrated circuit according to claim 5, further comprising another switch. 7. The integrated circuit according to claim 6, further comprising a test controller for testing the analog circuit and the digital circuit, wherein the test controller controls the switch and other switches. 8. Another digital circuit and a plurality of other digital boundary scan cells connected to the other digital circuit for inputting test data to the digital circuit or outputting test results from the digital circuit. 2. The integrated circuit according to claim 1, further comprising: another digital boundary scan path for connecting only the other digital boundary lease cancel in series. 9. A switch connected to each start end of the digital boundary scan path and the other digital boundary scan path, and a switch connected to each end of the digital boundary scan path and the other digital boundary scan path. 9. A switch according to claim 8, further comprising:
An integrated circuit as described. 10. The integrated circuit according to claim 9, further comprising a test controller for testing the analog circuit and the digital circuit, wherein the test controller controls the switch and other switches. 11. A first boundary scan path that connects the analog boundary lease cells in series, and a second and third boundary that connects the digital boundary cell cells in series and is divided into two. And a first, second and third bypass respectively arranged in parallel with the first, second and third boundary scan paths, wherein the analog boundary scan path includes And the second and third bypasses are connected in series, and the digital boundary scan path includes the second and third bypasses.
2. The integrated circuit according to claim 1, wherein a third boundary scan path and the first bypass are connected in series. 12. A switch for connecting one end of each of the first boundary scan path and bypass to one end of each of the second boundary scan path and bypass, and the first boundary scan path and bypass. 12. The integrated circuit according to claim 11, further comprising: another switch connected to each of the other ends of the third boundary scan path and each of the third boundary scan path and the one end of the bypass. 13. A test controller for testing the analog circuit and the digital circuit, wherein the test controller controls the switch and other switches, and when testing the analog circuit, the first bounder One end of the low scan path is connected to one end of the second bypass, and the other end of the first boundary scan path is connected to one end of the third bypass. 13. An end of the boundary scan path is connected to one end of the first bypass, and the other end of the first bypass is connected to one end of the third boundary scan path. An integrated circuit as described. 14. At least one of the second and third boundary scan paths is further divided into a plurality of boundary scan paths arranged in parallel, and each of the boundary scan paths is partially 14. The integrated circuit according to claim 11, wherein the digital boundary lease cells are connected in series. 15. A first and a second boundary scan path for connecting the digital boundary lease scan in series, and a second and third boundary where the analog boundary lease scan is connected in series and divided into two. A first scan path, and a first, a second, and a third bypass arranged in parallel with the first, second, and third boundary scan paths, respectively, and the digital boundary scan path includes: 1
And the second and third bypasses are connected in series, and the analog boundary scan path includes the second and third boundary scan paths and the first bypass. 2. The integrated circuit according to claim 1, wherein the integrated circuit is connected in series. 16. A switch for connecting one end of each of the first boundary scan path and the bypass to each end of the second boundary scan path and the bypass, and the first boundary scan path and the bypass. 16. The integrated circuit according to claim 15, further comprising: another switch connected to each of the other ends of the third boundary scan path and each of the first and second ends of the third boundary scan path and the bypass. 17. A test controller for testing the analog circuit and the digital circuit, wherein the test controller controls the switch and other switches, and when testing the digital circuit, the first bounder One end of the low scan path is connected to one end of the second bypass, and the other end of the first boundary scan path is connected to one end of the third bypass. Is connected to one end of the first bypass, and the other end of the first bypass is connected to the third bypass.
17. The integrated circuit according to claim 16, wherein the integrated circuit is connected to one end of the boundary scan path. 18. At least one of the second and third boundary scan paths is further divided into a plurality of boundary scan paths arranged in parallel, and each of the boundary scan paths is partially 16. The integrated circuit according to claim 15, wherein the analog boundary lease cells are connected in series. 19. A plurality of wirings connecting the analog circuit and the digital circuit, a scan cell arranged in the middle of the wiring, and a fourth boundary scan path connecting the scan cells in series 16. The integrated circuit according to claim 11, wherein: the fourth boundary scan path forms a part of the analog boundary scan path or the digital boundary scan path. 20. A fourth bypass arranged in parallel with the fourth boundary scan path, and one end of one of the fourth boundary scan path and the bypass is connected to the first boundary scan path or A switch connected to a first bypass; and a switch connecting the other end of one of the fourth boundary scan path and the bypass to a third boundary scan path or a third bypass. 20. The integrated circuit according to claim 19, wherein: 21. The integrated circuit according to claim 20, further comprising a test controller for testing the analog circuit and the digital circuit, wherein the test controller controls the switch and other switches.