JPH1010205A - Test head of semiconductor test deuce - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a test head of semiconductor test device for testing a plurality of channel signals by multiplexing them with a constitution that the stray capacity of comparator side does not increase. SOLUTION: Each of signal channels of multiple pin output of tested device is multiplexed for testing with this test head by providing two switches in signal line of each channel and one grounded switch. In this case, all switches S12, S22 and S32 connected to the comparator side of each channel are provided near the comparator 40 to reduce the input capacity to this comparator 40.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a test head of a semiconductor test apparatus for multiplexing and testing a multi-pin output channel of a device under test.

[0002]

2. Description of the Related Art A semiconductor test apparatus for testing a semiconductor integrated circuit comprises a main body comprising a number of measurement units and a test head.

A configuration example of a conventional test head will be described with reference to FIGS. 2 and 3. FIG. As shown in FIG. 2, the main configuration of the test head is a test head housing 73.
, Pin cards 51 and 61, and a load motherboard 72.
, A device mounting board 71, switch units 10, 2
0 and 30, a multiplexer control 63, and a comparator 40.

The test head includes a main body of a semiconductor test apparatus (not shown) and a DUT of a device under test.
An interface for performing a desired test by coupling the signal between the test signal and the signal 70 is provided.

There are many types of test items for a semiconductor integrated circuit. For example, a test signal is applied to a DUT 70 of a device under test, and a signal of each channel output from each pin of the DUT 70 is compared by a comparator 40 with a comparison voltage. There is a level test for making a pass / fail judgment for Further, each pin output signal of the DUT 70 is converted to a digitizer (DG).
There is a test for processing as a digital signal according to T).

For example, when testing a driver IC of a liquid crystal display (LCD) having a multi-pin output of 256 to 320 pins as the DUT 70 of the device under test, each channel corresponding to each output pin is Providing the same number of comparators 40 is not preferable because it increases the size of the test apparatus and increases power consumption.

Therefore, switches 10 to 30 are provided on the load motherboard 72 for channels corresponding to the outputs of the plurality of pins 1 to 3 of the DUT 70 of the device under test, and the switches are sequentially controlled by the multiplexer control 63. The number of comparators 40 can be reduced by the multiplex system in which one channel is selected by switching.

As shown in FIG. 3 in which FIG. 2 is developed, a pin 1 from a DUT 70 mounted on a device mounting board 71 is shown.
~ The pin output of pin 3 is branched to switch sections 10, 2
0, 30 and the DGT of the digitizer unit in the main body are stored via a buffer.

In the multiplex switch units 10 to 30, three semiconductor switches are inserted for each switch unit, and switching is performed by the multiplexer control 63.

Here, in the switch section 10, semiconductor switches S11 and S12 are connected in series on a signal line to improve isolation for interrupting a signal when the switch is turned off. Can be dropped to the ground by the switch S13 so that the crosstalk in which a signal leaks between adjacent channels is reduced.

Next, control of semiconductor switch switching by the multiplexer control 63 will be described. For example, when the channel of the pin 1 is selected, S11 and S12 of the switch unit 10 are ON and S13 is OFF. On the other hand, in the switch section 20, S21 and S22 are OFF.
S23 is turned ON. Further, the switch unit 30 is connected to S3
1 and 32 are OFF, and S33 is ON. Thereafter, in the same manner, the signals are multiplexed from pin 2 to pin 3 sequentially, switched and output to the comparator 40.

In this example, the case where the number of the switch units 10 to 30 is three has been described. However, an increase in the number of output pins of the DUT 70 can be realized in a similar manner.

However, by multiplexing,
Although the number of comparators can be reduced, on the other hand, the wiring cables and the like viewed from the comparator side are connected to a plurality of channels, so that the stray capacitance increases.

The increase in the stray capacitance has the same result as when a capacitor is added to the input section when viewed from the side to which the test signal is applied, and the rise of the test signal to be applied to the device under test becomes slow. There is an inconvenience that high-speed tests with fast test cycles cannot be performed.

[0015]

As described above, a plurality of channels are multiplexed and the pass / fail judgment is made by the comparator in response to the increase in the number of pins of the device under test. There is a practical inconvenience that the test signal waveform becomes dull due to the increase. Therefore, the present invention has been made in view of such a problem, and an object of the present invention is to provide a structure in which the stray capacitance on the comparator side is not increased, and to provide a test head of a semiconductor test apparatus for multiplexing and testing signals of a plurality of channels. It is intended to provide.

[0016]

In order to achieve the above object, the invention according to claim 1 provides a multi-pin output signal channel of a device under test with two signal lines for each channel. In a test head of a semiconductor test apparatus for multiplexing and testing each channel, each switch connected to the comparator side of each channel is provided with a switch connected to the comparator. The gist of the present invention is a test head of a semiconductor test apparatus which is provided in the vicinity and has a reduced input capacitance of the comparator.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described in the following examples.

[0017]

An embodiment of the present invention will be described with reference to FIG. As shown in FIG. 1, the main configuration of the test head of the semiconductor test apparatus includes a test head housing 73, pin cards 51 and 61, a load motherboard 72, and a device mounting board 71, similarly to the conventional configuration. Is done. The test head serves as an interface for performing a desired operation by coupling signals between the semiconductor test apparatus (not shown) and the DUT 70 of the device under test.

For example, when the DUT 70 of the device under test has a multi-pin output of 256 to 320 pins, the DUT 70 of the device under test is switched to a channel corresponding to the output of a plurality of pins 1 to 3 of the DUT 70 as in the conventional case. The number of comparators 40 can be reduced as a multiplex system in which each switch section is sequentially switched to select one channel.

As shown in FIG. 3, in each switch of the multiplex system in this case, three switches are inserted for each channel in order to avoid crosstalk between the channel to be tested and other channels. This figure 1
In the example, S11 and S12 are connected in series to the pin 1, and the switch between the middle of the switches S11 and S12 and the ground is S13.

That is, two semiconductor switches are connected in series between each channel to improve isolation for blocking a signal when the switches are turned off, and furthermore, the intermediate point between the two switches can be dropped to the ground by the switches. Thus, crosstalk in which a signal leaks between adjacent channels is reduced.

In the present invention, S11 and S1
3 is provided on the pin card 52, and the switch S12 is provided near the input terminal of the comparator 40 on the pin card 62. Similarly, the switches S21 and S23 of pin 2 and the switches S31 and S33 of pin 3 are provided on the pin card 52, and the switches S22 and S32 are provided near the input end of the comparator 40 on the pin card 62. Also, the switch S1
2, the comparator 40 side of S22 and S32 is commonly connected.

The switching of the multiplex type semiconductor switch is controlled by a multiplexer control 63. For example, when selecting the channel of pin 1, S11 and S12 are ON and S13 is OFF.
Becomes On the other hand, in the channel of pin 2, S21 and S22 are OFF and S23 is ON. In the channel of pin 3, S31 and S32 are OFF and S33 is ON. Thereafter, in the same manner, the signals are multiplexed from pin 2 to pin 3 sequentially, switched and output to the comparator 40.

And, by multiplexing,
Although the number of comparators can be reduced as in the related art, in the present invention, the increase in the stray capacitance can be suppressed even though a plurality of channels are connected to the wiring cable and the like as viewed from the comparator side.

In this embodiment, the case where the number of channels switched by the multiplex system is three has been described. However, the number of channels can be increased or decreased according to the number of output pins of the DUT 70 in a similar manner. Also, switches S13 and S2
3. Although S32 is set to the ground, it may be a fixed potential instead of the ground.

[0025]

The present invention is embodied in the form described above and has the following effects. That is,
When a test is performed by multiplexing signals of a plurality of channels, the switches S12, S22, and S32 are provided near the comparator so that the stray capacitance on the comparator side does not increase. The effect of improving and enabling a high-speed test is great.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a test head according to the present invention.

FIG. 2 is a configuration diagram of a conventional test head.

FIG. 3 is a circuit diagram of a conventional test head.

[Explanation of symbols]

 10, 20, 30 Switch section 40 Comparator 51, 52, 61, 62 Pin card 63 Multiplexer control 71 Device mounting board 72 Load motherboard 73 Test head housing

Claims (1)

[Claims] 1. A signal line for multi-pin output of a device under test is provided with two switches on a signal line for each channel and one switch grounded between the switch and ground. A test head for a semiconductor test apparatus, wherein switches connected to the comparator side of each channel are provided near the comparator to reduce the input capacitance of the comparator. .