JPH0997795A - Bump forming method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily form a bump at a low cost by a method wherein a metal multilayered film is formed between a first electrode and an insulating layer of a second electrode when one of first electrodes is not coincident with a corresponding second electrode. SOLUTION: A solder bump 9A is formed on a pad 2A through the intermediary of a barrier metal layer 6A. When a pad 2B deviates positionally from the corresponding electrode of a wiring board due to a pitch difference, a barrier metal layer 6B is formed between the pad 2B and a bump forming position, and a solder bump 9B is formed on the barrier metal layer 6B at a position corresponding to a bump forming position. Therefore, a process where the pad 2B and a bump forming position are electrically connected together and another process where the barrier metal layer 6B for preventing an intermetallic compound from being produced is formed between the pad 2B and the corresponding electrode of the wiring board can be carried out in a batch.

Description

Detailed Description of the Invention

[0001]

[Table of Contents] The present invention will be described in the following order. Technical Field to which the Invention pertains Related Art Problems to be Solved by the Invention Means for Solving the Problems Embodiments of the Invention (FIGS. 1 to 5) Effects of the Invention

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bump forming method, for example, in forming a bump electrode (so-called bump) on each external electrode (pad) formed on the circuit surface of a semiconductor element of an IC (Integrated Circuit) chip. It is suitable to be applied to.

[0003]

2. Description of the Related Art In recent years, even though the degree of integration of one chip has improved, the chip size of the IC has become larger as the circuit scale of the IC has increased. Therefore, the size of the IC chip is made as small as possible by reducing the pitch of the pad formed on the IC chip.

Further, the pattern rule of the wiring board on which the IC chip is flip-chip mounted is becoming finer,
Different from the pattern rule of the wiring board and the pad pitch of the IC chip at the mass production level, the pattern rule of the wiring board is a pattern rule larger than the pad rule of the IC chip. For example, the pad pitch of an IC chip is about 80 [μm] at a level where mass production is possible, while the electrode pitch of a wiring board is about 150 [μm]. Further, the manufacturing cost of the wiring board increases as the pattern rule of the wiring board becomes finer. Therefore, in order to reduce the cost, it is desirable to make the pattern rule of the wiring board as large as possible.

[0005]

By the way, when an IC chip having a pad pitch less than the pattern rule of the wiring board is flip-chip mounted on the wiring board, each pad (usually Al (aluminum), A
1-Si (silicon), Al-Si-Cu (copper) or Al
There is a pitch difference between each of the electrodes and the corresponding electrode of the wiring board. As a method of eliminating this pitch difference, there is a method of rewiring the pad of the IC chip using Al, for example.

For example, when the pad A of the IC chip and the electrode B of the wiring board corresponding to the pad A do not match due to the pitch difference, the ICs of the electrodes A to B of the pad wiring board of the pad A of the pad A are matched. The pitch difference is eliminated by forming an Al layer using Al up to a corresponding predetermined position on the chip and forming a bump made of a predetermined bump material at the predetermined position.

According to this method, the pad A of the IC chip is
Since it is possible to eliminate the positional deviation due to the difference in pitch between the electrode and the corresponding electrode B on the wiring board and increase the pitch between the bumps, it is possible to increase the size and height of the bump. Therefore, the reliability of flip-chip mounting on the wiring board can be improved. By wiring from the pad A to the corresponding position on the IC chip of the electrode B, it is not necessary to reduce the electrode pitch of the wiring board, so that the manufacturing cost of the wiring board can be reduced.

In this method, however, a metal such as Al is used to form an Al layer from the pad A to a predetermined position on the IC chip of the electrode B, and then, between the pad A (Al) and the bump on the Al layer. Since it is necessary to form a metal multi-layer film (hereinafter referred to as a barrier metal layer) for preventing the formation of intermetallic compounds, a step of forming an Al layer from the pad A to a corresponding predetermined position on the IC chip of the electrode B , The step of forming a barrier metal layer on the Al layer is required, which complicates the bump forming step and raises the bump forming cost.

In particular, when the pattern rule of the wiring board is roughened to reduce the cost, a part or all of the pads formed on the IC chip are connected to the ICs of the electrodes corresponding to the wiring board from the respective pads. After forming an Al layer using Al up to the position in the chip, a barrier metal layer must be formed on the Al layer and bumps must be formed at the IC chip positions corresponding to the corresponding electrodes on the wiring board. The bump forming process becomes more complicated, and the bump forming cost is further increased.

The present invention has been made in consideration of the above points, and an object thereof is to propose a bump forming method capable of forming bumps easily and at low cost.

[0011]

In order to solve such a problem, in the present invention, in the first step, a bump forming object is formed so that an opening having a predetermined size is formed on each first electrode. A first insulating layer is formed on one surface and each first electrode, and in the second step, a metal multilayer film for preventing intermetallic compound formation is formed on each first electrode exposed in each opening. At the same time, if there is a first electrode that does not match the positional relationship with the corresponding second electrode among the first electrodes, depending on the positional relationship with the corresponding second electrode of the first electrode. A metal multilayer film is formed between the first electrode and a predetermined position of the second electrode corresponding to the first electrode on the first insulating layer, and the third step corresponds to the corresponding second electrode. Of the metal multi-layer film formed on the first electrode whose positional relationship with the electrode of As the opening made in of is formed, a second insulating layer formed on the metal multilayer film, to form a bump made of a predetermined bump material on each metal multilayer film.

Therefore, in this bump forming method, when there is a first electrode whose positional relationship with the corresponding second electrode is not the same among the respective first electrodes, the corresponding second electrode of the first electrode is present. A metal multilayer film is formed between the first electrode and a predetermined position on the first insulating layer of the second electrode corresponding to the first electrode according to the positional relationship with the first electrode. As a result, the first electrode whose positional relationship with the corresponding second electrode does not match the second electrode corresponding to the first electrode
Electrically connecting all the electrodes to a predetermined position on the first insulating layer and forming a metal multi-layer film between each first electrode and each corresponding second electrode. You can

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings.

1A to 1E show a bump forming method according to an embodiment of the present invention. First, as shown in FIG. 1A, a bump is formed on a circuit surface 1B of a silicon wafer 1A of an IC chip 1. Pads 2A and 2B made of, for example, Al-Si
A first passivation layer (insulating layer) 3 made of, for example, polyimide is formed on the circuit surface 1B so as to cover the peripheral end portion of.

In the case of this embodiment, it is assumed that the pad 2B is aligned with the corresponding electrode of the wiring board (not shown).

Subsequently, as shown in FIG. 1B, an opening 4A having a predetermined size is formed on each of the pads 2A and 2B.
And a second passivation layer 5 is formed on the first passivation layer 3 and the pads 2A and 2B so that 4B are formed. As the second passivation layer 5, for example, a material obtained by etching a non-photosensitive polyimide or a material obtained by exposing and developing a photosensitive polyimide is used.

Next, as shown in FIG. 1C, on the pad 2A exposed in the opening 4A, in order from the pad 2A side,
A barrier metal layer 6A made of Cr (chromium) / Cu (copper) / Au (gold) is formed so as to slightly overlap the peripheral edge portion of the second passivation layer 5, and the pad 2B exposed in the opening 4B and Between the pad 2B and a predetermined position on the second passivation layer 5 corresponding to an electrode of a wiring substrate (not shown) corresponding to the pad 2B (hereinafter, referred to as a bump formation position), Cr / Cu is formed. A barrier metal layer 6B made of / Au is formed. Here, the barrier metal layer 6
A and 6B are formed by using a plating method, a sputtering method, a vacuum evaporation method, or the like, and the barrier metal layer 6B is an IC.
It is supposed to be formed in the peripheral end direction of the chip 1.

Subsequently, as shown in FIG. 1D, a third passivation layer made of polyimide is formed so that openings 7A and 7B having a predetermined size are formed at the barrier metal layer 6A and the bump forming position, respectively. 8 is formed on the second passivation layer 5 and the barrier metal layer 6B.
Next, as shown in FIG. 1E, spherical solder bumps 9A and 9B are formed on the openings 7A and 7B, for example, by electrolytic plating or vacuum deposition.

Thus, as shown in FIG. 2, the solder solder bumps 9A are formed on the pad 2A through the barrier metal layer 6A.
It is possible to obtain an IC chip in which the solder bumps 9B electrically connected to the pad 2B through the barrier metal layer 6B are formed.

Here, when the solder bumps 9A and 9B are formed by the above-described bump forming method, as shown in FIG. 3, the second passivation layer 5 has a thickness of, for example,
If the openings 7A and 7B are formed to have a large thickness of 10 [μm] and the openings 7A and 7B have the same size, when the same amount of solder is supplied to the openings 7A and 7B, the solder bumps 9A are soldered. The height of the bump 9B from the back surface 1C of the wafer 1 is increased by the thickness h of the second passivation layer 5.

When the heights of the solder bumps differ as described above, the mounting yield at the time of flip-chip mounting the IC chip on the wiring board decreases. Therefore, in this embodiment, the solder bumps 9A and 9A are formed by the following method.
The height difference of B is eliminated.

That is, the first method is a method corresponding to the case where the openings 7A and 7B formed in the third passivation layer 8 are formed to have the same size, or the amount of solder supplied to the opening 7B is reduced or By increasing the amount of solder supplied to the opening 7A, the solder bumps 9A and 9B are formed to have the same height from the back surface 1C of the wafer 1. This can be realized, for example, by changing the area of the opening of the resist or the like when performing electrolytic plating or vacuum deposition.

The second method is a method in which the amount of solder supplied to the openings 7A and 7B is the same, and the height of the solder bumps 9A and 9B from the back surface 1C of the wafer 1 is the same. In consideration of the above, the size of the opening 7B is made larger than the opening 7A, or the size of the opening 7A is made smaller than the opening 7B. The third method executes both the first method and the second method described above. Therefore, when forming the solder bumps 9A and 9B, by performing the above-mentioned first, second or third method,
It is possible to form the solder bumps 9A and 9B to be formed at the same height from the back surface 1C of the wafer 1A, and to avoid a decrease in yield when mounting the wiring board.

In the above structure, in this bump forming method, the solder bump 9A is formed on the pad 2A via the barrier metal layer 6A, and the pad 2B is displaced from the corresponding electrode on the wiring substrate due to the pitch difference. In contrast, the barrier metal layer 6B is formed between the pad 2B and the bump forming position, and the solder bump 9B is formed at a position corresponding to the bump forming position on the barrier metal layer 6B.

Therefore, in this bump forming method, the pad 2
Performing collectively the step of electrically connecting B and the bump forming position and the step of forming the barrier metal layer 6B for preventing the formation of the intermetallic compound between the pad 2B and the corresponding electrode of the wiring board. You can Further, as in the conventional case, an Al layer or an Al-Si layer for electrically connecting the pad A and a predetermined position in the IC chip of the electrode B is formed on the passivation layer.
Compared to the adhesion between the Si layer and the passivation layer, in this embodiment, the barrier metal layer 6B is formed directly on the passivation layer 5, and the passivation layers 5 and 8 are made of polyimide. It is possible to further improve the adhesion between the passivation layers 5 and 8 and the reliability of the IC chip. Further, by using copper for the barrier metal layer 6B,
Wiring can be performed with a low wiring resistance value as compared with the conventional case where an Al layer is used for pad wiring.

According to the above structure, the barrier metal layer 6B
To electrically connect the pad 2B and the bump forming position to form the solder bump 9B at the bump forming position of the barrier metal layer 6B, thereby electrically connecting the pad 2B and the bump forming position. Process and pad 2
A step of forming a barrier metal layer 6B for preventing the formation of an intermetallic compound between B and the corresponding electrode of the wiring board can be collectively performed, and thus a bump forming method capable of forming bumps easily and at low cost is provided. Can be realized.

In the above embodiment, the pad 2B is used.
The case where the solder bumps 9B for soldering are formed in the peripheral edge direction of the IC chip 1 has been described, but the present invention is not limited to this.
As shown in FIG. 4, the solder bumps 9B for the pads 2B are formed in the central direction of the IC chip 1, and the bumps are formed at predetermined positions of the IC chip 1 according to the positions of the electrodes corresponding to the wiring board of the bumps 2B. can do.

In the above embodiment, the pad 2B is used.
However, the present invention is not limited to this, and as shown in FIG. 5, the pads formed on the IC chip 1 and the wiring substrate correspond to each other. Depending on the positional relationship with each electrode, bumps are formed at a predetermined position on the IC chip corresponding to each electrode on the wiring board of each pad by using the above-described bump forming method for part or all of the pad. can do.

Further, in the above embodiment, in order to make the solder bumps 9A and 9B have the same height from the back surface 1C of the wafer 1 when the second passivation layer 5 is thick. The case where the first, second and third methods are applied has been described above. However, the present invention is not limited to this, and a chip according to the thickness of a wiring layer and an interlayer insulating film, such as an IC chip having multi-layer wiring, is not limited to this. Even if the heights of the surfaces are different, the heights of the solder bumps can be adjusted by using the above-described first, second, and third methods according to the height of each place.

Further, in the above-described embodiment, Cr / Cu / A is used as the metal multilayer film in order from the pads 2A and 2B.
The case where the barrier metal layers 6A and 6B made of u are formed has been described, but the present invention is not limited to this, and Ti (titanium) / Cu / Au (gold), in order from the pads 2A and 2B,
Cr / Ni (Nickel) / Au, Ti / Ni / Au, C
r / Ni / Cu / Au, Ti / Ni / Cu / Au, Ti
The barrier metal layers 6A and 6B made of N (titanium nitride) / Ti / Cu / Au or the like may be formed as a metal multilayer film.

Further, in the above-described embodiment, the case where the Al-Si pads are used as the pads 2A and 2B of the IC chip 1 has been described, but the present invention is not limited to this and Al and Al- are used as the pads 2A and 2B. Si-Cu, Cr
Alternatively, Ti or the like may be used. Pads 2A and 2B
When Al-Si or Al-Si-Cu is used as
As the combination of the pads 2A and 2B and the barrier metal layer 6, the first metal layer of the barrier metal layer 6 is most suitable for improving the reliability with the barrier metal layer 6 of Cr, Ti or TiN.

Further, in the above-mentioned embodiment, the case where the bumps 9A and 9B are formed by using the solder as the bump material has been described, but the present invention is not limited to this, and the bump material other than the solder is applied as the bump material. obtain. Furthermore, in the above-mentioned embodiment, the case where the present invention is applied to the IC chip 1 as the bump formation target is described, but the present invention is not limited to this, and for example, on each electrode of a printed wiring board or other electronic components. It can also be applied to the case where bumps are formed on.

Further, in the above embodiment, the passivation layers 3, 5 and 9 made of polyimide as the insulating layer.
However, the present invention is not limited to this, and a passivation layer made of silicon oxide, silicon nitride or the like may be formed as the passivation layers 3, 5 and 9.

[0034]

As described above, according to the present invention, the first surface of the bump forming object and the first electrode are formed so that the opening having a predetermined size is formed on each of the first electrodes. 1 insulating layer is formed, a metal multilayer film for preventing the formation of intermetallic compounds is formed on each first electrode exposed in each opening, and a metal second layer corresponding to the second electrode corresponding to each first electrode is formed. When there is a first electrode whose positional relationship does not match, the second electrode corresponding to the first electrode and the second electrode corresponding to the second electrode corresponding to the first electrode Of the metal multilayer film formed on the first electrode, the metal multilayer film being formed between the electrode and a predetermined position on the first insulating layer, and the positional relationship with the corresponding second electrode does not match. A second insulating layer is formed on the metal multilayer film so that an opening having a predetermined size is formed on the position. By forming a bump made of a predetermined bump material on each metal multilayer film, the first electrode corresponding to the first electrode from the first electrode whose positional relationship with the corresponding second electrode does not match. A step of electrically connecting the second electrode to a predetermined position on the first insulating layer;
The step of forming the metal multi-layer film between the electrodes and the corresponding second electrodes can be collectively performed, and thus the bump forming method capable of forming the bumps easily and at low cost can be realized.

[Brief description of drawings]

FIG. 1 is a sectional view for explaining a bump forming method according to an embodiment of the present invention.

FIG. 2 is a perspective view showing a part of an IC chip with solder bumps formed according to an embodiment of the present invention.

FIG. 3 is a sectional view for explaining a difference in height of formed solder bumps.

FIG. 4 is a perspective view for explaining a solder bump forming position according to another embodiment.

FIG. 5 is a perspective view showing a part of an IC chip with solder bumps in which the bump forming method according to the embodiment is applied to all pads.

[Explanation of symbols]

1 ... IC chip, 2 ... Pad, 3, 5, 8 ... Passivation layer, 4, 7 ... Opening, 6 ... Barrier metal layer, 9 ... Solder bump.

Claims (4)

[Claims] 1. A bump forming method for forming a bump to be mounted on a substrate on which second electrodes corresponding to a plurality of first electrodes formed on one surface of a bump forming object are formed. One surface of the bump formation target and each of the first to third openings are formed so as to form an opening having a predetermined size on the electrode of
A first step of forming a first insulating layer on the electrodes, and forming a metal multilayer film for preventing the formation of intermetallic compounds on each of the first electrodes exposed in each of the openings, and When there is the first electrode whose positional relationship with the corresponding second electrode does not match among the one electrodes, depending on the positional relationship with the corresponding second electrode of the first electrode,
A second step of forming the metal multilayer film between the first electrode and a predetermined position of the second electrode corresponding to the first electrode on the first insulating layer; On the metal multi-layer film, an opening having a predetermined size is formed on the predetermined position of the metal multi-layer film formed on the first electrode that does not have a positional relationship with the second electrode. And a third step of forming a second insulating layer, and a fourth step of forming a bump made of a predetermined bump material on each of the metal multilayer films described above. 2. Each of the first electrodes is made of aluminum-silicon or aluminum-silicon-copper, and the metal layer on the first electrode side of the metal multilayer film is made of chromium, titanium or titanium nitride. The bump forming method according to claim 1, wherein: 3. In the first step and the third step, if the supply amount of the predetermined bump material supplied onto the metal multilayer film in the fourth step is the same, the fourth step is performed.
2. The opening is formed in a size such that the height of each of the bumps formed in the step of the other surface facing the one surface of the bump forming object is the same. The method for forming bumps according to. 4. In the fourth step, when the openings are formed to have the same size in the first and third steps, the other surface of each of the bumps facing one surface of the bump formation target object. The bump forming method according to claim 1, wherein the predetermined bump material is supplied onto each of the metal multilayer films so that the heights from the bumps are the same.