JPH0993123A - Phase difference detection circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow the phase difference detection circuit to realize the phase synchronization circuit whose phase locking is not unlocked even a large input phase difference and to realize the angular modulation phase synchronization circuit in which an angular modulation frequency is set higher and the amplitude is more increased. SOLUTION: The phase difference detection circuit is provided with a phase comparator 1 receiving a reference phase 5a and a reference phase 6a to provide the output of a phase error signal 1a proportional to an input phase difference being a difference of the both, an integration circuit 2 integrating the phase error signal 1a to provide the output of a control voltage 2a, a phase difference offset conversion circuit 43 detecting a discontinuous point of the voltage 2a based on the change in the voltage level of the control voltage 2a to output a prescribed offset voltage 3a, and an offset addition circuit 4 inputting the control voltage 2a and the offset voltage 3a and outputting an offset addition control voltage 4a adding the voltages.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase difference detection circuit,
For example, it relates to a phase difference detection circuit applied to a phase synchronization circuit or an angle modulation phase synchronization circuit.

[0002]

2. Description of the Related Art The structure of a conventional phase difference detection circuit will be described with reference to FIG. As shown in FIG. 7, the phase difference detection circuit includes a phase comparator 1 and an integration circuit 2. The phase comparator 1 inputs the standard phase 5a and the reference phase 6a, and the phase error signal 1a proportional to the input phase difference 1b which is the difference between them.
Is output. The integrating circuit 2 integrates the phase error signal 1a and outputs a control voltage 2a.

Input / output characteristics of the phase difference detection circuit will be described with reference to FIG. In FIG. 8, the horizontal axis represents the input phase difference 1b and the vertical axis represents the control voltage 2a. Input phase difference 1b is + πrad to −πrad
In the section, the control voltage 2a is proportional to the input phase difference 1b. It becomes a discontinuity at the point of + πrad, and it becomes + πrad
When it exceeds, it becomes a proportional characteristic, and it becomes a discontinuous point at the point of + 3πrad, and when it exceeds + 3πrad, it becomes a proportional characteristic.
Repeats the discontinuity point and the proportional characteristic.

As shown in FIG. 8, the input / output characteristics are point-symmetric with respect to the origin, and a discontinuity point is obtained at -πrad, a discontinuity point is obtained at -3πrad, and this is repeated.
The distance between the discontinuous points on the horizontal axis is 2πrad, but it is a general value and may be an arbitrary value.

According to FIG. 8, when the input phase difference 1b exceeds ± πrad, the input / output characteristic in the prior art shown in FIG. Is limited to ± π rad.

As one application example of the phase difference detection circuit, the configuration of the phase synchronization circuit will be described with reference to FIG. In FIG. 9, 5 is an independent oscillator, and 6 is a slave oscillator. The other components are the same as those in FIG. 7.

The independent oscillator 5 oscillates at a constant frequency and gives the phase comparator 1 a reference phase 5a. The slave oscillator 6 has its oscillation frequency controlled by the control voltage 2a, and the reference signal 6
It outputs a and inputs it to the phase comparator 1. The control voltage 2a is a voltage for controlling the reference phase 5a output from the independent oscillator 5 and the reference phase 6a output from the dependent oscillator 6 to be equal.

In such a phase locked loop circuit, the input phase difference 1b of the phase comparator 1 is ± πra due to disturbance, for example.
When d is exceeded, the phase difference cannot be detected and the slave oscillator 6 is out of phase synchronization with the independent oscillator 5.

As another application example of the phase difference detection circuit, the configuration of an angle modulation phase synchronization circuit will be described with reference to FIG. Reference numeral 7 is an angle modulation oscillator, 8 is an adder circuit, and the other components are the same as those in FIG.

The angle modulation oscillator 7 outputs a modulation signal 7a. The adder circuit 8 adds the modulated signal 7a and the control voltage 2a, and outputs an added signal 8a. The operations of the other components are the same as those described with reference to FIG.

The slave oscillator 6 is subjected to frequency modulation or phase modulation angle modulation by the addition signal 8a. In such an angle modulation phase locked loop circuit, when the modulation frequency or the amplitude of the modulation signal 7a increases, the slave oscillator 6
The reference phase 6a output by the signal fluctuates more greatly. As a result, when the input phase difference 1b of the phase comparator 1 exceeds ± πrad, the phase synchronization is lost.

[0012]

The phase difference detection circuit in the prior art has a problem that the detectable input phase difference 1b is limited to ± π rad. Therefore, when the input phase difference 1b of the phase comparator 1 exceeds ± π rad due to disturbance in the phase locked loop circuit to which this phase difference detection circuit is applied, the phase difference cannot be detected and the dependent oscillator 6 becomes the independent oscillator 5
And the problem that the phase synchronization was lost occurred. Further, in the angle modulation phase synchronization circuit to which this phase difference detection circuit is applied, when the modulation frequency of the modulation signal 7a becomes high or the amplitude becomes large and the reference phase 6a output from the slave oscillator 6 fluctuates more, phase comparison is performed. Input phase difference 1b of unit 1 is ±
There was a problem that phase synchronization was lost beyond πrad.

An object of the present invention is to provide a phase difference detection circuit in which a detectable input phase difference is increased, whereby a phase synchronization circuit that does not lose phase synchronization with a large input phase difference and an angle modulation circuit. An object of the present invention is to provide an angle modulation phase locked loop circuit capable of higher frequency and larger amplitude.

[0014]

In order to achieve this object, the present invention inputs a standard phase 5a and a reference phase 6a and outputs a phase error signal 1a proportional to the input phase difference which is the difference between them. The phase comparator 1, the integration circuit 2 that integrates the phase error signal 1a and outputs the control voltage 2a, the discontinuity point of the voltage 2a is detected from the change in the voltage level of the control voltage 2a, and the predetermined offset voltage 3a is detected. Phase difference that outputs
It has an offset conversion circuit 3 and an offset addition circuit 4 which inputs a control voltage 2a and an offset voltage 3a and outputs an offset addition control voltage 4a obtained by adding these voltages.

Further, according to the present invention, the phase comparator 1 which inputs the standard phase 5a and the reference phase 6a and outputs the phase error signal 1a proportional to the input phase difference which is the difference between the two,
An integrator circuit 2 that integrates the phase error signal 1a and outputs a control voltage 2a, and a discontinuity point of the voltage 2a is detected from the change in the voltage level of the control voltage 2a, and a predetermined offset voltage 3
The phase difference / offset conversion circuit 3 that outputs a, the offset addition circuit 4 that inputs the control voltage 2a and the offset voltage 3a, and outputs the offset addition control voltage 4a obtained by adding these voltages, and the offset addition control voltage 4a. Reference phase 6a whose oscillation frequency is controlled by input
And a dependent oscillator 6 for outputting

Further, according to the present invention, the reference phase 5a
And a reference phase 6a, and a phase comparator 1 for outputting a phase error signal 1a proportional to an input phase difference which is a difference between the two.
An integrating circuit 2 that integrates the phase error signal 1a and outputs a control voltage 2a; and a position that outputs a predetermined offset voltage 3a by detecting a discontinuity point of the voltage 2a from the change in the voltage level of the control voltage 2a. A phase difference / offset conversion circuit 3, an offset addition circuit 4 for inputting the control voltage 2a and the offset voltage 3a and outputting an offset addition control voltage 4a obtained by adding these voltages, and an angle modulation oscillator 7 for outputting a modulation signal 7a. , The offset addition control voltage 4a and the modulation signal 7a are input, and an addition circuit 8 which outputs the addition signal 8a obtained by adding them, and a sub-phase 6a which outputs the reference phase 6a which is subjected to angle modulation of frequency modulation or phase modulation by the addition signal 8a And an oscillator 6.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Next, embodiments of the phase difference detection circuit according to the present invention will be described in detail. FIG. 1 is a functional block diagram showing the configuration of a phase difference detection circuit according to the present invention. In FIG. 1, 3 is a phase difference / offset conversion circuit, 4 is an offset addition circuit, and other components are the same as those in FIG.

The phase comparator 1 includes a standard phase 5a and a reference phase 6
a is input, and the phase error signal 1a proportional to the input phase difference, which is the difference between the two, is output. The integrating circuit 2 has a phase error signal 1
The control voltage 2a is output by integrating a. The phase difference / offset conversion circuit 3 detects a discontinuity point from the control voltage 2a,
The offset voltage 3a is output. Offset addition circuit 4
Adds the control voltage 2a and the offset voltage 3a and outputs the offset added control voltage 4a.

3 (a) to 3 (c) are input / output characteristic diagrams showing waveforms at respective points in FIG. That is, FIG. 3A shows the output 2a of the integrating circuit 2, FIG. 3B shows the output 3a of the phase difference / offset converting circuit 3, and FIG. 3C shows the output 4a of the offset adding circuit 4. ing.

In FIG. 3, V1 is the value of the control voltage 2a when the input phase difference 1b is πrad, and V2 is the input phase difference 1b is πrad.
Of the control voltage 2a when the input phase difference 1b is slightly larger than zero, V3 is the value of the control voltage 2a when
Is the control voltage 2 when the input phase difference 1b is slightly smaller than zero.
The value of a, V5 is the value of the control voltage 2a when the input phase difference 1b is less than -πrad, and V6 is the input phase difference 1b is -πra.
It is the value of the control voltage 2a at the time of d.

The phase difference / offset conversion circuit 3 is shown in FIG.
The value of the control voltage 2a shown in (a) is in the range of V1 to V2,
Whether or not it is in the range of V3 to zero, the range of zero to V4, or the range of V5 to V6 is detected, and the waveform shown in FIG. 3B is output.

That is, the phase difference / offset conversion circuit 3
Detects that it has entered the range of V1 to V2 and then detects that it has entered the range of V5 to V6,
The voltage of 1 to V6 is output in the positive direction to the offset voltage 3a. Following this, when the range of V1 to V2 is detected and the range of V5 to V6 is detected, V1 to V
Offset voltage 3a with voltage up to 6 as positive direction
Is cumulatively added to and output. If the range of V4 to zero or the range of zero to V3 is detected before the range of V5 to V6 is detected and the range of V1 to V2 is detected, the value of the offset voltage 3a is not changed.

Further, after detecting that the voltage has entered the range of V5 to V6 and thereafter detecting that the voltage has entered the range of V1 to V2, the voltage components of V1 to V6 are output in the negative direction to the offset voltage 3a. . After this, V
When the range of 5 to V6 is detected and the range of V1 to V2 is detected, the voltage components from V1 to V6 are set to the negative direction, and the offset voltage 3a is cumulatively subtracted and output. If the range from V3 to zero or the range from zero to V4 is detected before the range from V1 to V2 is detected and the range from V5 to V6 is detected, the value of the offset voltage 3a is not changed.

The offset adding circuit 4 adds the control voltage 2a and the offset voltage 3a to add the offset adding control voltage 4
Output a. By the above processing, the discontinuity point shown in FIG. 8 is eliminated, and the proportional characteristic shown in FIG. 3C is obtained.

FIG. 2 shows a configuration example of the phase difference / offset conversion circuit 3. 2, 31 is a detection circuit, 32 is a discrimination circuit,
33 is a constant voltage source, and 34 is a voltage inverting circuit.

In the detection circuit 31, the value of the control voltage 2a is V1.
To V2, V3 to zero, zero to V4, and V5 to V6 are detected, and a detection signal 31a is output according to each value. The determination circuit 32 determines whether to add, subtract, or do nothing to the offset voltage 3a according to the temporal change of the detection signal 31a, and outputs it to the determination signal 32a.

The constant voltage source 33 outputs a voltage component from V1 to V6 in the positive direction as a constant voltage output 33a. The voltage inversion circuit 34 outputs the constant voltage output 3 if the determination signal 32a is added.
3a is output as it is to the offset voltage 3a. If the determination signal 32a is subtraction, the constant voltage output 33a is inverted and output as the offset voltage 3a. If there is no discrimination signal 32a, the voltage inverting circuit 34 outputs the offset voltage 3a as zero.

An application example of the embodiment of the phase difference detection circuit shown in FIG. 1 will be described with reference to FIG. FIG. 4 is an application of the input / output characteristics of FIG. 3, and FIGS. 4 (a) to 4 (c) correspond to FIGS. 3 (a) to 3 (c).

When the phase difference / offset conversion circuit 3 detects the range of V1 to V2 and then the range of V5 to V6, it outputs the voltage component of V1 to V6 to the offset voltage 3a in the positive direction, and the accumulated number of times. Memorize +1 times. After that, when the range of V1 to V2 is detected and the range of V5 to V6 is detected, the cumulative number of times is +1 time.
The offset voltage 3a is output in the negative direction corresponding to the voltage from V1 to V6, and the cumulative number is -1.

When the range from V1 to V2 is detected after the range from V5 to V6 is detected, the offset voltage 3a becomes V1.
To V6 are output in the negative direction, and -1 is stored as the cumulative number. After this, V5 to V6
When the range of V1 and V2 is detected, the accumulated number of times is -1, so the offset voltage 3a is changed from V1 to V2.
The voltage up to 6 is output in the positive direction, and the cumulative number is set to +1. Through the above processing, the offset voltage 3a
Has the waveform shown in FIG. 4B, and as a result, the offset addition control voltage 4a has a characteristic in which a discontinuity is provided at ± 3π rad as shown in FIG. 4C. Therefore, the input phase difference 1b
Can be increased from ± πrad to ± 3πrad.

If the number of accumulations is ± 2, the input phase difference is 1
b increases to ± 5πrad, increases to ± 7πrad if it is ± 3 times, and generally, the input phase difference 1b increases to ± (2n + 1) πrad when the number of accumulations is ± n times.

Next, an embodiment in which the phase difference detection circuit according to the present embodiment is applied to a phase synchronization circuit will be described with reference to FIG. The constituent elements shown in the figure are the same as the constituent elements shown in FIGS. 1 and 9. That is, the phase synchronization circuit inputs the reference phase 5a of the independent oscillator 5 to the phase comparator 1, and the reference phase 6a of the dependent oscillator 6 whose oscillation frequency is controlled by the offset addition control voltage 4a of the offset addition circuit 4 is the phase. The configuration is such that feedback is input to the comparator 1.

The independent oscillator 5 oscillates at a constant frequency and gives the phase comparator 1 a reference phase 5a. The slave oscillator 6 has its oscillation frequency controlled by the offset addition control voltage 4a, and outputs the reference phase 6a and inputs it to the phase comparator 1. The offset addition control voltage 4a is supplied to the independent oscillator 5
Of the reference phase 6a output from the slave oscillator 6 is equal to the reference phase 5a output from the slave oscillator 6.

In the phase locked loop circuit of this embodiment,
For example, the input phase difference of the phase comparator 1 is ± π due to disturbance.
Even if it exceeds rad, the phase difference can be detected because of the input / output characteristics shown in FIG. 3 or 4, and the phase synchronization between the independent oscillator 5 and the dependent oscillator 6 can be maintained.

Next, FIG. 6 shows an embodiment in which the phase difference detection circuit of this embodiment is applied to an angle modulation phase locked loop circuit.
This will be described below. The components are the same as those shown in FIG. 1 and FIG. 10, and the phase difference detection circuit shown in FIG.
The configuration is such that the independent oscillator 5, the angle modulation oscillator 7, the addition circuit 8 and the slave oscillator 6 shown in FIG. 10 are added.

The slave oscillator 6 receives an angle modulation of frequency modulation or phase modulation by the modulation signal 7a. When the modulation frequency of the modulation signal 7a increases or the amplitude increases,
The reference phase 6a output from the dependent oscillator 6 fluctuates more greatly, the phase difference can be detected, and the phase synchronization is not lost.
Therefore, the modulation frequency of the angle modulation can be increased or the amplitude can be increased.

[0037]

According to the phase difference detecting circuit of the present invention, since the detectable input phase difference can be widened, a larger phase difference can be detected. Therefore, if the phase difference detection circuit according to the present invention is applied to the phase synchronization circuit, the conventional problem that the phase synchronization is lost due to the limitation of the input phase difference even if a disturbance occurs can be solved. Further, if the phase difference detection circuit according to the present invention is applied to the angle modulation phase synchronization circuit, even if the modulation frequency of the angle modulation is made higher or the amplitude is made larger, the phase synchronization cannot be lost due to the limitation of the input phase difference. You can expect an effect.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of a phase difference detection circuit according to the present invention.

FIG. 2 is a block diagram showing a configuration example of a phase difference offset / conversion circuit of the phase difference detection circuit of FIG.

3 is a waveform diagram showing input / output characteristics in the phase difference detection circuit of FIG.

FIG. 4 is a waveform diagram showing an application example of input / output characteristics in the phase difference detection circuit of FIG.

5 is a configuration diagram showing an embodiment when the phase difference detection circuit of FIG. 1 is applied to a phase synchronization circuit.

FIG. 6 is a configuration diagram showing an embodiment when the phase difference detection circuit of FIG. 1 is applied to an angle modulation phase locked loop circuit.

FIG. 7 is a configuration diagram showing a phase difference detection circuit in a conventional technique.

8 is a waveform diagram showing the input / output characteristics of the phase difference detection circuit in the conventional technique of FIG.

9 is a configuration diagram when the phase difference detection circuit in the conventional technique of FIG. 7 is applied to a phase synchronization circuit.

10 is a configuration diagram when the phase difference detection circuit in the conventional technique of FIG. 7 is applied to an angle modulation phase locked loop circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Phase comparator 2 Integration circuit 3 Phase difference / offset conversion circuit 4 Offset addition circuit 5 Independent oscillator 6 Slave oscillator 7 Angle modulation oscillator 8 Addition circuit

Claims (3)

[Claims] 1. A phase error signal which is input with a reference phase (5a) and a reference phase (6a) and is proportional to an input phase difference which is a difference between the two.
The phase comparator (1) that outputs (1a), the integration circuit (2) that integrates the phase error signal (1a) and outputs the control voltage (2a), and the change in the voltage level of the control voltage (2a) The phase difference / offset conversion circuit (3) that detects the discontinuity point of this voltage (2a) and outputs the predetermined offset voltage (3a), the control voltage (2a) and the offset voltage (3a) are input, A phase difference detection circuit comprising: an offset addition circuit (4) that outputs an offset addition control voltage (4a) obtained by adding these voltages. 2. A phase error signal which is input with a reference phase (5a) and a reference phase (6a) and is proportional to an input phase difference which is a difference between the two.
The phase comparator (1) that outputs (1a), the integration circuit (2) that integrates the phase error signal (1a) and outputs the control voltage (2a), and the change in the voltage level of the control voltage (2a) The phase difference / offset conversion circuit (3) that detects the discontinuity point of this voltage (2a) and outputs the predetermined offset voltage (3a), the control voltage (2a) and the offset voltage (3a) are input, An offset addition circuit (4) that outputs the offset addition control voltage (4a) that adds these voltages, and a subordinate that outputs the reference phase (6a) whose oscillation frequency is controlled by inputting the offset addition control voltage (4a) A phase-locked loop having an oscillator (6). 3. A phase error signal which is input with a reference phase (5a) and a reference phase (6a) and is proportional to an input phase difference which is a difference between the two.
The phase comparator (1) that outputs (1a), the integration circuit (2) that integrates the phase error signal (1a) and outputs the control voltage (2a), and the change in the voltage level of the control voltage (2a) The phase difference / offset conversion circuit (3) that detects the discontinuity point of this voltage (2a) and outputs the predetermined offset voltage (3a), the control voltage (2a) and the offset voltage (3a) are input, The offset addition circuit (4) that outputs the offset addition control voltage (4a) that adds these voltages, the angle modulation oscillator (7) that outputs the modulation signal (7a), the offset addition control voltage (4a), and the modulation signal ( Adder circuit that inputs 7a) and outputs the added signal (8a)
An angle modulation phase locked loop circuit comprising: (8); and a slave oscillator (6) that outputs a reference phase (6a) that undergoes angle modulation such as frequency modulation or phase modulation by the addition signal (8a).