JPH0991970A - Nondestructive ferroelectric memory and driving method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a nondestructive ferroelectric memory suitable for high integration in which nondestructive read-out can be realized without causing any interference with nonselected memory cell at the time of reading or writing data by employing a feedback circuit added with a capacitor, a sense circuit, etc. SOLUTION: Information in a memory cell 1 is erased by a first pulse having voltage Ve higher than a coercive voltage Vc. Information is written in by a second pulse having voltage Vw, the absolute value thereof is lower than the voltage Ve of reverse polarity. A feedback circuit system added with a capacitor for reading out a small ΔC/C without requiring any voltage variation on the data line and a sense circuit combining comparative read-out with a reference dummy cell 11 comprising a ferroelectric are additionally provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state recording device used in an electronic circuit, and more particularly to a non-destructive ferroelectric memory using a ferroelectric thin film.

[0002]

2. Description of the Related Art Generally, with the development of computers and image devices, there is a demand for high-density and high-performance memory devices. As a conventional memory device, an external memory device such as a magnetic tape, a floppy disk, a magneto-optical disk,
Alternatively, semiconductor memory, that is, DRAM, SRA
M, EPROM, EEPROM, flash memory, etc. have been used.

When the multimedia and the computer are integrated, the memory device is firstly nonvolatile, secondly driven at high speed and low voltage, and thirdly a driveless solid-state memory. Higher performance and more compact memory is needed. However, there are cases in which the technology of the conventional recording device cannot cope.

As a memory device which meets this requirement, for example,
USP 4,873,664 (S. Sheffield Eaton Jr., C
Ferroelectric memories such as those disclosed in Olorado Springs, CO).

The structure of this ferroelectric memory is shown in FIG.

Ferroelectric thin film capacitor 3 in memory cell 301
Reference numeral 02 denotes a switching element, which has a structure in which the DRAM type storage capacitance driven by the FET 303 is changed to a ferroelectric capacitance. The driving to the memory cell is connected to the word line 304, the plate line 305, and the bit line 308, and the reading is performed by the sense amplifier 30.
Do at 7.

In this configuration, the sense amplifier 307 is made of Si.
Since it is formed on the device, the degree of integration and the cost are about the same as those of semiconductor memory DRAM and FLASH memory, which is inconvenient when, for example, a card of several 100 Mbytes is manufactured.

On the other hand, USP 5,060,191
32 is a method in which, as shown in FIG. 32, a simple matrix structure is formed with a ferroelectric material 313 and signals are detected by the read drive circuits 314 and 315.

A major problem of a memory configured with such a simple matrix is interference between a selected cell and a non-selected cell because cells are arranged adjacent to each other. For example, when the voltage Va is applied when a certain cell is selected and writing / reading is performed, the voltage is also applied to the non-selected cells that are not selected. In particular, as the number of cells increases, Va / 2 is applied to the non-selected cells connected to the input / output side electrode lines of the selected cells.

Therefore, in the above-mentioned USP 5,060,191, with respect to the applied voltage Va to the selected cell, for example,
The write operation is performed by devising that Va / 3 is applied to the non-selected cells. Further, in the reading, a low impedance voltage is read to cut noise from the non-selected cells. However, when the voltage Va required for reversing the polarization of the selected cell is applied at the time of writing, the polarization state of the non-selected cell is destroyed even if the voltage of Va / 3 is applied many times.

USP 5,140,548 (CJ B
rennan), it is considered that both the space charge layer and the neutral region exist in the ferroelectric body to create the capacitance-voltage characteristic as shown in FIG. 33. In the written state of 321, a voltage Vb equal to or lower than a certain coercive voltage Vth is applied, and the capacitance is measured by the AC signal superimposed on it. The capacitance is 322 in the "1" state and the capacitance of 323 in the "0" state. Is obtained, and the difference is "1"
This is to determine “0”. Therefore, after writing, V has a time constant longer than the relaxation time of space charge.
By applying the read voltage of b and applying an AC waveform having a frequency component faster than the relaxation time, it is possible to read without changing the polarization state.

[0012]

However, as a problem of the above-mentioned prior art, in the configuration shown in FIG. 31, the combination with a semiconductor is relatively easy to realize, but it is a Si device, that is, a switching device. Element and FE
By using T, the degree of integration and cost are the same as DRAM.

Further, the ferroelectric memory having the simple matrix structure shown in FIG. 32 does not specifically disclose the guarantee against polarization breakdown of the ferroelectric cell at the time of writing.

The method of using the capacitance change shown in FIG. 33, when applied to a simple matrix, has the same problem that occurred in the device shown in FIG. 32 at the time of writing. Even in reading, if reading is performed with good S / N, the reading voltage Vb must be applied to a certain level, and the application of a large number of times also causes a change in polarization, which does not result in nondestructive reading. .

Therefore, the present invention has non-interference with non-selected memory cells at the time of writing / reading information, enables non-destructive reading, and is suitable for large-scale non-destructive ferroelectric memory. The purpose is to provide.

[0016]

In order to achieve the above object, the present invention uses a memory cell that stores information according to the spontaneous polarization state of a ferroelectric thin film sandwiched by a pair of electrodes. In a dielectric memory, a first terminal for applying a first pulse for erasing stored information having a voltage Ve larger than a coercive voltage Vc of the ferroelectric thin film to the storage cell, and the storage cell to the storage cell. A second terminal for applying a second pulse for writing information having a voltage Vw having an absolute value smaller than Ve having a polarity opposite to the applied voltage Ve, and an absolute value larger than the voltage Ve to the memory cell. A third terminal for applying a third pulse for nondestructively reading the memory information, which has the same value or a small voltage Vr of positive or negative, and the first to third Select one of the terminals And a first selection switch means having a feedback capacitance connected to the output side of the memory cell via a first changeover switch means whose one end is grounded. The first amplifier is composed of a differential amplifier and a ferroelectric thin film equivalent to the memory cell, stores the same information as the information stored in the memory cell, and is connected to a reference dummy cell for arbitrarily performing comparison reading. To fourth to sixth terminals to which a pulse signal equivalent to the third to third pulse signals is applied, and a second selection switch for selecting any one of the fourth to sixth terminals and applying it to the reference dummy cell Means, and a second differential amplifier having a feedback capacitance connected to the output side of the reference dummy cell via a second changeover switch means whose one end is grounded, and which is fed back to the output. , The first differential amplifier and the second differential amplifier A third differential amplifier that outputs a difference from the differential amplifier, and the first and second selection switch means and the first and second changeover switch means enable the storage cell and Information is erased / written / read to / from the reference dummy cell, the memory cell and the reference dummy cell store information in a partially polarized state, and non-destructive by applying a third pulse of the voltage Vr. Provided is a non-destructive type ferroelectric memory for reading memory information selectively.

In the non-destructive ferroelectric memory having the above-mentioned structure, the voltage Ve larger than the coercive voltage Vth of the ferroelectric thin film is generated in the first polarization state of the two states of spontaneous polarization. Is applied to polarize, and then a second pulse having a voltage Vw having a polarity opposite to the applied voltage Ve is applied to polarize the domain having the polarization in the first direction. Information is stored in a partially polarized state in which domains having a second polarization in the opposite direction to the first direction are mixed. This state appears as a difference in capacitance, but when reading with a read voltage, since the capacitance ratio ΔC / C is small, it is necessary to amplify. At this time, considering the temperature dependence and the data retention time dependence of C, it is necessary to perform comparative reading by a reference cell using a ferroelectric capacitor. Here, the non-destructive large-capacity memory can be realized by the sense circuit in which the small-capacity ΔC / C can be read out without changing the voltage of the data line and the comparative reading of the reference cell and the capacitance-added feedback circuit are combined.

[0018]

DETAILED DESCRIPTION OF THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings.

First, a nondestructive ferroelectric memory device according to the present invention and a driving method thereof will be described with reference to FIGS.

First, as shown in FIG. 2A, for example,
One end of a ferroelectric memory cell 1 in which a ferroelectric thin film is sandwiched by electrodes such as platinum is connected via a selection switch 2 to an erase pulse input terminal 3, a write pulse input terminal 4, and a read pulse input terminal 5. Connected to. The other end of the ferroelectric memory cell 1 is connected to the input terminals of the discharge changeover switch 6 and the differential amplifier 7, one end of which is grounded to the reference potential,
A feedback capacitance element (capacitor) 8 is connected to the differential amplifier 7 so that the output is fed back.

Data writing and data reading by the signals shown in FIG. 2B in the ferroelectric memory device having the above structure will be described.

The principle of data writing and data reading of this ferroelectric memory device is basically the same as in Japanese Patent Application Nos. 6-22545 and 7-9992 proposed by the present applicant.

In this configuration, first, the erase pulse Ve
Delete the recorded data by entering
With respect to the memory cell 1, the polarization set in the first (downward) direction is set to the “0” state. After that, predetermined data is written with the write pulse Vw.

Here, the potential of the write pulse Vw needs to be smaller than the absolute value of the potential of the erase pulse Ve. The written cell has a first (downward) polarization state and a second
It has both polarization states reversed in the (upward) direction, that is, a partially polarized region. That is, the partial polarization is a polarization state having a mixed state of polarization in the first direction and polarization in the second direction. This state is set to "1" and is shown in FIG. The memory is retained in "0" state and "1"
The information is recorded in a state, and this information is not easily deteriorated by temperature or holding for a long time. Further, there is a difference in the zero bias state between "1" and "0", and _assuming that the "1" state is C _s1 and the "0" state is C _s0 , C _s0 > C _s1 and the difference (C _s0
It has been confirmed that -C _s1 ) / C _s0 is about 20%.

Then, the read pulse V shown in FIG.
Data is read by r. This read pulse Vr
Is read non-destructively and erase pulse V
It is desirable that it is smaller in absolute value than the potential of e, and preferably smaller than the write pulse Vw. The read pulse Vr may have either polarity.

By applying the read pulse Vr, 1
It has been confirmed that non-destructive reading can be performed approximately 10 ¹⁰ to 1 × 10 ¹² times. By the writing / reading method using these pulses, the ferroelectric film is sandwiched between the upper electrodes arranged in parallel and the lower electrodes arranged in parallel so as to be substantially orthogonal to the upper electrodes, and sandwiched between the upper and lower electrodes. A memory structure having a simple matrix structure in which the closed region becomes one memory cell is possible. Moreover, it has been confirmed that the voltage applied to the non-selected cells is small at the time of writing the data, and the recorded data is not destroyed.

Therefore, the above-mentioned writing / reading method suggests the realization of a non-volatile memory which can be highly integrated.

Here, any ferroelectric material may be used as long as it has spontaneous polarization. Pb (Zr, Ti) O ₃ , (Pb, La) (Zr, T having a perovskite structure
i) O ₃ , PbTiO ₃ , BaTiO _{3 and the} like are common. It may also be a layered compound. For example, SrBi
₂ Ta ₂ O ₉ , SrBi ₂ Nb ₂ O ₉ , SrBi ₄ Ti
₄ O ₁₂ , SrBi ₂ (Ta, Nb) ₂ O ₉ , Bi ₄ Ti
₃ O ₁₂ etc. Further, the film forming method may be a sol-gel method, an organic metal method, a sputtering method, a MOCVD method, or the like. Further, the film thickness can be scaled according to the actual driving voltage.

FIG. 1 shows a circuit configuration of a non-destructive ferroelectric memory device as a first embodiment and will be described. Although this configuration is conceptual, the memory device having the configuration shown in FIG. 2 is symmetrically arranged in a pair with the differential amplifier 10 as the center, and the dummy cell 11 made of a ferroelectric memory cell is used. One end is connected to the erase pulse input terminal 13, the write pulse input terminal 14, and the read pulse input terminal 15 via the selection switch 12. The other end of the dummy cell 11 is connected to the input terminals of the discharge switch 16 and the differential amplifier 17 whose one end is grounded to the reference potential, and the feedback capacitor element 18 feeds back the output to the differential amplifier 17. It is connected to the. Further, in the figure, the reference potential (ground) indicated by the arrow is a predetermined reference potential and does not need to be zero potential.

The operation of the ferroelectric memory device shown in FIG. 1 will be described in detail with reference to FIG.

FIG. 3A is a simple matrix ferroelectric memory device in which a plurality of memory cells 1 are arranged in a matrix and the first line 19 and the second line 20 are connected.

By applying the voltage Ve shown in FIG. 3B to this ferroelectric memory device, the recorded data is erased at once.

Similarly, FIG. 3C is a diagram for explaining a data writing method. Data writing is 1/3
Using the driving method, the voltage Vw is applied to the first line 19 of the selected cell of the X line group as shown in FIG. 3C, and the voltage 1 / 3Vw is applied to the first line 19 of the non-selected cell. Is applied, and 0V is applied to the selected cell of the Y line group, and the unselected cell 2 /
As with applying a voltage of 3 Vw, destruction and deterioration during data writing are prevented. Regarding this destruction and deterioration, it has been confirmed that even if the memory cell of 1 mat is integrated up to 1 Gbit by the driving method described above using the PZT thin film, the cell is not destroyed at the time of data writing.

Similarly, FIG. 3E is a diagram for explaining the data reading method. Here, the first lines 19 other than the first line 19a of the selection line are grounded. The second line 20 other than the second line 20a of the selected data line is grounded.

At this time, the second line 20a of the selected data line is grounded in advance by the discharge switch 6, and the feedback capacitor 8 is connected to the differential amplifier 7. Here, in the differential amplifier 7, since one side of the differential input is grounded, the input impedance is held at “0” by virtual grounding,
The potential of the second line 20a of the selected data lines is not boosted. Therefore, no charge is injected from the non-selected cells. Therefore, non-interfering data reading can be performed, and
The output Vout is determined by the ratio of the memory cell capacitance Cs and the feedback capacitance Cr because it is the differential amplifier 7 that feeds back the capacitance 8. Therefore, V _out = − (C _s / C _r ) ^* V _r Here, in the “0” and “1” states, V _{c0 and} V _c1 are V _c1 = − (C _s1 / C _r ) ^* V _r V _c0 = − ( C _s0 / C _r ) ^* V _r This state is shown in FIG. In this figure, the vertical axis is drawn with -V for easy understanding. Here, it is possible to read information from V _c1 > V _c0 , but this difference is as small as 20%, and because this C _s0 changes with temperature, holding time, etc.,
Use a dummy cell.

Next, as shown in FIG. 4, one input terminal side of the third differential amplifier 10 is composed of the first differential amplifier 7, the memory cell 1 and the capacitor 8 shown in FIG. Configuration and
The second differential amplifier 17 and the dummy cell 1 are connected to the other input terminal.
1 and a capacitor 18 are connected.

With this configuration, the voltage at point A in the figure is -V
_Where V _c0 <V _ref <V _c1 with V as the vertical axis.
Select _ref . That is, the dummy cell 11 is selected so that V _ref is in this range. For example, if the feedback capacitances of the capacitor 8 and the capacitor 18 are accurately matched, the area of the dummy cell 11 is changed to match V _ref . For example,
If Vr is the same,

[Equation 1]

This means that the area of the dummy cell is increased by (C _s1 -C _s0 ) / 2C _s0 times that of the memory cell. For example, for a 1 μm cell, (C _s1 −C _s0 ) / C
_{When s0} is 20%, (C _s1 -C _s0 ) / 2C _s0 is 10%, which corresponds to a cell of 1.1 μm □.

In this case, data writing in the dummy cell is not performed. Since a 1/5 stepper is used in the actual device production, the relative processing accuracy can be determined. 1 μm
It is assumed to be 0.01 μm in the process, the variation of the processing accuracy is 2% in the area of 1 μm □, and the reduction of the noise margin due to the variation of the processing dimension is expected to be ⅕.

That is, using a 1 μm cell, 16 M
By using this embodiment, the bit memory can be easily manufactured with only two masks. That is, a lower electrode made of platinum or the like is processed into a stripe shape on a semiconductor substrate (wafer) on which a MOS or a bipolar element is formed, and then PZT is formed.
Etc. to form a ferroelectric thin film. Further, an upper electrode is formed and processed so as to be substantially orthogonal to the lower electrode, an interlayer protective film is formed on the upper electrode, and a through hole for wiring is formed,
It is completed by using devices formed on a Si wafer and aluminum wiring.

Therefore, unlike the conventional DRAM, there is no need to create a complicated cell capacity, and there is no need to use a two-layer or three-layer polysilicon process like a flash memory. 1
It has the merit that a μm □ cell can be created with a manufacturing technology that has a processing accuracy of 1 μm. In addition, it is possible to increase the integration degree four times by setting the processing accuracy to 0.5 μm without any additional process.

Further, since the memory cell of this embodiment does not include an active element such as a MOS transistor, the base on which it is formed is not limited. That is, it can be formed on other than a silicon substrate such as a glass plate. In this case, the peripheral circuit becomes a TFT device. Further, if the low temperature process of the ferroelectric material is achieved, a simple matrix can be formed on the aluminum wiring and the driving circuit can be spread over the entire surface, so that the degree of integration can be further increased. In addition, the circuit elements can be doubled or tripled.

In this way, the multi-layered and stacked memory device of this embodiment can be used as a 128 Mbit nonvolatile memory even with a processing accuracy of 1 μm (1 micron rule). Using the well-known 0.5 micron rule,
It is possible to realize a 512 Mbit non-volatile memory.

In this embodiment, it is possible to incorporate a control circuit such as a smart memory card, a microprocessor and the like, which are restricted in the conventional memory formation, into the element.

In FIG. 5, using the memory cell described above,
A specific example will be shown when the device is configured. Here, an X selection circuit 22, a Y selection circuit 23, a sense circuit 24, a reference dummy cell 25, and a data erasing / writing / reading are arranged in a memory cell mat 21 configured by arranging a plurality of memory cells in a simple matrix. It is composed of a pulse generation circuit 25 and a pulse generation circuit 26 for erasing / writing data.

Next, a nondestructive ferroelectric memory device according to the second embodiment and a driving method thereof will be described.

FIG. 6 shows a configuration example of the ferroelectric memory device according to the second embodiment, which will be described. The basic configuration of the second embodiment is the same as that of the first embodiment, and different points will be described. Although the sense amplifier system in the above-described first embodiment has a symmetrical structure, the memory cell 1 and the dummy cell 1
1 is asymmetric. Therefore, the memory cell 1 and the dummy cell 11 need to be separately prepared.

For example, if two memory cell mats including the dummy cells 11 are prepared and are arranged symmetrically, it is possible to construct them symmetrically by the changeover switch. However, this method is different from the folded bit line method which is generally used in DRAM and the like. This folded bit line method is a method used to strictly match the parasitic load capacitances of the data lines. Since the method of this embodiment reads data by capacitive feedback,
This is not necessary. Since the cell array is composed of the intersecting regions of the lower part and the upper part in addition to the Si device, it is better to arrange the dummy cells inside the cell array from the standpoint of integration and process than to arrange the dummy cells independently. Is also much more advantageous. In this embodiment, the structure is simplified, the recording capacity is increased, and necessary selection circuits and pulse generation circuits are effectively used.

In the ferroelectric memory cell used in this embodiment, the upper stripe electrode is formed on the upper part of the ferroelectric thin film, and the lower stripe electrode is formed on the lower part in a direction substantially orthogonal to the stripe direction of the upper stripe electrode. With this configuration, a region of the ferroelectric thin film sandwiched by the upper and lower stripe electrodes is arranged in a simple matrix, and a dummy cell is a ferroelectric memory cell array provided in the cell array.

As shown in FIG. 6, the differential amplifier 37 having the feedback capacitance 38 is connected to the (+) input terminal side via the Y selection switch 32 for selecting the second line (Y line). Connected to the ferroelectric memory cell array.
A pulse generation circuit 40a is connected to the ferroelectric memory cell array via an X selection switch 39 that selects the first line (X line). The (−) input end side of the differential amplifier 37 is grounded. The output end of the differential amplifier 37 is connected to one end of the input end of the differential amplifier 10, and the other end has the differential amplifier 47, the Y selection switch 42, and the strong amplifier which are configured similarly to the differential amplifier 37 side. The dielectric memory cell array, the X selection switch 49, and the pulse generation circuit 40b are connected. Further, a reference ferroelectric capacitor is connected between the first electrode line 33 and the pulse generator 37. A reference ferroelectric capacitor is connected between the second electrode line 43 and the pulse generator 42b. The pulse generator 37 and the pulse generator 42 may be the same.

A detailed specific example of a memory device using such a ferroelectric memory cell will be described in a fifth embodiment described later.

Next, a nondestructive ferroelectric memory device according to the third embodiment and a driving method thereof will be described.

FIG. 7 shows, as a third example, a specific example in which the ferroelectric memory cell configured to be capable of writing and reading data described in the first embodiment is used in an actual device configuration. Here, the ferroelectric memory cell (memory cell mat) used in this embodiment has the same structure as that of the second embodiment having a simple matrix structure, and has the same parts as those shown in FIGS. 3 to 5. The parts will be described with the same reference numerals.

This memory cell mat 21 is composed of a ferroelectric capacitor 1, an upper electrode line 19 and a lower electrode line 20, and has an X selection circuit 22, a Y selection circuit 23, a sense circuit 24, a reference dummy cell 28, It is composed of pulse generation circuits 26 and 27 for erasing / writing / reading. Here, a switch element 50 for collectively erasing the inside of the memory cell mat is formed.

The Y selection circuit 23 is a circuit for selecting a data line and giving a pulse for writing or erasing data,
A sense amplifier 24, a reference cell 28, and a pulse generator 27 are connected to each of the plurality of Y electrode lines. As a result, it becomes possible to read the memory information for the data lines, and a high data transfer rate can be obtained.

Next, FIG. 8 shows another structural example of this embodiment. Here, the memory cell mat 21, the X selection circuit 22, the Y selection circuit 23, which are configured by a simple matrix,
It is composed of a sense circuit 24, a reference dummy cell 28, and a pulse generation circuit 36 for erasing / writing / reading. A pulse generator 36 for the sense amplifier 24 and the reference cell 28 is connected to each of the plurality of Y electrode lines.

Next, a nondestructive ferroelectric memory device and its driving method as a fourth embodiment will be explained.

FIG. 9A shows a specific example in which the ferroelectric memory cell configured to be capable of writing and reading data described in the first embodiment is used in an actual device configuration. Here, in the parts of the present embodiment, the same parts as those shown in FIGS. 7 and 8 are designated by the same reference numerals, and the description thereof will be omitted. Here, the ferroelectric memory cell (memory cell mat) used in this embodiment has the same structure as that of the second embodiment having the simple matrix structure, and the ferroelectric capacitor 1 and
It is composed of an upper electrode line 19 and a lower electrode line 20, and has an X selection circuit 22, a Y selection circuit 23, and a sense circuit 2.
4, reference dummy cell 28, and data erasing / writing / reading pulse generation circuits 26 and 27.

Further, the collective SW elements 50a and 50b for collectively erasing the data in the memory cell mat 21 are
Memory cell mat 21, X selection circuit 22, Y selection circuit 2
3 and 3, respectively.

In this embodiment, as shown in FIG.
Collective SW element 50b (not shown) connected to a plurality of unit lower electrode lines (second electrode lines) 20
And a reference selection dummy cell 28 between the Y selection SW23,
Further, a reference pulse generator 27 is provided. As a result, one sense system can be formed for a plurality of electrode lines, and pattern design becomes extremely easy. For example,
When one mat has a byte structure of 64 KB, if 512 X lines are provided, one sense amplifier can be formed for every 128 lines.

Next, a nondestructive ferroelectric memory device and its driving method as a fifth embodiment will be explained. The basic configuration of the fifth embodiment is the same as that of the second embodiment described above, and FIG. 10A shows the basic configuration, which is the same as the configuration shown in FIG. 4 of the first embodiment. 10 (b)
Is a modification based on the configuration shown in FIG. In this embodiment, since the memory cell 1 and the dummy cell 17 are separately prepared in the first embodiment, two memory cell mats including the dummy cell 17 are prepared as in the case of the second embodiment. Are arranged symmetrically. Of course,
Unlike the folded bit line system used in a DRAM or the like, in this embodiment, since the reading is performed by capacitive feedback, it is not necessary to match the parasitic load capacitances of the data lines.
It simply simplifies the configuration, increases the recording capacity, and effectively uses the necessary selection circuit and pulse generation circuit.

As shown in FIG. 10B, a plurality of ferroelectric thin film capacitors 1a are connected to the input side of the differential amplifier 7.
These ferroelectric thin film capacitors 1a have a first
Electrode (X electrode line 19) and second electrode (Y electrode line 2)
It is sandwiched by 0) and has a simple matrix structure. The Y electrode line 20 includes a plurality of memory cells 1 and one dummy cell 11
a is connected to the input side of the differential amplifier 7. On the other hand, the input side of the differential amplifier 17 is connected to the plurality of memory cells 1b and one dummy cell 11b.

Here, the effective additional capacitances 51 and 52 are
The capacity may be the same or different. In the actual configuration, the upper electrode 19 and the upper electrode 53 are symmetrically connected to the sense system including the sense circuit 24. Where the upper electrode 1
The SW and the differential amplifier 17 between 9 and the upper electrode 53 may be omitted. The upper electrode 53 forms a simple matrix so as to be substantially orthogonal to the pair of electrode lines 13. The dummy cells 11a and 11b also form a simple matrix so as to be substantially orthogonal to the electrode lines 18 and the electrode lines 53. The operation of such a memory device will be described with reference to FIGS.
This will be described with reference to FIG. The dummy cell 11b is used when detecting the cell 1b on the right side of the sense system, and the dummy cell 11b is used when detecting the cell 1b on the right side of the sense system.
It controls the pulse generation circuit connected to the electrodes of a and 11b.

In this case, the number of dummy ferroelectric capacitors 11a and 11b connected to the electrode line 19 connected to the differential amplifier 7 and the electrode line 52 connected to the differential amplifier 17 may be the same. Is the effective additional capacity 51, 52
Becomes the same and the load of the sense amplifier becomes the same, so
The timing of signals appearing in the differential amplifier becomes the same, which is convenient.

Next, a non-destructive ferroelectric memory device and its driving method as a sixth embodiment will be explained. The basic configuration of the memory device according to the present embodiment is the same as the above-mentioned fifth configuration
This is the same as the embodiment and is a modification thereof.

FIG. 11 shows the structure of the ferroelectric memory device of the sixth embodiment. In this ferroelectric memory device, the Y selection circuits 62a, 62a and
b, and memory cell mats 60a and 60b are provided. The memory cell mats 60a and 60b are provided with X selection circuits 61a and 61b, and the X and Y selection circuits are
The pulse generation circuits 65 are respectively connected. Therefore, the memory cell mats 60a and 60b are symmetrically arranged with the sense circuit 63 interposed therebetween. In such a configuration, one Y-selection signal line may be connected to each sense circuit, or some collected electrodes may be combined by Y-selection. At least one pulse generation circuit 65 is required.

Next, a non-destructive ferroelectric memory device and its driving method as a seventh embodiment will be explained.

FIG. 12 shows the configuration of a memory device according to the seventh embodiment. This memory device includes sense circuits 63a to 63a.
3n are sandwiched between the Y selection circuits 62a1 and 62b1 to 62a.
n, 62bn, and the memory cell mat 60, respectively
a1 and 60b1 to 60an and 60bn are provided. The memory cell mats 60a1 to 60an, 60b1 to 6
X selection circuits 61a and 61b are provided at 0bn, and a pulse generation circuit 65 is connected to the X and Y selection circuits.

This embodiment has a circuit configuration in which the devices of the fifth embodiment are stacked. In this configuration, the Y selection circuit 6 is sandwiched by the sense circuits 63a to 63n.
2a1, 62b1 to 62an, 62bn 32 and memory cell mats 60a1, 60b1 to 60an, 60bn have a plurality of structural units that are substantially symmetrical.

The structure shown in FIG. 13 is a modified example of the seventh embodiment, in which the electrode lines 19a and 19b are shared by the structural units in the Y direction, and the dummy cells 11a1 to 11a are shared.
n, 11b1 to 11bn are also shared by the structural units in the Y direction.

Next, with reference to FIG. 14, a nondestructive ferroelectric memory device and its driving method as an eighth embodiment will be described. The method of writing and reading data in this memory device is the same as that in FIGS. 3 (a) to 3 (c).

In a ferroelectric memory constituted by a simple matrix having a ferroelectric thin film capacitor sandwiched by a pair of upper and lower electrodes orthogonal to each other as a memory cell, spontaneous polarization (polarization) in the ferroelectric thin film is A first pulse (erasing pulse) having a voltage Ve larger than the coercive voltage Vc of the ferroelectric thin film is applied to the first polarization state of the two states to polarize the first polarization state, and then the applied voltage is applied. The term “Ve” means that a second pulse (writing pulse) having a voltage Vw having an absolute value smaller than the opposite polarity Ve is applied, and the domain having polarization in the first direction and the first direction are This is a method of storing information in a partially polarized state in which a domain having a second polarization in the opposite direction is mixed.

In the present embodiment, as shown in FIG. 14, the memory cell mat of the entire chip is composed of one block or more of recording unit called a sector 66, and at least one sector is included in this sector 66. The above reference memory cell (dummy cell) 28 is provided. The data in the memory cells are erased at once.

In FIG. 14, the memory cell and
Data writing to the dummy cells may be collectively performed in sector units. The data read in the sector 66 enables random access. Further, it may be a non-volatile memory chip having a plurality of sectors 66 and a sector control circuit 67 in one chip.

As shown in FIG. 15, each sector 40 has a memory cell mat 21, an X selection circuit 21, a Y selection circuit 23, a sense circuit 24, at least one dummy cell 28, and a control circuit 26. You may comprise.

Further, as shown in FIG. 16, a plurality of chips including a memory cell mat, a bus line 68, and an I / O circuit 6 are provided.
It can be used for a removable memory device, for example, a memory card, having an output terminal 71 for inputting / outputting to / from the CPU 9, the control circuit 70 and the outside. Next, with reference to FIG. 17, a nondestructive ferroelectric memory device and its driving method as a ninth embodiment will be described.

In this memory device, the method of writing and reading data is the same as in FIGS. 3A to 3C,
This structure is the same as that of the eighth embodiment.

In FIG. 17, it is composed of blocks 72 including a plurality of sectors 66, and one chip is composed of a plurality of blocks 72.

The blocks 72 may be collectively erased by the collective erase circuit 73 in units of blocks, data may be written in units of each sector 66, and data may be randomly accessed. Further, the blocks 72 may be collectively erased by the collective erase circuit 73 in units of blocks, writing may be performed in units of each sector 66, and reading may be similarly performed collectively.

Next, with reference to FIG. 18, a nondestructive ferroelectric memory device as a tenth embodiment and a driving method thereof will be described.

In this memory device, the method of writing and reading data is the same as that of the first embodiment, and the configuration is based on the eighth embodiment.

This memory device includes a plurality of X selection circuits 22.
And a Y selection circuit 75 including a function of a sense circuit, and a memory cell area 74 including a memory cell including a dummy cell 28.
And a pulse generation circuit 65. The X selection circuit 22 is common and the Y selection circuit 75 is independent for each sector on a chip or block basis. Further, it can be used for a removable memory device having a plurality of chips, a bus line 68, an I / O circuit 65, a control circuit 70, and an output terminal 71, for example, a memory card.

Next, with reference to FIG. 19, a nondestructive ferroelectric memory device and its driving method as an eleventh embodiment will be described. The method of writing and reading data in this memory device is the same as that in FIGS. 3A to 3C.

In this embodiment, the memory section 81, the memory management function 82, and the I / O circuit 83 are provided on one chip 80.
The present invention is used for a removable memory device equipped with a, for example, a memory card.

The memory management function 82 controls erasing, writing, and reading of data in block or sector units in the storage area in the memory unit 81, and has a directory (address information) and keyword information in each sector unit. Good.

Next, with reference to FIG. 20, a nondestructive ferroelectric memory device and its driving method as a twelfth embodiment will be described. This memory device is a modification based on the above-described eighth embodiment, and the method of writing and reading data is the same as that of FIGS. 3A to 3C.

In a ferroelectric memory constituted by a simple matrix having a ferroelectric thin film capacitor sandwiched by a pair of upper and lower electrodes orthogonal to each other as a memory cell, spontaneous polarization (polarization) in the ferroelectric thin film is suppressed. A first pulse (erasing pulse) having a voltage Ve larger than the coercive voltage Vc of the ferroelectric thin film is applied to the first polarization state of the two states to polarize the first polarization state, and then the applied voltage is applied. The term “Ve” means that a second pulse (writing pulse) having a voltage Vw having an absolute value smaller than the opposite polarity Ve is applied, and the domain having polarization in the first direction and the first direction are This is a method of storing information in a partially polarized state in which a domain having a second polarization in the opposite direction is mixed.

The configuration of this embodiment is composed of one chip or a plurality of chips, and includes a memory section 81, an antenna 85, a tuning circuit 86, a detection circuit 87, a demodulation circuit 88, and an oscillation circuit 9.
1, a modulation circuit 90, and a control circuit 89, which is used for a removable memory device, such as a memory card, for exchanging data signals with the radio waves generated and oscillated. Also,
Voltage generation circuit 9 for extracting voltage for driving from radio waves
It may be a removable memory device having two. Further, it may be a removable memory device in which parts other than the antenna 85 are formed on one chip, for example, a memory card.

A removable memory device, such as a memory card, for exchanging signals with a one-chip radio wave including an integrated antenna may be used.

Further, in the present embodiment, microwaves to millimeter waves are used as radio waves, but the present invention is not limited to this.

The present embodiment is a memory device using a ferroelectric thin film as a storage medium. In addition to low drive voltage, high speed erasing, high speed writing, high speed reading and high integration, non-destructive type is also seen. It has no characteristics. That is, the external recording device is individualized, the drive unit is eliminated, and the reliability is increased,
In addition, high speed and low power were achieved. For the first time, it is possible to realize a large-capacity data carrier that does not have a battery by radio waves. For example, card capacities range from 4 Mbytes to 256 Mbytes. These can meet all needs.

Next, with reference to FIGS. 21A and 21B, a nondestructive ferroelectric memory device as a thirteenth embodiment and a method for driving the same will be described. The configuration of this memory device is based on the twelfth embodiment, and the method of writing and reading data is the same as that of FIGS. 3A to 3C.

In this embodiment, the memory card shown in the twelfth embodiment is used, and an RF antenna or a microwave antenna including a signal modulation / demodulation circuit serving as a transmission / reception function is installed in an ordinary computer or a small computer, and is unique to an individual. The data of can be exchanged by radio waves. Further, the personal reference number may be read from the memory card 98 capable of communicating information by radio waves and the environment may be automatically set.

The operation will be described with reference to the flowchart of FIG.

First, the user is seated in front of a computer equipped with a transmission / reception function (step S1). The computer reads the ID number oscillated from the memory card 98 (step S2), and based on the ID number, the computer sets the environment preset (step S3). Further, the personal information is read from the memory card 98 (step S4), and the actual work is started (step S5). After the completion of the work, new personal information is written in the memory card 98 (step S6), and a series of steps is completed. Further, when the work is to be performed again, only by sitting in front of the computer, the above-described processing is performed, and the work can be similarly started.

This embodiment is characterized in that a ferroelectric thin film is used as a recording medium, and in addition to low voltage, high speed erasing, high speed writing, high speed reading, high integration, nondestructive reading. That is, the external recording device is individualized, the driving unit is not required, and high reliability is achieved, and high speed processing, low power consumption, and low driving power are realized. . Therefore, by converting radio waves into a power source and driving the power source, a large-capacity data carrier without a battery can be realized. For example, memory card capacities range from 4 Mbytes to 256 Mbytes. They are,
It is possible to meet the needs of a personal wireless card for a computer.

Next, with reference to FIG. 22, a nondestructive ferroelectric memory device and its driving method as a fourteenth embodiment will be described. The configuration of this memory device uses the memory card described in the twelfth embodiment, and the method of writing and reading data is the same as in FIGS. 3A to 3C.

In this embodiment, the door lock 101, the in-vehicle computer 102, the navigation system 103, etc. mounted on the automobile have an RF antenna and a microwave antenna 85 including a signal modulation / demodulation circuit, and data unique to an individual is transmitted by radio waves. It is an exchangeable memory card 98.

When a driver carrying the memory card 98 as described above approaches an automobile, this system is activated on the automobile side to unlock the door lock 101 and activate the navigation system 103, etc. The work being performed is set at a suitable level on an individual level.

According to this embodiment, low voltage, high speed erase,
In addition to high-speed writing, high-speed reading, and high integration, it has the characteristics of non-destructive reading. That is, the external recording device is individualized, the drive unit is not required, and the reliability is increased, and high speed, low power consumption, and low drive power are realized. Therefore, it is possible to realize a large-capacity data carrier that does not have a battery for radio waves. For example, memory card capacities range from 4 Mbytes to 256 Mbytes. These can meet the needs of personal wireless files for automobiles.

Next, with reference to FIG. 23, a nondestructive ferroelectric memory device and its driving method as a 15th embodiment will be described. The configuration of this memory device uses the memory card described in the twelfth embodiment, and the method of writing and reading data is the same as in FIGS. 3A to 3C.

In this embodiment, the automatic lock mechanism 104, the ID recognizing device 105, the position recognizing device 106, etc. mounted on the door of the room have an RF antenna and a microwave antenna 58 including a signal modulation / demodulation circuit and are peculiar to an individual. The memory card 98 is capable of exchanging data by radio waves.

According to the present embodiment, a system in which only a specific person set in advance can enter the room is constructed.
The same effect as the fourth embodiment can be obtained.

Next, with reference to FIG. 24, a nondestructive ferroelectric memory device as a 16th embodiment and a method for driving the same will be described. The configuration of this memory device uses the memory card described in the twelfth embodiment, and the method of writing and reading data is the same as in FIGS. 3A to 3C.

A memory card 98 equipped with an automatic tailor device (automatic depositing / withdrawing device) 107, having an RF antenna including a signal modulation / demodulation circuit and a microwave antenna 108, and capable of exchanging data peculiar to an individual by radio waves.

This system uses a ferroelectric material and, in addition to low voltage, high speed erasing, high speed writing, high speed reading and high integration,
It has a unique feature other than being non-destructive. That is, the external recording device is individualized, the drive unit is lost,
High reliability, high speed, and low power consumption were achieved. For the first time, it is possible to realize a large-capacity data carrier that does not have a battery by radio waves. For example, card capacities range from 4 Mbytes to 256 Mbytes. These are able to meet the needs of your account's personal wireless files.

Next, with reference to FIG. 25, a nondestructive ferroelectric memory device and a method of driving the same according to the seventeenth embodiment will be described. The configuration of this memory device uses the memory card described in the twelfth embodiment, and the method of writing and reading data is the same as in FIGS. 3A to 3C.

The memory device shown in FIG. 25 is equipped with an RF antenna including a signal modulation / demodulation circuit and a microwave antenna 110 mounted on a home-use television, a game device, and a home-use data terminal 109, and data unique to an individual can be exchanged by radio waves. Memory card 98. This memory card 9
8, various information such as the health condition of the owner, account information, business information, and FAX information can be provided. Therefore, according to the present embodiment, the above-described fifteenth
The same effect as that of the embodiment can be obtained.

Next, with reference to FIG. 26, a nondestructive ferroelectric memory device and its driving method as an eighteenth embodiment will be described. The configuration of this memory device is based on the twelfth embodiment, and the method of writing and reading data is the same as that of FIGS. 3A to 3C.

A memory section 81, which is composed of one chip or a plurality of chips and in which memory cells having a ferroelectric thin film as a recording medium is arranged in a matrix, a control circuit 89, a high-speed light modulator and a high-speed circuit photodiode 112, A removable memory device, such as a memory card 98, which is composed of a photovoltaic cell 111.

In the above-described embodiment, the communication is performed by radio waves, but the memory card 98 of the present embodiment is used.
Is for writing and reading data by light, and the same effect as that of the fifteenth embodiment can be obtained.

Next, with reference to FIG. 27, a nondestructive ferroelectric memory device and its driving method as a nineteenth embodiment will be described. The method of writing and reading data in this memory device is the same as that in FIGS. 3A to 3C.

In a ferroelectric memory constituted by a simple matrix having a ferroelectric thin film capacitor sandwiched by a pair of upper and lower electrodes orthogonal to each other as a memory cell, spontaneous polarization (polarization) in the ferroelectric thin film is suppressed. A first pulse (erasing pulse) having a voltage Ve larger than the coercive voltage Vc of the ferroelectric thin film is applied to the first polarization state of the two states to polarize the first polarization state, and then the applied voltage is applied. The term “Ve” means that a second pulse (writing pulse) having a voltage Vw having an absolute value smaller than the opposite polarity Ve is applied, and the domain having polarization in the first direction and the first direction are This is a method of storing information in a partially polarized state in which a domain having a second polarization in the opposite direction is mixed.

FIG. 27 shows the positional relationship between the memory cell mat 21 and the peripheral circuit 115 when viewed from above. See also FIG.
(A) to (c) are diagrams showing a process for forming the memory cell mat 21.

The ferroelectric thin film is sandwiched between the upper electrode line 19 formed as a stripe electrode and the lower electrode line 20 formed as a stripe electrode substantially orthogonal to the stripe electrode, and the memory cell 1 is provided in the region of the sandwiched intersection. Is formed. These memory cells 1 are arranged in a simple matrix.

This simple matrix memory cell mat 2
1 is formed on the region including the silicon oxide film 121, and the peripheral circuit 115 is formed on the region other than the memory matrix mat 21.

Preformed bipolar transistor and M
The semiconductor substrate including the OS transistor 124 is PSG or B
Before forming a contact hole for forming a passivation film 122 such as PSG and connecting with a diffusion layer of a device,
The lower electrode line 20, which includes the oxide film 121, is formed on the passivation film 122 such as PSG or BPSG.
The ferroelectric thin film 125 and the upper electrode line 19 are laminated in this order.

Here, the upper and lower electrode lines are usually formed by using a vapor deposition apparatus, a sputtering apparatus, a magnetron sputtering apparatus or the like, and the etching processing is performed by a usual photolithography and dry etching apparatus, an ion etching apparatus, a reaction apparatus. It is performed by using a reactive ion etching device, an ion milling device, or the like. Ferroelectric materials include spin coating methods such as sol-gel method and organometallic decomposition method, sputtering and MOCV.
D and the like, the material used is platinum group element as the upper and lower electrodes,
A combination including a conductive oxide and an adhesive layer is suitable. Of course, the material is not limited to these, and any material that can be used equivalently may be used. The ferroelectric is PZT, PLZ.
T, Bi layered compounds and the like are preferred. Protective film 12 on top
Do 6.

After that, the semiconductor device 124 and the upper and lower electrode lines 19 and 20 are simultaneously or separately vi.
A hole is formed and wiring such as aluminum or aluminum with a heat-resistant barrier layer is formed. After that, a protective film is formed again.

Further, in this embodiment, the peripheral circuits may be formed in the peripheral region of the memory matrix mat, or may be dispersed according to the function in the chip.

Next, with reference to FIG. 29, a nondestructive ferroelectric memory device as a 20th embodiment and a method for driving the same will be described. The configuration of this memory device is based on the twelfth embodiment, and the method of writing and reading data is the same as that of FIGS. 3A to 3C.

FIG. 29A shows the positional relationship between the memory cell mat 21 and the peripheral circuit 115. Also, FIG. 29 (b),
(C) shows a cross-sectional structure in the manufacturing process. Here, a memory cell mat 2 of a simple matrix in which a ferroelectric thin film is used as a recording medium is provided on the upper layer of the circuit where the peripheral circuits 115 are spread.
1 is formed.

As shown in FIG. 29 (b), a bipolar transistor or an MO, which is an active device formed in advance, is formed.
PSG or B on the semiconductor substrate including the S transistor 124
After forming a passivation film 122 such as PSG and forming a contact hole connecting to a diffusion layer of a device, one layer or a plurality of wirings are formed. After forming these devices and circuits, an appropriate interlayer film 128 is formed and
A hole is formed in advance, and a lower electrode line 20, a ferroelectric thin film 125, and an upper electrode line 19 are formed in that order in that order. The forming method and material may be the same as those in the nineteenth embodiment described above.

Further, a central processing unit including a peripheral circuit and a control circuit and a digital signal processing unit may be formed in an active device on a semiconductor substrate.

According to this embodiment, since the memory cell has no transistor, the semiconductor chip can be effectively used. For example, a 32-bit central processing circuit can be formed in an active element, and memories can be stacked to form a one-chip microcomputer. Further, it is possible to form a digital signal processing device including a central processing circuit as an active element and stack memories to form a one-chip complete audio / image processing function with a recording device. Next, referring to FIG. 30, the second
A nondestructive ferroelectric memory device as one embodiment and a driving method thereof will be described.

In this embodiment, since the memory cell does not have a transistor, the ferroelectric memory cell mat formed of a simple matrix is not limited to one layer.
Multiple layers can be formed. At least two pairs of upper electrode lines 20 and lower electrode lines 19 may be stacked.

According to this embodiment, since the memory cell does not include a transistor, the semiconductor chip can be effectively used. For example, a 32-bit central processing circuit is formed as an active element, and memory cells are stacked to form a one-chip microcomputer. Further, a digital signal processing device including a central processing circuit is formed as an active element, and memory cells are stacked to form a one-chip complete audio / image processing function with a recording device.

Further, according to this embodiment, a very large memory can be integrated with a loose processing rule. Where 1
Even with micron processing rules, this embodiment allows for 512 Mbit to 2 Gbit of non-volatile memory with 4 layer stacking, which is suitable for multimedia.

Although the description has been given based on the above embodiments, the present invention also includes the following inventions.

(1) In a ferroelectric memory having a ferroelectric thin film capacitor sandwiched by first and second electrodes which are orthogonal to each other as a memory cell, the first of two states of spontaneous polarization. Of the ferroelectric thin film to the polarization state of
a first pulse having a voltage Ve greater than c is applied to polarize, and then a second pulse having a voltage Vw having an absolute value smaller than Ve having a polarity opposite to the applied voltage Ve is applied; In a method of storing information in a partially polarized state in which a domain having a polarization in the first direction and a domain having a second polarization in the direction opposite to the first direction are mixed, an absolute value from Ve is used. The non-destructive memory information is read by using the same or small positive or negative read pulse Vr, and the comparison dummy ferroelectric thin film capacitor provided separately from the ferroelectric thin film capacitor and the ferroelectric A first differential amplifier that is fed back by a capacitance connected to the body thin film capacitor, and a second differential amplifier that is fed back by a capacitance connected to the comparative dummy ferroelectric thin film capacitor , These differential type The third differential ferroelectric memory device constituted by an amplifier for receiving the output of the.

(2) In the ferroelectric memory device, a plurality of the ferroelectric thin film capacitor elements are provided, and the ferroelectric thin film capacitor element is passed through a selection switch to pass a first erase pulse and a first erase pulse. A second erase pulse and a second read pulse are connected to a first pulse generator that generates a write pulse and a first read pulse, and a second dummy pulse and a second blank pulse are passed through a comparative dummy ferroelectric thin film capacitor through a selection switch. (1) characterized in that it is connected to a second pulse generator for generating.
The ferroelectric memory device according to claim 1.

(2) 'In the ferroelectric memory device, a plurality of the ferroelectric thin film capacitor elements are provided, and the ferroelectric thin film capacitor element is passed through a selection switch to pass a first erasing pulse Writing pulse, a first erasing pulse for generating a first reading pulse, and a second erasing pulse and a second writing pulse through a selection switch in the comparative dummy ferroelectric thin film capacitor. The ferroelectric memory device according to (1) above, wherein the ferroelectric memory device is connected to a second pulse generator that generates a second read pulse.

(3) In the ferroelectric memory device, the area of the dummy cell is about 1/2 of the ratio of the capacitance difference between the first direction and the partially polarized state to the capacitance in the first direction. The ferroelectric memory device according to (1) above, which is larger than the area.

(4) In the ferroelectric memory device, the area of the dummy cell is 8/10 to 2/10 of the ratio of the capacitance difference between the first direction and the partially polarized state to the capacitance in the first direction. The ferroelectric memory device according to (1) above, which is larger than a cell area.

(5) In the ferroelectric memory device, a first changeover switch is provided between the ferroelectric thin film capacitor and the first differential amplifier, and a comparison dummy ferroelectric thin film capacitor and a second difference are provided. The ferroelectric memory device according to any one of the above items (1) and (2), characterized in that a second changeover switch is provided between the dynamic amplifiers.

(6) In the ferroelectric memory device, one input terminal of the first differential amplifier and one terminal of the first changeover switch are 0 bias or the same potential, and One input terminal of the differential amplifier 2 and one terminal of the second changeover switch
The ferroelectric memory device according to any one of the items (1) to (3), wherein the ferroelectric memory device is set to 0 bias or the same potential.

Therefore, according to the above items (1) to (6), the voltage Ve larger than the coercive voltage Vc of the ferroelectric thin film is generated in the first polarization state out of the two states of spontaneous polarization. Is applied to polarize, and then a second pulse 14 having a voltage Vw having a polarity opposite to the applied voltage Ve is applied to form a domain having a polarization in the first direction. Information is stored in a partially polarized state in which domains having a second polarization in the direction opposite to the first direction are mixed. This state appears as a difference in capacitance, but when reading with a read voltage, the capacitance ratio ΔC / C is small, so it is necessary to amplify. At this time, considering the temperature dependence and the data retention time dependence of C, it is necessary to perform comparative reading by a reference cell using a ferroelectric capacitor. Here, the non-destructive large-capacity memory can be realized by the sense circuit in which the small-capacity ΔC / C can be read out without changing the voltage of the data line and the comparative reading of the reference cell and the capacitance-added feedback circuit are combined. Therefore, in the sense circuit that combines the small-capacity feedback circuit that can read out a small ΔC / C without changing the voltage of the data line and the comparative reading of the reference cell, the non-coherence at the time of writing and the non-coherence at the time of reading, A nondestructive ferroelectric memory that can realize destructive reading and is suitable for large scale and large capacity can be realized.

(7) In the ferroelectric memory device, a plurality of ferroelectric thin film capacitors connected to the first differential amplifier are provided, and the ferroelectric thin-film capacitor according to item (1) is characterized. Dielectric memory device.

(8) In the ferroelectric memory device, the ferroelectric thin film capacitor connected to the first differential amplifier has a striped upper electrode and a striped lower electrode substantially orthogonal to the striped upper electrode. 2. The ferroelectric memory device according to item (1), wherein the ferroelectric memory device has a simple matrix structure in which the regions are sandwiched by the upper electrodes and the stock electrodes intersecting each other and being sandwiched between them.

(9) In the ferroelectric memory device described in the item (8), a line selection circuit connected to the first electrode and a pulse generator connected through the line selection circuit are characterized. Ferroelectric memory device.

(10) In the ferroelectric memory device, there is provided a line selection circuit connected between the second electrode and the first differential amplifier, and the paragraphs (7) and (7) are provided. 8. The ferroelectric memory device according to any one of items 8).

(11) In the ferroelectric memory device, the plurality of second ferroelectric thin film capacitors connected to the second differential amplifier are plural, and the item (1) is described. Ferroelectric memory device.

(12) The ferroelectric memory device has a line selection circuit connected between the electrode of the second ferroelectric thin film capacitor and the second differential amplifier. The ferroelectric memory device according to any one of the items (1) and (7) to (11).

(13) The ferroelectric memory device has a line selection circuit connected between the electrode of the second ferroelectric capacitor and the second pulse generator for generating the second pulse. (1) above, characterized in that
The ferroelectric memory device according to any one of items (7) to (11).

(14) In the ferroelectric memory device, a reference ferroelectric capacitor is connected between the first electrode line and the first pulse generator, (1) Item 7. The ferroelectric memory device according to any one of items (7) to (13).

(15) In the ferroelectric memory device, a reference ferroelectric capacitor is connected between the second electrode line and the first pulse generator. (1) Item 7. The ferroelectric memory device according to any one of items (7) to (14).

(16) In the ferroelectric memory device, the first pulse generator and the second pulse generator are equivalent to each other, and the items (1) and (7) to (7) are provided. 15. The ferroelectric memory device according to any one of 15).

Therefore, according to the above items (7) to (16), a dummy reference cell is formed in the simple matrix and is driven by the same pulse drive circuit.

Therefore, the manufacturing and pattern design can be easily carried out, and stable driving is possible.

(17) In the ferroelectric memory device, a memory cell mat, a collective switch connected to the first electrode line, a first selection circuit, a first pulse generator, and a sense circuit are further provided. An amplifier and another collective switch connected to the second electrode line, a second pulse generator equivalent to the first pulse generator, a reference cell, and a reference pulse generator. The ferroelectric memory device according to (1) above.

(18) In the ferroelectric memory device, the sense amplifier, the reference cell, and the pulse generator are connected to each of the plurality of the second electrode lines. (17) Item Ferroelectric memory device.

Therefore, according to the items (17) and (18), the output of each data line is connected to the sense circuit, and the reference dummy cells for each data line are arranged. Read the signal.

Therefore, a large amount of data can be read once.

(19) In the ferroelectric memory device, a selection switch and a reference pulse generator are provided between another reference switch and the collective switch connected to the second electrode line. The ferroelectric memory device according to item (17).

(20) In the ferroelectric memory device, a pulse generator for a sense amplifier and a reference cell is connected to each of the plurality of units through a selection circuit through the second electrode line. The ferroelectric memory device according to the item (17).

Therefore, according to the above items (19) and (20), the selection circuit is provided in the data line of an arbitrary number of units, and the output is connected to the sense circuit, and the data line of the arbitrary number of units is connected. Since the reference dummy cells are arranged, the data line is selected and the signal is read.

Therefore, it becomes possible to read a large amount of data in units of bytes once. Further, it becomes possible to design the pattern of the sense circuit.

(21) In the ferroelectric memory device, a plurality of electrodes are provided on the first electrode line connected to the first differential amplifier and the second electrode line connected to the second differential amplifier. 2. The ferroelectric memory device according to item (1) above, wherein the memory cell ferroelectric capacitor of 1) and at least one dummy ferroelectric capacitor are connected.

(22) In the ferroelectric memory device, connected to a first electrode line connected to the first differential amplifier and a second electrode line connected to the second differential amplifier, respectively. The ferroelectric memory device as described in the above item (21), wherein the number of the formed memory cell ferroelectric capacitors is the same. (23) In the ferroelectric memory device, the first
The number of dummy ferroelectric capacitors connected to each of the first electrode line connected to the differential amplifier and the second electrode line connected to the second differential amplifier is the same. The ferroelectric memory device according to the item (21).

(24) In the ferroelectric memory device, when the information of the ferroelectric capacitance of the memory cell connected to the first electrode line connected to the first differential amplifier is read, the second difference is generated. Memory cell connected to the second electrode line connected to the second differential amplifier by performing comparative reading using the dummy ferroelectric capacitor connected to the second electrode line connected to the dynamic amplifier. In reading the ferroelectric capacitor, the comparative reading is performed by using the dummy ferroelectric capacitor connected to the first electrode line connected to the first differential amplifier. A ferroelectric memory device according to claim 1.

(25) In the ferroelectric memory device, the first electrode line and the third electrode line connected to the first differential amplifier are substantially orthogonal to each other to form a simple matrix. (2) The second electrode line and the fourth electrode line connected to the two differential amplifiers are substantially orthogonal to each other to form a simple matrix.
2. A ferroelectric memory device according to item.

(26) In the ferroelectric memory device, the dummy ferroelectric capacitor is given as an intersection of the first electrode line and the third electrode substantially orthogonal to the dummy electrode, and the dummy ferroelectric capacitor is The ferroelectric memory device according to item (21), which is provided as an intersection of the second electrode line and another electrode substantially orthogonal thereto.

Therefore, according to the above items (21) and (26), a memory cell and a reference memory cell are created in two simple matrices and compared to each other, so that one sense circuit can double the memory cells. Can read cells.

Therefore, since the data line capacities are the same,
The sense amplifier can be easily designed and the area of the sense amplifier can be effectively used.

(27) In the ferroelectric memory device, it further comprises a plurality of X selection circuits, a Y selection circuit, a memory cell mat, a pulse generation circuit, and a sense amplifier. 7. The ferroelectric memory device according to the item (1), wherein the Y selection circuit and the memory cell mat are configured to be substantially the same.

Therefore, according to the above item (27), by arranging the memory cells symmetrically via the sense amplifier, the memory mat can be efficiently arranged in an effective area.

Therefore, it is possible to increase the bit density.

(28) In the above ferroelectric memory device, the Y selection circuit and the memory cell mat have a plurality of structural units which are arranged substantially across the sense amplifier. 2. A ferroelectric memory device according to item.

(29) In the ferroelectric memory device, the first memory cell, the first dummy cell and the second memory cell are provided.
29. The ferroelectric memory device according to item (28) above, wherein the memory cell and the second dummy cell are composed of a simple matrix sandwiched by upper and lower electrodes that are substantially orthogonal to each other.

Therefore, according to the above items (28) and (29), the memory cell can share the X selection circuit and the Y selection circuit and the sense amplifier can be divided to disperse the functions. Reference cells can be created at the same time.

Therefore, it is possible to increase the bit density and achieve high functionality.

(30) In a ferroelectric memory device having a ferroelectric thin film capacitor sandwiched by a pair of electrodes as a memory cell, the ferroelectric memory device is set to the first polarization state out of two states of spontaneous polarization. A first pulse having a voltage Ve larger than the coercive voltage Vc of the dielectric thin film is applied to polarize, and then a second voltage Vw having an absolute value smaller than Ve having a polarity opposite to the applied voltage Ve is applied. Is applied, and information is stored in a partially polarized state in which a domain having a polarization in the first direction and a domain having a second polarization in the opposite direction to the first direction are mixed. In the above, the ferroelectric memory cell and the reference memory cell are composed of a simple matrix of a pair of electrodes that are substantially orthogonal to each other, and the memory cell mat of the entire chip is called one or more sectors. A ferroelectric memory device comprising at least one reference memory cell arranged in this sector, and erasing is collectively performed in this memory cell.

(31) In the ferroelectric memory device, the writing to the ferroelectric memory cell and the reference memory cell is collectively performed in sector units, and the item (30) is described. Ferroelectric memory device.

(32) In the ferroelectric memory device, the reading in the sector can be randomly accessed, and the ferroelectric memory device according to the item (30).

(33) The ferroelectric memory device according to item (30), which is a nonvolatile memory chip having a plurality of sectors and a sector control circuit in one chip. Dielectric memory device.

(34) In the ferroelectric memory device, each sector has a memory cell mat, an X selection sense circuit, a Y selection sense circuit, at least one dummy cell,
And a control circuit. The ferroelectric memory device according to the item (31).

(35) The ferroelectric memory device is a removable memory device having a plurality of chips, a bus line, an I / O circuit, a control circuit and an output terminal, for example, a memory card. (33),
The ferroelectric memory device according to any one of items (34).

Therefore, according to the above items (30) to (35), the minimum unit of the memory is made into a sector, and the unit for erasing and writing is set as the sector.

Therefore, non-interference writing and non-destructiveness during writing are guaranteed.

(36) In the ferroelectric memory device, the block is formed including a plurality of sectors, and one chip is formed of a plurality of blocks. Ferroelectric memory device. (37) In the ferroelectric memory device, the information is collectively erased in the block unit, the information is written in each sector unit, and the information is read out at random access. A ferroelectric memory device according to claim 1.

(38) In the ferroelectric memory device, information is collectively erased in block units, information is written in each sector, and information is read in batch. ). The ferroelectric memory device according to the paragraph.

Therefore, according to the above items (36) to (38), the minimum unit of erasing is divided into blocks, and the minimum unit of writing in the memory is sectorized to read information.

Therefore, non-interference writing and non-destructiveness during writing are guaranteed.

(39) In the ferroelectric memory device, a plurality of X selection circuits, Y selection circuits, memory cell mats, pulse generation circuits, and sense amplifiers are provided, and the sense amplifiers are sandwiched between them. The Y selection circuit and the memory cell mat are arranged substantially symmetrically, and the X selection circuit is common to each sector in one chip or block unit, and the Y selection circuit is arranged independently. The ferroelectric memory device according to any one of items (36) and (36).

(40) The ferroelectric memory device is a removable memory device having a plurality of chips, a bus line, an I / O circuit, a control circuit and an output terminal, for example, a memory card. The ferroelectric memory device according to any one of (37) to (39) above.

Therefore, according to the above items (39) and (40), the memory cell area common to the X selection is used as a block for erasing, and a certain Y selection is used as a sector for writing. .

Therefore, it is possible to increase the bit density and achieve high functionality.

(41) In the ferroelectric memory device, a removable memory device having a memory section, a memory management function, and an I / O circuit on one chip, for example, a memory card, is used. 37. The ferroelectric memory device according to any one of items 37) to 39.

(42) In the ferroelectric memory device, the memory management function controls information erasing, writing, and reading functions with respect to memory cells in blocks or sector units in the memory unit, and in each sector unit. The ferroelectric memory device according to the item (41), which has a directory (address information) and keyword information.

(43) In the ferroelectric memory device, the control circuit is composed of an MPU, and controls the erasing, writing, and reading functions of information with respect to memory cells in block or sector units in the memory section, The ferroelectric memory device according to the item (40), which has a directory (address information) and keyword information in sector units.

Therefore, according to the above items (41) to (43), the directory manages the use status of the sector and the block, and the memory becomes easy to use.

Therefore, a large capacity memory can be used easily.

(44) A ferroelectric thin film capacitor sandwiched by a pair of electrodes has a storage cell, and the storage cell is set to the first polarization state of the two states of spontaneous polarization. A first pulse having a voltage Ve larger than the coercive voltage Vc of the dielectric thin film is applied to polarize, and then a second voltage Vw having an absolute value smaller than Ve having a polarity opposite to the applied voltage Ve is applied. Pulse is applied to store information in a partially polarized state in which a domain having a polarization in the first direction and a domain having a second polarization in the opposite direction to the first direction are mixed. In the dielectric memory device,
A memory unit mounted on one chip or a plurality of chips,
Antenna, tuning circuit, detection circuit, demodulation circuit, oscillation circuit,
A ferroelectric memory device comprising a modulation circuit and a control circuit, which is a removable memory device for exchanging signals by radio waves, for example, a memory card.

(45) The ferroelectric memory device is a removable memory device having a circuit for generating voltage and power for driving from a received radio wave. 2. A ferroelectric memory device according to item.

(46) In the ferroelectric memory device, it is a removable memory device in which a portion other than the antenna is mounted on one chip and information signals are exchanged by radio waves. ) The ferroelectric memory device according to any one of items (45).

(47) The ferroelectric memory device described in any one of the paragraphs (44) to (45), wherein the antenna is mounted on the one chip. Body memory device.

(48) In the ferroelectric memory device, the radio wave is a removable memory device that is a microwave to a millimeter wave, for example, a memory card. (44), (45) Item 14. The ferroelectric memory device according to any one of items 47.

Therefore, according to the above items (44) to (48), this ferroelectric system enables low voltage, low power and large capacity memory, and enables large amount of data communication by radio waves. It is suitable for various applications. This advantage can be brought out by using radio frequency (RF) circuits.

Therefore, a data carrier capable of a large amount of data communication by radio waves becomes possible.

(49) In the ferroelectric memory device, a memory card capable of exchanging data unique to an individual by radio waves to a computer provided with an RF antenna or a microwave antenna including a signal modulation / demodulation circuit. The ferroelectric memory device as described above in (44).

(50) In the ferroelectric memory device, the personal reference number can be read from the memory card that can be exchanged by radio waves, and the environment can be automatically set in the computer. Dielectric memory device.

Therefore, according to the items (49) and (50), a large amount of data communication by radio waves (RF) and a large amount of memory are suitable for a personal data card of a computer. Personal hard desks have sometimes been difficult in the past,
This is possible because this method is used.

Therefore, the personal database enables any computer to be used as if it were its own machine.

(51) In the ferroelectric memory device, provided with an RF antenna or a microwave antenna including a signal modulation / demodulation circuit, is an automatic door lock function mounted on a vehicle, a vehicle-mounted computer for controlling traveling, and a navigation system. The ferroelectric memory device according to (44) above, which is a memory card capable of exchanging data peculiar to an individual with respect to a system including the above.

Therefore, according to the item (51), a large amount of data communication by radio waves (RF) and a large amount of memory are suitable for a personal data card of an automobile. Large data and C
By using this method, it is possible to retain the ID, security, and dedicated data, which were difficult for the PU in the past.

Therefore, the ID, security and exclusive data can be held by using this method.

(52) In the ferroelectric memory device, provided with an RF antenna or a microwave antenna (58) including a signal modulation / demodulation circuit, mounted on the automobile, has an automatic door lock function, and ID recognition for identifying a driver. Device and
The ferroelectric memory device according to item (44), which is a memory card capable of exchanging data peculiar to an individual with a system including a position recognition device by radio waves.

Therefore, according to the item (52), a large amount of data communication by radio waves (RF) and a large amount of memory are suitable for the personal ID data card of the security system. Large-capacity data and CPU, which was difficult in the past,
Security and exclusive data retention are possible using this method.

Therefore, the ID, security and exclusive data can be held by using this method.

(53) In the ferroelectric memory device, data unique to an individual is exchanged by radio waves with respect to an automatic tailor device (automatic deposit / withdrawal device) provided with an RF antenna or a microwave antenna including a signal modulation / demodulation circuit. The ferroelectric memory device according to the item (44), which is a memory card that can be used.

Therefore, according to the item (53), a large amount of data communication by radio waves (RF) and a large amount of memory are suitable for a personal ID data card of a personal information system. With large volume data and CPU, ID, security, personal account, health, business, telephone,
Retention of fax-specific data is possible using this method.

Therefore, it becomes possible to personally own all kinds of information using this method.

(54) In the ferroelectric memory device, an RF antenna including a signal modulation / demodulation circuit or a microwave antenna is provided, and a system including a home-use television, a game device and a home-use data terminal is unique to an individual. The ferroelectric memory device according to item (44), which is a memory card capable of exchanging data by radio waves.

Therefore, according to the item (54), a large amount of data communication by radio waves (RF) and a large amount of memory are suitable for the personal ID data card of the personal information system. With large volume data and CPU, ID, security, personal account, health, business, telephone,
Retention of fax-specific data is possible using this method.

Therefore, it becomes possible to personally own all kinds of information using this method.

(55) Spontaneous polarization (polarization) having a memory cell of a ferroelectric thin film capacitor sandwiched by a pair of electrodes.
The first polarization state of the two states is polarized by applying a first pulse having a voltage Ve larger than the coercive voltage Vc of the ferroelectric thin film, and then the polarization is reversed from the applied voltage Ve. A domain having a polarization in the first direction and a domain having a second polarization opposite to the first direction are applied by applying a second pulse having a voltage Vw having an absolute value smaller than the polarity Ve. In a ferroelectric memory for storing information in a partially polarized state in which and are mixed, a memory unit, a control unit, a high-speed light modulator, a high-speed circuit photodiode, and a photovoltaic cell mounted on one chip or a plurality of chips. A removable memory device comprising, for example, a memory card, which is a ferroelectric memory device.

Therefore, according to the above item (55), a large-capacity memory card is possible with this method, but the use of electrode terminals causes problems such as size, water resistance, environment resistance, and the reliability of the terminals. It does not have good performance, so it uses a high-speed optical interface.

Therefore, there are problems such as size, water resistance, environment resistance, etc., and it becomes possible to provide a memory card which clears all the reliability of the terminals, and no battery is required.

(56) It has a memory cell of a ferroelectric thin film sandwiched by a pair of electrodes, and has a spontaneous polarization (polarization) of 2.
A first polarization state out of the two states is applied with a first pulse having a voltage Ve larger than the coercive voltage Vc of the ferroelectric thin film to polarize the ferroelectric thin film, and then a polarity opposite to the applied voltage Ve is applied. A domain having a polarization in the first direction and a domain having a second polarization opposite to the first direction are applied by applying a second pulse having a voltage Vw having an absolute value smaller than Ve. In a ferroelectric memory that stores information in a mixed partial polarization state, the memory cells are arranged in a simple matrix at intersections of upper electrode lines and lower electrode lines that are orthogonal to each other, and these memory cells are oxidized by silicon oxide. A ferroelectric memory device formed on a region including a film, wherein a peripheral circuit is formed outside a region where a memory cell is arranged. (57) In the ferroelectric memory device, the peripheral circuit is formed in the periphery of a region where the memory cell is arranged, in the ferroelectric memory device described in (56).

(58) In the ferroelectric memory device, the upper electrode and the lower electrode are connected to a peripheral circuit device by a newly provided third electrode. 57) The ferroelectric memory device according to any one of 57).

Therefore, according to the above items (55) to (58), the present method shows the configuration and process of the actual production of the present memory, with a simple configuration, a loose processing rule, and a small number of masks. Memory can be realized.

(59) It has a memory cell of a ferroelectric thin film sandwiched by a pair of electrodes, and has a spontaneous polarization (polarization) of 2.
A first polarization state out of the two states is applied with a first pulse having a voltage Ve larger than the coercive voltage Vc of the ferroelectric thin film to polarize the ferroelectric thin film, and then a polarity opposite to the applied voltage Ve is applied. A domain having a polarization in the first direction and a domain having a second polarization opposite to the first direction are applied by applying a second pulse having a voltage Vw having an absolute value smaller than Ve. In a ferroelectric memory that stores information in a mixed partial polarization state, active devices are arranged on a semiconductor substrate, and the memory cells are arranged above each other on a region where wiring is performed between the active devices. A ferroelectric memory device characterized by being stacked and arranged in a simple matrix form at intersections of upper electrode lines and lower electrode lines which are orthogonal to each other.

(60) In the ferroelectric memory device, the peripheral circuit and the control circuit are formed as active devices on the semiconductor substrate, and the ferroelectric memory according to the item (59). apparatus.

(61) In the ferroelectric memory device, the central processing unit including the peripheral circuit and the control circuit and the digital signal processing device are formed as active devices on a semiconductor substrate. 59. The ferroelectric memory device according to the item 59).

Therefore, according to the above-mentioned items (59) to (61), the present method shows the configuration and process of the actual production of the present memory, and the simple configuration, the loose processing rule, and the small number of masks are used. High-density memory can be realized.

(62) In the ferroelectric memory device, the ferroelectric memory device according to any one of (59) to (61), wherein at least two pairs of upper electrodes and lower electrodes are laminated. Dielectric memory device.

Therefore, according to the above (62), the present method shows the configuration and process of the actual production of the present memory, which has a simple configuration, a loose processing rule, a small number of masks and an extremely high density memory. Can be realized.

[0228]

As described above in detail, according to the present invention, a sense circuit combining a capacitance addition feedback circuit capable of reading a small ΔC / C without a voltage change of the data line and a comparison read of a reference cell is used to obtain information. It is possible to provide a non-destructive ferroelectric memory having a non-coherent property at the time of writing and a non-coherent property at the time of reading, capable of realizing non-destructive reading, and suitable for large scale, and a driving method thereof.

[Brief description of drawings]

FIG. 1 is a diagram showing an example of a circuit configuration of a ferroelectric memory as a first embodiment.

FIG. 2 is a diagram for explaining an outline of a ferroelectric memory device according to the present invention.

FIG. 3 is a diagram for explaining an operation of the ferroelectric memory device shown in FIG.

FIG. 4 is a diagram for explaining the operation of the ferroelectric memory device shown in FIG.

FIG. 5 is a diagram showing a block configuration of a ferroelectric memory device including memory cell mats arranged in a simple matrix.

FIG. 6 is a diagram showing an example of a configuration of a ferroelectric memory device as a second embodiment.

FIG. 7 is a diagram showing an example of a configuration of a ferroelectric memory device as a third embodiment.

FIG. 8 is a diagram illustrating a configuration example of a modified example of the third embodiment.

FIG. 9 is a diagram showing an example of a configuration of a ferroelectric memory device as a fourth embodiment.

FIG. 10 is a diagram for explaining the configuration and operation of the ferroelectric memory device as the fifth embodiment.

FIG. 11 is a diagram showing an example of a configuration of a ferroelectric memory device as a sixth embodiment.

FIG. 12 is a diagram showing an example of a configuration of a ferroelectric memory device as a seventh embodiment.

FIG. 13 is a diagram showing a modified example of the seventh embodiment.

FIG. 14 is a diagram showing an example of a configuration of a ferroelectric memory device as an eighth embodiment.

FIG. 15 is a diagram showing a modified example of the eighth embodiment.

FIG. 16 is a diagram showing an example in which the eighth embodiment is applied to a memory card.

FIG. 17 is a diagram showing an example of a configuration of a ferroelectric memory device as a ninth embodiment.

FIG. 18 is a diagram showing an example of a configuration of a ferroelectric memory device as a tenth embodiment.

FIG. 19 is a diagram showing an example of a configuration of a ferroelectric memory device as an eleventh embodiment.

FIG. 20 is a diagram showing an example of a block configuration of a ferroelectric memory device as a twelfth embodiment.

FIG. 21 is a flow chart for explaining the outline and operation of the ferroelectric memory device as the thirteenth embodiment.

FIG. 22 is a diagram showing an outline of a ferroelectric memory device as a fourteenth embodiment.

FIG. 23 is a diagram schematically showing a ferroelectric memory device as a fifteenth embodiment.

FIG. 24 is a diagram showing an outline of a ferroelectric memory device as a 16th embodiment.

FIG. 25 is a diagram schematically showing a ferroelectric memory device as a seventeenth embodiment.

FIG. 26 is a diagram showing a configuration of a ferroelectric memory device as an eighteenth embodiment.

FIG. 27 is a diagram showing a configuration of a ferroelectric memory device according to a nineteenth embodiment viewed from above.

FIG. 28 is a diagram showing a cross-sectional structure in a manufacturing process of a ferroelectric memory device as the nineteenth embodiment.

FIG. 29 is a diagram showing a configuration and a cross-sectional structure of a ferroelectric memory device according to a twentieth embodiment viewed from above.

FIG. 30 is a view showing the cross-sectional structure of the ferroelectric memory device of the twenty-first embodiment.

FIG. 31 is a diagram showing a circuit configuration of a conventional ferroelectric memory.

FIG. 32 is a diagram showing a schematic configuration of a conventional ferroelectric memory.

FIG. 33 is a diagram showing an example of capacitance-voltage characteristics of a ferroelectric.

[Explanation of symbols]

1 ... Ferroelectric memory cell, 2, 12 ... Selection switch,
3, 13 ... Erase pulse input terminal, 4, 14 ... Write pulse input terminal, 5, 15 ... Read pulse input terminal,
6, 16 ... Changeover switch (for discharging), 7, 10, 17
... Differential amplifier, 8,18 ... Feedback capacitance element, 11 ... Dummy cell.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical indication location H01L 21/8242

Claims (3)

[Claims] 1. A ferroelectric memory using a memory cell for storing information according to a state of spontaneous polarization (polarization) of a ferroelectric thin film sandwiched by a pair of electrodes, comprising: A first terminal for applying a first pulse for erasing stored information having a voltage Ve higher than the coercive voltage Vc, and an absolute value smaller than Ve having a polarity opposite to the applied voltage Ve to the storage cell. A second terminal for applying a second pulse for writing information, which has a voltage Vw, and an absolute value which is less than the voltage Ve to the memory cell,
Any one of the first to third terminals, which has a positive or negative voltage Vr and which applies a third pulse for nondestructively reading memory information; A first selection switch means for selecting, and a feedback capacitor connected to the output side of the memory cell via a first changeover switch means whose one end is grounded. 1. A differential amplifier of No. 1 and a ferroelectric thin film equivalent to the memory cell, which stores the same information as the information stored in the memory cell and is connected to a reference dummy cell for arbitrarily performing comparison reading. A fourth pulse signal to which a pulse signal equivalent to the first to third pulse signals is applied
To a sixth terminal, a second selection switch means for selecting any one of the fourth to sixth terminals and applying the selected dummy cell to the reference dummy cell, and an output terminal of the reference dummy cell having one end grounded. Two
Second differential amplifier having a feedback capacitor connected through the changeover switch means and having its output fed back, the first differential amplifier and the second differential amplifier And a third differential amplifier that outputs a difference between the storage cell and the reference cell by the first and second selection switch means and the first and second changeover switch means. Erase / write / read information to / from the dummy cell,
The memory cell and the reference dummy cell are polarized by applying a first pulse of the voltage Ve to a first polarization state of two states of spontaneous polarization of the ferroelectric thin film,
Then, a second pulse having the voltage Vw is applied to mix partial domains having a domain having a polarization in the first direction and a domain having a second polarization in the opposite direction to the first direction. A nondestructive ferroelectric memory characterized in that information is stored in a state, and memory information is read out nondestructively by applying a third pulse of the voltage Vr. 2. A ferroelectric thin film having a plurality of memory cells for storing information according to a spontaneous polarization state of a ferroelectric thin film sandwiched by a pair of electrodes and at least one reference dummy cell. Of the spontaneous polarization (polarization) of the ferroelectric thin film to the first polarization state of the two states.
a first pulse having a voltage Ve greater than c is applied to polarize, and then a second pulse having a voltage Vw having an absolute value smaller than Ve having a polarity opposite to the applied voltage Ve is applied; A ferroelectric memory for storing information in a partially polarized state in which a domain having a polarization in the first direction and a domain having a second polarization in a direction opposite to the first direction are mixed, A memory cell and the reference dummy cell form a memory cell mat arranged in a simple matrix between a pair of stripe electrodes orthogonal to each other on a semiconductor chip, and the memory cell mat is formed on the semiconductor chip by an arbitrary number of memory cells. The memory cell mat is divided into one or more sectors, and at least one or more reference dummy cells are placed in the sector. Information may nondestructive type ferroelectric memory characterized in that it is erased collectively. 3. A ferroelectric thin film sandwiched by a pair of electrodes, comprising a memory cell for storing information according to a state of spontaneous polarization (polarization) of the ferroelectric thin film. A first pulse having a voltage Ve larger than the coercive voltage Vc of the ferroelectric thin film is applied to the first polarization state of the states to polarize the first thin film, and then Ve having a polarity opposite to the applied voltage Ve is applied. A domain having a polarization in the first direction and a domain having a second polarization opposite to the first direction are mixed by applying a second pulse having a voltage Vw having a smaller absolute value. In a ferroelectric memory that stores information in the partially polarized state described above, the ferroelectric memory includes a memory unit having a memory cell, an antenna, and a tuning circuit formed on one semiconductor chip or a plurality of semiconductor chips. , Detection circuit, recovery Circuit, an oscillation circuit is composed of a modulation circuit, and a control circuit, a non-destructive type ferroelectric memory, wherein the communication and processing of information using radio waves, a removable memory device.