JP2002026277A - Memory device and method for driving the same - Google Patents

Memory device and method for driving the same

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Publication number
JP2002026277A
JP2002026277A JP2000200276A JP2000200276A JP2002026277A JP 2002026277 A JP2002026277 A JP 2002026277A JP 2000200276 A JP2000200276 A JP 2000200276A JP 2000200276 A JP2000200276 A JP 2000200276A JP 2002026277 A JP2002026277 A JP 2002026277A
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JP
Japan
Prior art keywords
direction
linear electrodes
memory device
memory
material layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000200276A
Other languages
Japanese (ja)
Inventor
Satoshi Inoue
聡 井上
Original Assignee
Seiko Epson Corp
セイコーエプソン株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, セイコーエプソン株式会社 filed Critical Seiko Epson Corp
Priority to JP2000200276A priority Critical patent/JP2002026277A/en
Publication of JP2002026277A publication Critical patent/JP2002026277A/en
Application status is Pending legal-status Critical

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Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic

Abstract

(57) Abstract: A memory device having a highly integrated layer structure with a simplified circuit structure. SOLUTION: An organic memory material layer is laminated, a plurality of linear electrodes are arranged in parallel in one direction along one surface of each organic memory material layer, and a plurality of linear electrodes are arranged along the other surface. The memory device has a simple matrix structure in which memory cells are formed at positions where both linear electrodes intersect with the linear electrodes in the Y direction perpendicular to the linear electrodes in the direction and intersect the organic memory material layer. Further, the memory cells at the corresponding positions in the adjacent organic memory material layers share at least one of the linear electrodes arranged in the X direction and the linear electrodes arranged in the Y direction.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a memory device having a layer structure, and more particularly to a ferroelectric memory device having a simple matrix structure in which ferroelectric layers are stacked.

[0002]

2. Description of the Related Art Ferroelectric materials have a very large relative dielectric constant of several hundreds to several thousands, and if they are used as insulating films of capacitors, small-area, large-capacity capacitors suitable for large-scale integrated circuits can be obtained. Since the ferroelectric material has spontaneous polarization and can reverse the polarization direction by the action of an external electric field, a nonvolatile memory can be manufactured using this characteristic. As a ferroelectric, PZT having a perovskite crystal structure is used.
(Lead, zirconium, titanium oxide), PLZT, bulk BTO, VDF (vinylidene fluoride), TrF
E (trifluoroethylene) and the like are known.

[0003] The polarization characteristics of the strong derivative material exhibit hysteresis characteristics as shown in FIG. When the voltage E is applied to the ferroelectric material to cause polarization, even if the voltage is returned to “0”, the point 5
Since there is a characteristic that the state of the remanent polarization value ± Pr indicated by 00 or 502 is maintained, the digital signals “1” and “0” correspond to each of the remanent polarization values indicated by the point 500 or 502. By doing so, it can function as a nonvolatile memory.

Specifically, by applying a voltage V (saturation voltage) of a sufficient magnitude exceeding the threshold voltage Vc,
"0" is recorded, and a voltage -V (saturation voltage) of a sufficient magnitude exceeding the threshold voltage -Vc is applied, and the state of "1" is recorded. When the voltage V 1 is applied while the state of “1” is recorded, the polarization state changes from the point 500 to the point 502. At this time, charges corresponding to the two polarization differences 2Pr are emitted. On the other hand, when in the state of “0”,
Since the polarization state changes from point 502 to point 501 to point 502, the polarization difference is “0”. Therefore, by detecting the amount of charge generated by the application of the voltage V, it is possible to read whether the storage state is “1” or “0”.

FIG. 8 is a diagram showing a specific configuration of a simple matrix structure among memory devices using the above-mentioned polarization. In this memory device, a pair of linear lower electrodes 601 and upper electrodes 603 crossing each other are arranged on both surfaces of a substrate 600 serving as a support.
A ferroelectric layer 602 is provided between 1 and 603, and a memory cell is formed at an intersection where the upper and lower linear electrodes 601 and 603 overlap in the stacking direction. Here, the laminating direction means a direction in which the layers are laminated in a manufacturing process, such as a substrate / lower electrode / ferroelectric layer / upper electrode, and corresponds to a vertical direction in the drawing.

FIG. 9 shows an equivalent circuit when the simple matrix structure is a 3 × 3 matrix. FIG. 9A is a memory cell layout diagram, and FIG. 9B is an equivalent circuit diagram. FIG.
The memory cells 701 to 709 formed at the intersections of the upper and lower linear electrodes 601 and 603 in FIG. 9A correspond to the capacitors having the same reference numerals in FIG.

As references, ZY Hau,
A. new material f by GR Chen
or optical, electrical th
infilm memories ", Vacuum 4
3, No. 11, pp. 1019-1023 (199
2), Kiyoshi Nishimura, Takaaki Fuchigami, Kazuhiro Senba, "Development of a ferroelectric hysteresis characteristic model and its application", IEICE Transactions J80-C-II, [7], pp. 229-2
35 (1997) is known.

On the other hand, there is known a memory device having a layered structure in which organic memory material layers such as ferroelectric layers are stacked in order to increase the storage capacity. FIG. 10 shows an example of a memory device having a simple matrix structure and a layer structure. As shown, each organic memory material layer 800 comprises an insulating layer 80.
1 are provided.

[0009]

In the conventional stacked memory device, since each organic memory material layer has an independent structure, when the number of organic memory material layers increases, the number of electrode layers and circuits related thereto doubles. As a result, there is a problem that the circuit configuration becomes complicated. For example, when ten organic memory material layers are stacked, two upper and lower electrode layers are required for each organic memory material layer, so that the entire memory device requires twenty layers.

Further, when the number of the electrode layers increases, the number of processes for forming the electrode layers naturally increases, so that the manufacturing process of the memory device becomes complicated, which causes a problem that the cost increases.

The present invention has been made in order to solve such a conventional problem, and an object of the present invention is to provide a highly integrated stacked memory device having a simple circuit configuration.

[0012]

A memory device according to the present invention has an organic memory material layer laminated thereon, a plurality of memory cells formed in each organic memory material layer, and an organic memory material layer sandwiched between each memory cell. A memory device provided with a pair of electrodes, wherein memory cells at corresponding positions in adjacent organic memory material layers share at least one of the pair of electrodes. This reduces the number of electrodes and simplifies the circuit configuration.

In the memory device according to the present invention, an organic memory material layer is laminated, a plurality of linear electrodes are arranged in parallel in one direction along one surface of each organic memory material layer in the X direction, and a plurality of linear electrodes are arranged along the other surface. Memory having a simple matrix structure in which the linear electrodes are arranged in parallel in the Y direction orthogonal to the linear electrodes arranged in the X direction, and memory cells are formed at positions where both linear electrodes intersect with the organic memory material layer interposed therebetween. The device, wherein memory cells at corresponding positions in adjacent organic memory material layers share at least one of the linear electrodes arranged in the X direction and the linear electrodes arranged in the Y direction. It is characterized by. As a result, the number of electrodes is reduced, and the circuit configuration can be simplified and made compact. As a result, high integration can be achieved.

With respect to the sensor circuit, one sensor circuit for measuring a voltage for each of the linear electrodes connected in the X direction or the linear electrodes connected in the Y direction is connected. It is possible to consider the form. In such an embodiment, since one sensor circuit is shared by two layers, the circuit configuration can be simplified.

Further, for example, two sensor circuits for measuring a voltage for each of the linear electrodes arranged in the X direction or the linear electrodes arranged in the Y direction are connected. Is possible. Further, for example,
Regarding the linear electrodes arranged in parallel in the X direction and the linear electrodes arranged in parallel in the Y direction, a form in which one sensor circuit for measuring a voltage is connected to each linear electrode is considered. In these embodiments, one sensor circuit can be assigned to each layer, so that stable reading can be performed.

In the memory device of the present invention, the dielectric layer can be formed by a sol-gel method, a MOD method, a sputtering method or a printing method.

The memory device of the present invention can be used as a memory of an information processing device. The information processing device refers to a device including a CPU such as a computer and a printer, a memory, and a data input / output device.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (Description of Structure) Next, the structure of a memory device according to the present invention will be described with reference to the drawings.

FIG. 1 is a schematic perspective view of a memory device according to the present invention, FIG. 2A is a schematic view of an XZ section, and FIG.
Is a schematic diagram of an XY cross section.

As shown in FIGS. 1 and 2, a memory device 1 according to the present invention has organic memory material layers 100 to 107 laminated thereon, and linear electrodes 1 above and below each organic memory material layer.
08 is arranged in the X direction, and the linear electrodes 109 are arranged in the Y direction. Hereinafter, the linear electrodes arranged in the X direction are referred to as X direction linear electrodes, and the linear electrodes arranged in the Y direction are referred to as Y direction linear electrodes. In each organic memory material layer, X
It has a simple matrix structure in which memory cells 110 are formed at positions where the direction linear electrodes 108 and the Y direction linear electrodes 109 intersect. Note that a decoder is connected to each linear electrode so that a predetermined voltage can be applied.

Although FIGS. 1 and 2 show eight organic memory material layers, the number of organic memory material layers can be determined according to the design. The number of linear electrodes in each layer is 1
Although it is determined according to the number of memory cells in the layer, in the figure, the X-direction linear electrodes and the Y-direction linear electrodes are both shown as four.

Here, as the organic memory material, for example, a copolymer of vinylidene fluoride and trifluoroethylene can be used.

As can be seen from FIGS. 1 and 2, in the memory device of the present invention, at least one of the X-direction linear electrodes 108 and the Y-direction linear electrodes 109 It is structured to share one. For example, the layer 103 and the layer 104 share an X-direction linear electrode, and the shared X-direction linear electrode functions as an upper electrode for the layer 103 and functions as a lower electrode for the layer 104. ing. By adopting a configuration in which the linear electrodes are shared in this manner, the number of the linear electrodes can be reduced to about 比 べ compared with the conventional memory device,
The circuit configuration can be simplified and compact. As a result, the degree of integration of the memory can be improved. (Arrangement of Sensor Circuit) FIGS. 3, 4 and 5 are views showing an example of the arrangement of the sensor circuit in the present invention. here,
The sensor circuit refers to a circuit for reading information stored in a memory cell, and includes a sense amplifier, a decoder, and the like.

In the example shown in FIG. 3, one sensor circuit for measuring a voltage is connected to the X-direction linear electrode of each layer. In such a configuration, one sensor circuit corresponds to two organic memory material layers. For example, for a memory cell included in the layer 103 and a memory cell included in the layer 104, the sensor circuit 3
00 performs a reading process. Thus, by adopting a configuration in which the sensor circuit is shared by the two layers, the circuit configuration can be greatly simplified. In addition,
The sensor circuit may be provided on the Y-direction linear electrode instead of the X-direction linear electrode.

In the example shown in FIG. 4, a sensor circuit for measuring a voltage is provided at both ends of the linear electrodes of each layer in the X direction.
Are connected. In such a configuration,
One sensor circuit corresponds to one organic memory material layer. For example, readout processing is performed by the sensor circuit 300 on the memory cells included in the layer 103 and by the sensor circuit 301 on the memory cells included in the layer 104. In this manner, by providing an independent sensor circuit for each layer, detection stability in the sensor circuit can be improved. For example, the linear electrode to which the sensor circuit on the left side of the drawing is connected is fixed to the upper electrode side with respect to the layer (for example, the sensor circuit 300 is
3 is connected to the upper electrode side, and the linear electrode to which the sensor circuit on the right side of the figure is connected is fixed to the lower electrode side with respect to the layer (for example, the sensor circuit 301 is connected to the lower electrode side of the layer 104). This is because the sensor circuit always has only one type of voltage, and the reference voltage can be kept constant. In addition, instead of the X-direction linear electrode, Y
You may comprise so that a sensor circuit may be provided in a direction linear electrode.

In the example shown in FIG. 5, one sensor circuit for measuring a voltage is connected to the X-direction linear electrode and the Y-direction linear electrode of each layer. In such a configuration, one sensor circuit corresponds to one organic memory material layer. For example, the sensor circuit 300 applies a memory cell included in the layer 103 to the layer 10
4 is read out by the sensor circuit 301. In this example as well, similar to the example shown in FIG. 4, the configuration in which an independent sensor circuit is provided for each layer can improve the detection stability in the sensor circuit. (Write / Read Operation) FIG. 6 is a circuit diagram showing the entire configuration of a memory device according to the present invention, including peripheral circuits. In the present embodiment, one Z-direction decoder 400, 5
Four X-direction decoders 401 and four Y-direction decoders 40
2 is provided. The Z-direction decoder is for specifying the position of the access layer, and is connected to each X-direction decoder and Y-direction decoder. Also, each X direction decoder,
The Y-direction decoder is connected to each of the X-direction linear electrodes and the Y-direction linear electrodes arranged in layers.

Hereinafter, the write / read operation of the memory device will be described assuming that the case where the remanent polarization value of the ferroelectric is -Pr is "1" and the case where it is Pr is "0".

First, the write operation will be described. A memory cell 403 to be written is selected by a Z-direction decoder, an X-direction decoder, and a Y-direction decoder based on an externally supplied address signal. Each decoder is supplied with H, L, P, Q voltage signals from a voltage generator. For example, the H and L voltage signals are output to the X-direction linear electrode and the Y-direction linear electrode corresponding to the selected memory cell 403, and the P and Q voltage signals are output to the other X-direction linear electrodes in the access layer. , Y-direction linear electrodes. For linear electrodes corresponding to layers different from the access layer, for example, P and Q voltage signals are output to predetermined linear electrodes based on a pattern determined by a relative positional relationship with the access layer. Is done.

Here, in the X-direction decoder and the Y-direction decoder corresponding to the access layer, the polarities of the supplied voltage signals are always opposite to each other. That is, when "1" is written to the selected memory cell 403, the voltage signal L is applied to the X-direction decoder and the voltage signal H is applied to the Y-direction decoder.
Is supplied, and when "0" is written, the voltage signal H is supplied to the X-direction decoder and the voltage signal L is supplied to the Y-direction decoder.

As a result, a voltage + (HL) or-(HL) is applied to the selected memory cell 403, and the ferroelectric layer in the memory cell is polarized. After polarization, the residual polarization value -Pr or Pr is maintained even when no voltage is applied, so that "1" or "0" can be stored.

Next, the read operation will be described. At the time of reading, the voltage signal H is always supplied to the X-direction decoder and the voltage signal L is supplied to the Y-direction decoder corresponding to the access layer. As a result, the voltage + (HL) is applied to the selected memory cell, and when the recording state is "1", that is, when the remanent polarization value is -Pr, the polarization state is -Pr.
To Pr. On the other hand, when the storage state is “0”, that is, when the remanent polarization value is Pr, the remanent polarization value remains Pr because the polarization state temporarily increases from Pr and returns to Pr.

Therefore, only when the recording state is "1",
The polarization state is reversed from -Pr to Pr, and charges are released to generate a reversal current. When the recording state is "0", a small amount of current is generated, but the current is sufficiently smaller than the reversal current. The inverted current is converted to a reference voltage in the sense amplifier 404 after voltage conversion.
Is read out via the. (Other Modifications) The memory device manufactured according to the present invention can be used for all information processing devices having a memory, for example, an internal storage device of a computer, a memory stick, a memory card, and the like.

The present invention is not limited to the above embodiments but can be applied in various modifications.

[0034]

As described above, in the memory device according to the present invention, in a memory device having a layered structure in which organic memory material layers are stacked, at least one of the electrodes sandwiching each organic memory material layer extends in the layer direction. Since the structure is shared by the adjacent organic memory material layers, the number of electrodes is reduced, the circuit configuration is simplified, and a highly integrated memory device can be realized.

[Brief description of the drawings]

FIG. 1 is a schematic perspective view of a memory device according to the present invention.

FIG. 2 is a schematic diagram illustrating a cross section of a memory device according to the present invention.

FIG. 3 is a diagram illustrating an example of an arrangement of a sensor circuit according to the present invention.

FIG. 4 is a diagram showing an example of an arrangement of a sensor circuit according to the present invention.

FIG. 5 is a diagram showing an example of an arrangement of a sensor circuit according to the present invention.

FIG. 6 is a diagram for explaining the overall configuration of the memory device of the present invention.

FIG. 7 is a diagram for explaining hysteresis characteristics of a ferroelectric material.

FIG. 8 is a diagram for explaining a memory device having a simple matrix structure.

FIG. 9 is a diagram showing an equivalent circuit of a memory device having a simple matrix structure.

FIG. 10 is an explanatory diagram of a memory device having a layer structure according to the related art.

[Explanation of symbols]

 100 to 107, 800 Organic memory material layer 108, 1081, 1082 X-direction linear electrode 109 Y-direction linear electrode 110, 200, 403 Memory cell 300, 301 Sensor circuit 400 Z-direction decoder 401 X-direction decoder 402 Y-direction decoder 404 Sense amplifier 801 insulation layer

Claims (7)

[Claims]
1. A memory device in which an organic memory material layer is laminated, a plurality of memory cells are formed in each organic memory material layer, and each memory cell is provided with a pair of electrodes sandwiching the organic memory material layer. A memory device, wherein memory cells at corresponding positions in adjacent organic memory material layers share at least one of the pair of electrodes.
2. An organic memory material layer is stacked, a plurality of linear electrodes are arranged in parallel in one direction along one surface of each organic memory material layer, and a plurality of linear electrodes are formed along the other surface. A memory device having a simple matrix structure in which memory cells are formed at positions where both linear electrodes are arranged in parallel with each other in the Y direction orthogonal to the linear electrodes arranged in the X direction and intersect the organic memory material layer. The memory cell at the corresponding position in the adjacent organic memory material layer has at least linear electrodes or Y
A memory device sharing one of the linear electrodes arranged in the direction.
3. A sensor circuit for measuring a voltage for each linear electrode is connected to either the linear electrodes parallel in the X direction or the linear electrodes parallel in the Y direction. The memory device according to claim 2, wherein:
4. Two sensor circuits for measuring a voltage for each of the linear electrodes are connected to either the linear electrodes arranged in the X direction or the linear electrodes arranged in the Y direction. The memory device according to claim 2, wherein:
5. A sensor circuit for measuring a voltage for each linear electrode is connected to each of the linear electrodes arranged in the X direction and the linear electrodes arranged in the Y direction. 3. The memory device according to claim 2, wherein:
6. The organic memory material is a copolymer of vinylidene fluoride and trifluoroethylene.
The memory device according to claim 5.
7. An information processing apparatus comprising the memory device according to claim 1 as a memory.
JP2000200276A 2000-06-30 2000-06-30 Memory device and method for driving the same Pending JP2002026277A (en)

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WO2004042737A1 (en) * 2002-11-04 2004-05-21 Advanced Micro Devices, Inc. Stacked organic memory devices and methods of operating and fabricating
EP1622433A1 (en) * 2004-07-28 2006-02-01 Endicott Interconnect Technologies, Inc. Circuitized substrate with an internal organic memory device
JP2006250928A (en) * 2005-02-10 2006-09-21 Semiconductor Energy Lab Co Ltd Semiconductor device
EP1717862A2 (en) 2005-04-28 2006-11-02 Semiconductor Energy Laboratory Co., Ltd. Memory device and semiconductor device
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US7551471B2 (en) 2006-04-28 2009-06-23 Semiconductor Energy Laboratory Co., Ltd. Memory element and semiconductor device
US7679107B2 (en) 2005-04-28 2010-03-16 Semiconductor Energy Laboratory Co., Ltd. Memory device that utilizes organic layer with a compound that can photoisomerize between conductive layers; at least one of which is light transmitting
US7713800B2 (en) 2005-11-09 2010-05-11 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
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US7829473B2 (en) 2007-03-26 2010-11-09 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing memory element
US7956352B2 (en) 2005-03-25 2011-06-07 Semiconductor Energy Laboratory Co., Ltd. Memory element comprising an organic compound and an insulator
US7960771B2 (en) 2005-08-12 2011-06-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device comprising a switching element and memory element having an organic compound
US7988057B2 (en) 2006-11-28 2011-08-02 Semiconductor Energy Laboratory Co., Ltd. Memory device and semiconductor device
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US8188461B2 (en) 2005-05-31 2012-05-29 Semiconductor Energy Laboratory Co., Ltd. Organic memory device
US8283724B2 (en) 2007-02-26 2012-10-09 Semiconductor Energy Laboratory Co., Ltd. Memory element and semiconductor device, and method for manufacturing the same
US8288197B2 (en) 2005-04-27 2012-10-16 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing a semiconductor device including a memory device comprising an insulator mixture region in a conductive layer
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WO2004042737A1 (en) * 2002-11-04 2004-05-21 Advanced Micro Devices, Inc. Stacked organic memory devices and methods of operating and fabricating
US7326643B2 (en) 2004-07-28 2008-02-05 Endicott Interconnect Technologies, Inc. Method of making circuitized substrate with internal organic memory device
US7253502B2 (en) 2004-07-28 2007-08-07 Endicott Interconnect Technologies, Inc. Circuitized substrate with internal organic memory device, electrical assembly utilizing same, and information handling system utilizing same
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US7988057B2 (en) 2006-11-28 2011-08-02 Semiconductor Energy Laboratory Co., Ltd. Memory device and semiconductor device
US9006741B2 (en) 2007-02-02 2015-04-14 Semiconductor Energy Laboratory Co., Ltd. Memory device in a programmed state having a memory layer comprising conductive nanoparticles coated with an organic film formed between two conductive layers
US8753967B2 (en) 2007-02-26 2014-06-17 Semiconductor Energy Laboratory Co., Ltd. Memory element and semiconductor device, and method for manufacturing the same
US8431997B2 (en) 2007-02-26 2013-04-30 Semiconductor Energy Laboratory Co., Ltd. Memory element and semiconductor device and method for manufacturing the same
US8283724B2 (en) 2007-02-26 2012-10-09 Semiconductor Energy Laboratory Co., Ltd. Memory element and semiconductor device, and method for manufacturing the same
US7829473B2 (en) 2007-03-26 2010-11-09 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing memory element
US8067316B2 (en) 2008-06-20 2011-11-29 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing memory element
US8361909B2 (en) 2008-06-20 2013-01-29 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing memory element
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