JPH0991959A - Dynamic semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a DRAM in which power consumption can be reduced while retaining a data through a simple structure by varying the precharge level thereby lengthening the refresh interval. SOLUTION: The DRAM comprises a memory cell including a plurality of word lines WL1, WL2,... and plurality of bit lines BL1, BL2,..., a VPR applying means (VPR generation circuit 16, a gate circuit 17) for bringing the potential of the plurality of bit lines BL1, BL2,... to a precharge level (VPR) prior to activation of the word lines, and a sense amplifier 13. In such a DRAM, the VPR applying means (VPR generation circuit 16, a gate circuit 17) lowers the precharge level gradually under data retaining state depending on the lowering of data retaining voltage thus retarding the lowering rate of voltage difference.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic semiconductor memory device (hereinafter referred to as "DRAM"), and more particularly to a DRAM in which power consumption is reduced by lengthening a refresh cycle in a data holding state. .

[0002]

2. Description of the Related Art DRAMs are widely used as semiconductor memory devices, and further reduction of power consumption is required. Hereinafter, MOS dynamic RAM (MOSDRA
M) will be described as an example. The DRAM has a configuration in which a plurality of word lines and a plurality of bit lines are vertically arranged and memory cells are arranged at intersections. Each memory cell is composed of one MOS transistor and a capacitive element (capacitor), one of the controlled electrodes (drain electrode) of the MOS transistor is connected to the corresponding bit line, and the other controlled electrode (source electrode). Is connected to the capacitive element, and the other end of the capacitive element is grounded. The control electrode (gate electrode) of the MOS transistor is connected to the corresponding word line. D
In the RAM, data is stored in correspondence with the potential level held by the capacitive element of the memory cell.

To access a memory cell, a pulse is applied to the word line to which the MOS transistor of the memory cell to be accessed is connected to make the MOS transistor conductive,
Connect the capacitive element to the bit line. In parallel with this, at the time of reading, the output of the sense amplifier connected to the bit line to be accessed is controlled to be output to the outside, and at the time of writing, the write amplifier connected to the bit line to be accessed is controlled to control the bit. Bring the line to the level corresponding to the write data. When the application of the pulse to the word line is completed, M
The OS transistor is turned off, and the potential level at that time is held in the capacitor.

At the time of writing, in the accessed state, the potential of "high (H)" or "low (L)" is applied to the bit line through the write amplifier according to the write data. Hereinafter, this potential will be referred to as a write potential “H” or “L”. As a result, the capacitive element of each memory cell holds the potential corresponding to the write data. At the time of reading, the potential held in the capacitor of the memory cell to be accessed is read to the bit line. The sense amplifier compares the potential of the bit line at this time with a predetermined value and changes it to a predetermined level according to the comparison result. The sense amplifier is
There are a configuration in which it is simply compared with the reference potential, a configuration in which it is compared with the potential read from the dummy cell, and a configuration in which two bit lines are paired and the potential between them is compared. Here, a configuration in which two bit lines are paired and the potentials between them are compared is targeted.

The sense amplifier comprises a differential amplifier and is connected to two bit lines. When reading, first set the two bit lines to the precharge level (VPR)
The write level is called "H" and "L". After that, when a pulse is applied to the word line to be accessed and the MOS transistor of the memory cell to be accessed becomes conductive, the bit line changes in accordance with the potential held in the capacitor. That is, if the memory cell to be accessed holds the “H” level, the potential of the bit line becomes higher than the precharge level, and if it holds the “L” level, the potential of the bit line is precharged. It becomes lower than the level. At this time, M which is conductive to the other bit line
Since the OS transistor is not connected, it remains at the precharge level, and the sense amplifier amplifies the difference to the write levels “H” and “L”. The result of this amplification is sent to the input / output circuit.

As described above, a large number of memory cells are connected to one word line, and the MOS transistor of the memory cell connected to the bit line which is not accessed is also turned on and held in the capacitive element. The potential of the bit line changes according to the potential. The potential difference between the bit lines is amplified by the sense amplifier connected to each bit line as described above, but is not sent to the input / output circuit. By this amplification, the potential of each bit line becomes the write level corresponding to the held data, and the potential of the corresponding write level is held again in each capacitive element.

FIG. 5 is a diagram showing a structure of a precharge level (VPR) generation circuit in a conventional DRAM.
In a conventional DRAM, VPR is constant, and as shown in FIG.
It has been generated in a circuit for resistance-dividing the power supply voltage VCC as shown in FIG. Although data is stored in the DRAM in association with the potential stored in the capacitive element of the memory cell, the potential stored in the capacitive element gradually decreases with the passage of time. This is because charges leak from the connection point between the MOS transistor and the capacitive element through the P-N junction of the MOS transistor. The potential stored in the capacitor continues to drop, and if it drops to a certain level or more, the data is lost. That is, "H" data changes to "L" data, and it becomes impossible to discriminate.

In order to prevent such a problem, an operation called a refresh operation is performed at regular intervals. In the refresh operation, a pulse is applied to the word line. As a result, the MOS transistor of the memory cell connected to the word line becomes conductive, and the potential of the bit line changes according to the potential held in the capacitor. The potential difference between the bit lines becomes a write level corresponding to the data that is amplified and held by the sense amplifier connected to each bit line, and each capacitance element holds the potential at the corresponding write level again. Thus, in the refresh operation, the memory cells connected to the word line are refreshed at the same time. Further, as is apparent from the above description, when a word line is accessed for writing or reading, all memory cells connected to the word line will be refreshed.

FIGS. 6A and 6B are views for explaining the voltage difference generated on the bit line at the time of reading. (1) shows the state before reading, (2) shows the state after reading, and (3) shows on the bit line. Indicates the voltage difference. Since a similar voltage difference is generated at the time of refreshing, the case of reading will be described here as an example. In FIG. 6, C-CELL is the capacitance of the capacitive element of the memory cell, C-BL is the capacitance of the entire bit line, VS
T (H) represents the potential held in the memory cell holding the “H” level write potential, and VPR represents the precharge level. Note that VST (L) shown later is “L”
The potential held in the memory cell holding the level write potential is shown. A parasitic capacitance exists between the bit line and the peripheral circuit element, and C-BL corresponds to this parasitic capacitance. As shown in (1) of FIG. 6, the MOS transistor TR is in a non-conducting (off) state before reading.
VST (H) is held in the capacitor C. In this state, before reading, VPR is applied to the bit line BL, so that C-BL holds VPR. As shown in (2) of FIG. 6, when the potential stored in the memory cell is read next time, the MOS transistor TR
Becomes conductive (ON), and the capacitive element C becomes the bit line BL.
Will be connected to. When the potential of the bit line in this state is VPR + ΔV, both C-CELL and C-BL hold VPR + ΔV. In the state (1) and the state (2), no charge is supplied to and from the outside, so the amount Q of the held charge is the same in the state (1) and the state (2). Therefore, the formula shown in (3) of FIG. 6 is established, and ΔV is represented by the illustrated formula.

Whether or not the potential difference ΔV generated on the bit line can be amplified to the “H” level by accessing the memory cell holding the “H” level at the read time depends on the capability of the sense amplifier circuit. The sense amplifier circuit mounted on a normal DRAM is usually difficult to read unless there is a voltage difference ΔV of several tens of mV or more, although it depends on variations in manufacturing and layout balance. Assuming that the minimum voltage difference required for this reading is V0, the refresh operation must be performed before the voltage difference ΔV drops below V0.

As shown in (3) of FIG. 6, ΔV is VST
It is proportional to the difference between (H) and VPR. Therefore, VST (H)
It is necessary to perform the refresh operation before the difference between VPR and VPR becomes aV0. FIG. 7 shows "H" in the DRAM.
It is a figure which shows the electric potential change of the memory cell which hold | maintained the electric potential of a level. The holding potential of the memory cell to which the potential of the write level “H” is applied decreases with the passage of time, and is restored to the write level “H” every refresh operation. In a conventional DRAM, VST (H) decreases and VST (H) decreases.
The refresh cycle is set so that the refresh operation is performed before the difference between (H) and VPR becomes aV0.

[0012]

In a device in which a DRAM is actually used, reading or writing is not performed on the DRAM for a long time, and the ratio of a state called a data holding state in which data up to that point is simply held is large.
Therefore, in order to reduce the power consumption of the device, it is important to reduce the power consumption in the data holding state. In the data holding state, only the refresh operation is performed, and power is mainly consumed in the refresh operation.
Therefore, one method of reducing the power consumption in the data holding state is to lengthen the refresh operation interval, reduce the number of refresh operations within a predetermined time, and reduce the average power consumption in the data holding state. is there.

To increase the interval between refresh operations,
The leakage current from the capacitive element is reduced, and the "H" level of the memory cell is reduced.
It is conceivable to slow down the rate of reduction of the level holding potential, but this requires a major improvement in the memory cell structure and is not easy. In the present invention, ΔV is VST
Paying attention to the fact that it is proportional to the difference between (H) and VPR, the VPR is decreased in accordance with the decrease in VST, so that the decrease rate of ΔV is slowed and the refresh cycle is lengthened.

[0014]

A dynamic semiconductor memory device of the present invention includes a plurality of word lines arranged in parallel, a plurality of bit lines arranged vertically to the plurality of word lines, and a plurality of word lines. Are arranged corresponding to the intersections of the bit lines and a plurality of bit lines, and are composed of a transistor and a capacitive element, the transistor is connected between the corresponding bit line and the capacitive element, and the control electrode of the transistor is connected to the corresponding word line. A memory cell being selected, VPR applying means for setting the potentials of a plurality of bit lines to a precharge level before activating a word line to which the memory cell to be accessed at the time of reading and refreshing data, Of the bit line connected to the memory cell that changes according to the data stored in the accessed memory cell at the time of reading and refreshing In a dynamic semiconductor memory device including a sense amplifier that compares a position with a potential of a bit line in which a connected memory cell is not activated and amplifies according to a comparison result, the VPR applying unit performs writing or reading. It is characterized in that the precharge level is gradually lowered in the absence of data retention.

It is desirable that the VPR applying means changes the precharge level at the same rate as the decrease of the potential of the capacitive element of the memory cell in which the high potential side of the logic data is written. The VPR applying means includes a dummy cell having a configuration and discharge characteristics similar to those of the memory cell, and a voltage divider circuit that divides the output potential of the dummy cell into about 1/2, and the dummy cell is added to the dummy cell every time the memory cell is refreshed. , By writing a potential corresponding to one of the logical data.

The VPR applying means includes a voltage holding means whose holding potential decreases at a predetermined speed, and a normal VPR generating circuit which applies the maximum value of the precharge level to the voltage holding means every refresh operation to the memory cell. It can also be realized by providing the output of the voltage holding means to the precharge level (VPR). FIG. 1 is a diagram for explaining the principle of the present invention. In FIG. 1, the level V held in the memory cell is
Since ST (L) is originally at a low level, VST
The decrease is almost negligible compared to (H) and is shown as being considered to be constant.

As shown in FIG. 1, in the conventional DRAM, since VPR is constant, a refresh operation is required until VST (H) drops to VPR + V0. That is, VST (H) -VPR is VST (H)
The refresh operation is required at the time when it becomes V0. On the other hand, in the present invention,
Since VPR drops at the same rate as VST (H), VST
(H) -VPR decreases at about half the speed of the conventional example. Therefore, the time until it becomes V0 is approximately doubled, and the refresh cycle can be lengthened accordingly.

Here, the minimum voltage V0 for the sense amplifier to accurately amplify the voltage difference ΔV generated on the bit line.
Is also necessary when reading from a memory cell holding the “L” level. To read the data of “H” level and “L” level most efficiently and stably,
It is desirable to set PR to an intermediate level between the potentials of the bit lines when the data of "H" level and "L" level is read. Therefore, during normal operation of writing and reading and immediately after the refresh operation, V
PR is set to an intermediate level between the writing levels of “H” and “L”. From this state, if VPR is changed so as to decrease by half of the amount of decrease in VST (H), VPR
Is set to an intermediate level between VST (H) and VST (L). In the initial state, VPR is half of VST (H), so the reduction rate is the same.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 2 shows a DRA according to an embodiment of the present invention.
It is the whole M block diagram. In FIG. 2, reference numeral WL
1, WL2, WL3, WL4 ... Are word lines, and BL
1, BL2, BL3, BL4 ... Are bit lines. The word line and the bit line are paired with two lines, and WL1 is shown in the figure.
And WL2, WL3 and WL4, BL1 and BL2, BL3 and BL4, respectively. A memory cell composed of a MOS transistor Tr and a capacitive element C is connected to the intersection of a pair of word line and bit line. Here, memory cells are arranged corresponding to the intersections of WL1 and BL1, and WL2 and BL2. The MOS transistor Tr and the capacitive element C of each memory cell are connected between the corresponding bit line and the ground, and the gate electrode of the MOS transistor Tr is connected to the corresponding word line. Sense amplifiers 13-1, 13-2, ... Are provided for each bit line pair. Reference numeral 11 is a row decoder which decodes a row address signal and applies a pulse to a word line to be accessed, 12 is a column decoder which decodes a column address signal and outputs a column selection signal, and 14 is a bit which is accessed according to the column selection signal. A select gate circuit that connects a sense amplifier connected to the line to the data input / output circuit 15, a VPR generation circuit 16 that generates a precharge level voltage (VPR), and a gate circuit 17 that applies the VPR to the bit line. Of these circuit configurations, the part excluding the VPR generation circuit 16 is the same as the conventional one, and the description thereof is omitted here.

FIG. 3 is a circuit diagram of the VPR generation circuit 16 of the first embodiment. In FIG. 3, reference numeral 21 is a dummy cell having a structure similar to that of the memory cell.
Reference numeral 2 is a MOS transistor that is rendered conductive when a “H” write potential is applied to the dummy cell 21, 23 is a current mirror type amplifier circuit that outputs a signal corresponding to the potential held in the dummy cell 21, and 24 is a current Numerals 25 and 26 are P-channel MOS transistors whose resistance value changes according to the output of the mirror type amplifier circuit 23.
It is a resistor that divides the potential generated at the source electrode of the channel type MOS transistor.

The dummy cell 21 has a structure similar to that of an actual memory cell, and is set so that the leakage current and the like are also the same. MOS transistor 2 for each refresh operation
A pulse is applied to 2 and the same potential as that of the memory cell is held. Here, it is shown that the power supply voltage VCC is applied. Therefore, the potential held in the dummy cell 21 changes like the memory cell. The potential is input to the current mirror type amplifier circuit 23, and the P channel type M
A potential corresponding to the potential held in the dummy cell 21 is generated at the source electrode of the OS transistor. If this is divided into ½ by the resistors 25 and 26 to obtain VPR, VPR becomes ½ of the potential held in the dummy cell 21. Therefore,
It changes like VPR in FIG.

FIG. 4 shows the VPR generation circuit 16 of the second embodiment.
It is a figure which shows the circuit diagram of. In FIG. 4, reference numeral 31
And 32 are resistors for dividing the power supply voltage VCC by resistance, and
Reference numeral 3 is a MOS transistor forming a transfer gate, 34 is a resistor connected between the source electrode of the MOS transistor 33 and the ground, and 35 is a MOS transistor.
It is a capacitive element connected between the source electrode of the transistor 33 and the ground. Resistors 31 and 32 are power supply voltage VCC
Is divided to generate a potential of 1/2 VCC. The transfer gate composed of the MOS transistor 33 is
Conducts when a refresh operation is performed. As a result, 1/2 VCC is held in the capacitive element 35. The holding potential of the capacitor 35 becomes VPR. Since the holding potential of the capacitive element 35 is discharged through the resistor 34, VPR decreases with the passage of time. Resistance of VPR is 34
The value of the resistor 34 is set so that the VPR becomes the desired degree of decrease shown in FIG.

[0023]

As described above, according to the present invention,
The refresh interval can be lengthened by a simple change of the precharge level without changing the process such as changing the structure of the memrial, and the power consumption in the data holding state can be reduced.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a diagram showing an overall configuration of an embodiment of the present invention.

FIG. 3 is a diagram illustrating a precharge level voltage (VP) of the first embodiment.
R) is a diagram of a generation circuit.

FIG. 4 shows a precharge level voltage (VP) of the second embodiment.
R) is a diagram of a generation circuit.

FIG. 5 is a diagram of a conventional precharge level voltage (VPR) generation circuit.

FIG. 6 is a diagram illustrating a voltage difference on a bit line that occurs during reading in a DRAM.

FIG. 7 is a diagram showing VPR showing a change in write data of “high (H)” level in a conventional example.

[Explanation of symbols]

 11 ... Row decoder 12 ... Column decoder 13-1, 13-2 ... Sense amplifier 14 ... Selection gate circuit 15 ... Data input / output circuit 16 ... VPR generation circuit 17 ... Gate circuit WL1 to WL4 ... Word lines BL1 to BL4 ... Bit lines Tr ... Transistor of memory cell C ... Capacitive element of memory cell

Claims (4)

[Claims] 1. A plurality of word lines (WL) arranged in parallel.
1, WL2, WL3, WL4, ...), and a plurality of bit lines (BL1, BL2, BL3, BL4, ...) arranged vertically to the plurality of word lines, and the plurality of word lines and the plurality of bits. The transistor (Tr) and the capacitor (C) are arranged corresponding to the intersections of the lines.
The transistor (Tr) is connected between the corresponding bit line (BL) and the capacitive element (C), and the control electrode of the transistor (Tr) is connected to the corresponding word line (WL). Before activating the connected memory cell and the word line to which the memory cell to be accessed is connected at the time of reading and refreshing data,
VPR applying means (16, 17) for setting the potentials of the plurality of bit lines (BL) to a precharge level (VPR), and data read and refresh depending on the data stored in the accessed memory cell. Dynamic semiconductor memory device comprising: a sense amplifier that amplifies the potential of a bit line connected to the memory cell that changes due to 2. The dynamic semiconductor memory device according to claim 1, wherein the VPR applying means (16, 17) gradually lowers the precharge level (VPR) in a data holding state where writing or reading is not performed. 2. The VPR applying means (16, 17) comprises:
2. The precharge level (VPR) is changed at the same rate as the decrease of the potential of the capacitive element (C) of the memory cell in which the high potential side of the logic data is written.
5. A dynamic semiconductor memory device described in. 3. The VPR applying means (16, 17) comprises:
A dummy cell having a configuration and discharge characteristics similar to that of the memory cell, and a voltage divider circuit that divides the output potential of the dummy cell into about 1/2 are provided, and the dummy cell is provided to the dummy cell each time the refresh operation is performed on the memory cell. 3. The dynamic semiconductor memory device according to claim 2, wherein a potential corresponding to one of logical data is written. 4. The VPR applying means (16, 17) comprises:
A voltage holding unit that lowers the holding potential at a predetermined speed; and a normal VPR generation circuit that applies the maximum value of the precharge level (VPR) to the voltage holding unit every refresh operation on the memory cell, 2. The dynamic semiconductor memory device according to claim 1, wherein the output of the voltage holding means is the precharge level (VPR).