JPH0991884A - Digital modulation method, demodulation method, and digital modulation device and demodulation device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To limit the error propagation to be short at the time of demodulation while reducing losses of memory capacity and to reproduce data at a low error rate, by arranging a state reset bit to reset an internal state of a modulation/ demodulation circuit under operation to a specified state during record- formatting. SOLUTION: A state reset bit(SRB) addition block 30 is provided in a data recording system which records information in record medium 5, being connected with a record modulation block 2 and a format encoded block 3, and SRB is added into channel bit string at a specified position in the record format of the data, and the channel bit pattern is composed so that the length of SRB becomes short enough compared with a synchronized byte. Thus, by reducing the loss of the memory capacity and limiting the error propagation to be short at the time of demodulation, a digital modulation and demodulation method and a device which enable the data to be reproduced at a low error rate are provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital modulation method and a digital modulation / demodulation device,
For example, data is recorded in a recording device such as an optical disc device,
Alternatively, the present invention relates to a digital modulation method, a demodulation method, a digital modulation device, and a demodulation device used when reproducing.

[0002]

2. Description of the Related Art FIG. 11 is a block diagram showing an entire conventional data recording system. In the figure, the information is the content to be recorded on the medium. The error correction coding block 1 is a block to which an error correction code is added in order to detect and correct an error during data reproduction. Recording modulation block 2
Is a block for converting an error-correction-coded data bit string into a bit string that facilitates high density recording on a recording medium, that is, a channel bit string. The format encode block 3 is a block that adds a sync pattern or the like for enabling sync detection at the time of reproduction to the data pattern converted into the channel bit in the recording modulation block 2 and encodes it according to the recording format. The recording amplifier and the recording head 4 are blocks that write recording marks on the recording medium 5 in accordance with a bit string input according to the recording format.

FIG. 12 is a block diagram showing an entire conventional data reproducing system. In the figure, the signal on the recording medium 5 is detected and read by the reproducing head and the reproducing amplifier block 6. The signal read out as a digital channel bit string is input to the format decoding block 7. The format decoding block 7 detects the synchronization signal included in the channel bit string, decodes the recording format, and generates timing for demodulating data. The recording demodulation block 8 starts demodulation of the input channel bit string at the timing according to the synchronization signal from the format decoding block 7, and reproduces the data bit string. The error decoding block 9 detects and corrects the error contained in the data bit string using the error correction code applied at the time of recording.

FIG. 13 is a block diagram showing the internal structure of the recording modulation block 2. The data bits are converted into channel bits in 1-byte units according to the modulation conversion rule table 21. The converted channel bit is once synchronized with the byte clock by the channel bit latch 22 and then output. At this time, there is a recording modulation method with a high recording density in which a plurality of modulation conversion tables are switched for each byte for modulation conversion. Which table is used to convert each byte is determined by the internal state display bit held in the internal state latch 23 inside the modulation circuit. The internal state defining the table to be used for the next conversion is defined by the rules incorporated in the modulation conversion table, which is the internal state latch 23 as the next internal state.
Sent to

When the conversion of 1 byte is completed, internal state latch 23 latches the channel bit by channel bit latch 22 and, at the same time, stores the next internal state in internal state latch 23. Further, the internal state latch 23 is reset to the initial state by the frame synchronization signal received from the format encode block 3 when the recording frame is delimited. Therefore, at least at the frame head position, the internal state is initialized and the conversion rule table used for modulation conversion is also reset to the specified table.

FIG. 14 is a block diagram showing the internal structure of the recording / demodulating block 8. The channel bits are converted into data bits in 1-byte units according to the demodulation conversion rule table 81. The converted data bit is once synchronized with the byte clock by the data bit latch 82 and then output. At this time, as described with reference to FIG. 13, there is a recording modulation method with a high recording density in which a plurality of modulation conversion tables are switched for each byte for modulation conversion. To demodulate a signal modulated by such a modulation method, it is necessary to switch the table used for conversion for each byte.

The demodulation conversion table used for demodulating the current byte is determined by the internal state display bit held in the internal state latch 83 inside the demodulation circuit. The internal state defining the table to be used for the next demodulation conversion is defined by the rules incorporated in the demodulation conversion table, and it is sent to the internal state latch 83 as the next internal state. When the conversion of 1 byte is completed, the internal state latch 83 latches the data bit by the data bit latch 82 and, at the same time, stores the next internal state in the internal state latch 83.
Further, the internal state latch 83 is reset to the initial state by the frame synchronization signal received from the format decode block 7 when the recording frame breaks. Therefore, at least at the frame head position, the internal state is initialized and the conversion rule table used for modulation conversion is also reset to the prescribed table.

FIG. 15 shows an example of the modulation conversion rule table. In this example, four types of conversion rule tables 211, 212, 213, and 214 are used when performing modulation. According to the rules of the table, the data bit is converted into the channel bit, and at the same time, the internal status indication bit is updated. The table used for the current modulation conversion is selected and designated by the modulation conversion rule table selector 215 in response to the current internal state indication bit.

FIG. 16 shows an example of the demodulation conversion rule table. In this example, the signal modulated by the method described in FIG. 15 is demodulated. At this time, four types of conversion rule tables 811, 812, 813, 814 are used. According to the rules of the table, the channel bit is converted into the data bit and the internal status indication bit is updated at the same time. The table used for the current demodulation conversion is selected and designated by the demodulation conversion rule table selector 815 in response to the current internal state indication bit.

17 and 18 show examples of conversion tables used for modulation conversion and demodulation conversion. FIG. 17 shows Table-1 and Table-2, and FIG. 18 shows Table-
3 and Table-4 are shown. For conversion, one of these four tables is used. First, a table reference method at the time of modulation conversion will be described. The internal state of the modulation circuit is 4
There are four states that use each of the types of tables.
When the current internal state is 1, Table-1 is used to convert data bits to channel bits. The conversion is the operation of only extracting the channel bit corresponding to the data bit in the table. At the same time, the next internal state is given.

[0011] For example, the data is "00" in order from the beginning.
"000011", "00000011", "00000
Let us consider a case where they are connected in series such as "001", "00000001", .... Initial state is "1"
Since it has been reset to, the table -1 in FIG.
"00000011" to "0010000"
00001001 ". At the same time, "2" is obtained as the next internal state. Next, using the table-2 of FIG. 17, "00000011" is changed to "0100010010".
000000 ". At the same time, "4" is obtained as the next internal state. Next, "00000001" is changed to "1000000100" using Table-4 in FIG.
100,000 ". At the same time, "3" is obtained as the next internal state. Further next is the table of FIG.
"3000000" to "1000000"
100100,000 ". At the same time, "3" is obtained as the next internal state. Similarly, the table will be referred to for conversion. In this way, the modulation conversion is an operation of converting the data bit string into the channel bit string using the modulation conversion table corresponding to the current internal state for each byte, and at the same time determining the next internal state.

Next, a table reference method at the time of demodulation conversion will be described. As the internal state of the demodulation circuit, there are four states using each of the four types of tables. When the current internal state is 1, table-1 is used to perform conversion from channel bits to data bits contrary to the case of modulation. The conversion is an operation of only extracting the data bit corresponding to the channel bit in the table. At the same time, the next internal state is given.

Consider, for example, the case of demodulating in the reverse of the above example. Channel bits are "00100" from the beginning.
"0000100001", "01000100100
"00000", "1000000100100000
"0", "1000000100100000" ...
Consider the case where they are connected like. Since the internal state has been reset to "1" which is the initial state, first, using Table-1 in FIG. 17, "00100000000010" is used.
01 "is converted into" 00000011 ". At the same time, "2" is obtained as the next internal state. Next, using Table-2 in FIG. 17, "010001001000000
0 "is converted into" 00000011 ". At the same time, "4" is obtained as the next internal state. Next, using Table-4 in FIG. 18, "1000000100100000"
Convert "0" to "00000001". At the same time, "3" is obtained as the next internal state. Furthermore, next to FIG.
Table-3 of "100000010010"
Convert "0000" to "00000001". At the same time, "3" is obtained as the next internal state. Similarly, the table will be referred to for conversion.

As described above, the demodulation conversion is an operation of converting a data bit string into a channel bit string using the demodulation conversion table corresponding to the current internal state for each byte and determining the next internal state at the same time. In this example, the same table can be used for the modulation conversion and the demodulation conversion, but the operation is the same when another table is used.

FIG. 19 is a diagram showing a data recording format. The error correction coded data byte sequence is (1,1), (1,2), (1,3), (1,4),
..., (1,15), (1,16), (2,1),
(2,2), (2,3), (2,4), ...
(2,15), (2,16), (3,1), ...
... (20,15), (20,1)
It is input to the recording modulation block in the order of 6). Figure 1
In the recording format shown in FIG. 9, the matrix is configured with 16 rows and 20 columns, the 1st byte to 12th byte of each column are used as information, and the 13th byte to 16th byte are used as error correction codes.

It is assumed that a Reed-Solomon code is used as the error correction code. This Reed-Solomon code adds 4 bytes of parity bytes to 12 bytes of information. Since the minimum distance is 5, errors up to 2 bytes can be corrected. In addition, a synchronization byte for recovering from bit synchronization loss is arranged at the beginning of each column constituting the frame of the error correction code. The sync byte is added by the format encoder after recording and modulation. The data bytes are modulated, record-formatted, and then recorded in the order of the bytes described above on a recording medium such as a disc. The recording format is not limited to the one shown here. An example is shown here for the sake of explanation.

Now, when reproducing information from a recording medium recorded in such a recording format, an error occurs due to scratches, defects, dust or the like of the medium. FIG. 20 shows an example of error occurrence. The x mark is the byte in which the error occurred. As a recording modulation method, when using the modulation method that switches according to the content of the preceding data bit string as the modulation conversion rule for converting the data bit string to the channel bit string as described above, an error occurs during demodulation. If it is demodulated by mistake, not only that byte will be erroneous, but also the next internal state will be erroneously specified, so the next byte will be demodulated by the wrong demodulation conversion table and the next byte will also be erroneous. The error propagation of, occurs. When such an error that the next internal state is erroneous occurs, there is a problem that the error propagation cannot be interrupted until the internal byte is reset by reaching the sync byte at the beginning of the frame. The black triangle mark in FIG. 20 indicates an error caused by error propagation.

As a method for avoiding such a problem, there is also a method of inserting a synchronization byte not only at the beginning of the frame but also in the middle and resetting the internal state once at the portion of the synchronization byte. This means that a plurality of sync bytes at the beginning of the frame are also placed in the frame. By doing so, it is possible to prevent error propagation due to propagation of an error in the internal state.

However, the synchronization byte has a long function because it has a function of resetting the internal state after having a function of synchronization recovery including recovery from bit slip. If a plurality of frames are arranged in a frame, the degree of redundancy will increase and a large loss will occur in the recording capacity. In order to recover the synchronization from the state where the bit synchronization is lost, it is necessary to assign a unique bit pattern that does not appear in the channel bits of the data portion only in the synchronization pattern portion. This is because it is unavoidable. In the example shown in FIGS. 19 and 20, the length of one synchronization byte is 2 bytes of data.

FIG. 21 shows an example in which a sync byte is added to the recording format shown in FIG. Although the error propagation at this time is limited as shown in FIG. 22, the ratio of the synchronization bytes in the number of recording bytes is increased and the data recording capacity is reduced. In this example, the coding efficiency in the format of FIG. 19 in which no error propagation countermeasure is taken, that is, the ratio of data bytes to the total number of bytes is 320 bytes out of 360 bytes, that is,
While 88.9%, when adding a synchronization byte every 4 bytes, the coding efficiency is 3 out of 480 bytes.
20 bytes, that is, 66.7%. It turns out that adding synchronization bytes to prevent error propagation is a very inefficient way. The number of data bytes at this time includes an error correction code.

[0021]

Since the conventional digital modulation method is configured as described above, when an error occurs during demodulation of a channel bit string, error propagation occurs and an error occurs until the next synchronization information. There is a problem that there is a high possibility that the will not recover and continue. Therefore, prevention of error propagation becomes an issue.

Further, if a synchronization byte is inserted in a frame in order to avoid such a problem of error propagation, there is a problem that redundancy is increased and a large loss is caused in recording capacity. Therefore, it is an issue to obtain an efficient method for preventing error propagation.

The present invention has been made in order to solve the above-mentioned problems, and while reducing the loss of the recording capacity, the error propagation at the time of demodulation is limited to a short time, and the data reproduction with a low error rate becomes possible. It is an object of the present invention to obtain a digital modulation / demodulation method and a digital modulation / demodulation device.

[0024]

[Means for Solving the Problems] During the recording format,
A state reset bit for resetting the internal state of the modulator circuit and the demodulator circuit during operation to a prescribed state is arranged. Then, the channel bit pattern is configured such that the length of the state reset bit is sufficiently shorter than the synchronization byte.

Further, the cycle of adding the status reset bit to the data byte string is related to the correction capability of the error correction code used in this format, and is not too large compared with the correctable error length. , For example, set within 3 times the correctable error length.

An apparatus for reproducing data from a recording medium in which a status reset bit is arranged in the recording format is
In addition to a plurality of demodulation conversion tables, a means for detecting the status reset bit arranged in the recording format and a demodulation conversion table used by the demodulation means when the status reset bit is detected are reset to a prescribed initial state. And means.

In the modulator, a modulation circuit for switching the modulation conversion rule used when converting a data bit string into a channel bit string according to the contents of the preceding data bit string, and an internal state of the modulation circuit at a predetermined interval are set. A state reset bit addition circuit for periodically adding a state reset bit to reset to a prescribed state.

Further, the period for adding the status reset bit is set to be not more than 3 times the error length correctable by the error correction code.

A plurality of demodulation conversion circuits for converting a channel bit string into a reproduced data bit string, a circuit for detecting a status reset bit periodically added in the channel bit string, and the demodulation conversion circuit when the status reset bit is detected. And a state reset circuit for resetting the conversion in the circuit to a state in which a specified conversion circuit is used.

[0030]

BEST MODE FOR CARRYING OUT THE INVENTION A digital modulation method, a demodulation method, and a digital modulation apparatus, which are embodiments of the present invention,
In the demodulator, a status reset bit is placed in the recording format to reset the internal status during operation of the modulator and demodulator to the specified status, and the length of this status reset bit is set to the synchronization byte. The channel bit pattern is configured so that it has a sufficiently short length.

Embodiment 1. FIG. 1 is a block diagram showing the configuration of the entire data recording system of the present invention. In the figure, an error correction block 1, a recording modulation block 2, a format encoding block 3, a recording amplifier, a recording head 4, and a recording medium 5 are the same blocks as those described in FIG. In the present invention, as shown in FIG. 1, a state reset bit addition block 30 is provided and connected to the format encode block 3. It has the function of adding a status reset bit to the channel bit string at a specified position on the data recording format.

FIG. 3 shows a specific example in which a status reset bit is added in the data recording format. A state reset bit is arranged in the data recording format of FIG. 19 described as a conventional example. The error propagation at this time is limited to be short as shown in FIG. FIG. 21 of the above-mentioned conventional example shows an arrangement of sync bytes in the data recording format of FIG. The arrangement of the status reset bytes in FIG. 3 is the same as the arrangement of the synchronization bytes in FIG. 22, and has the same error propagation blocking ability with respect to the error propagation blocking. However, in the conventional example of FIG.
While the length of the synchronization byte inserted in the frame was 2 bytes of data, in the embodiment shown here,
The length of the status reset bit can be 0.25 bytes of data. Specific bit patterns will be described later.

While the coding efficiency in the format of FIG. 19 in which no error propagation countermeasure is taken, that is, the ratio of data bytes to the total number of bytes is 320 bytes out of 360 bytes, that is, 88.9%, In the example shown here, when the status reset bit is added every 4 bytes, the coding efficiency is 320 bytes out of 375 bytes, that is, 85.3%. The reduction rate of the recording capacity is (1- (85.3 / 88.9)) = 4%.
Although it has the same ability to prevent error propagation as the addition of the synchronization byte, it can be seen that this is a very efficient method with little loss in recording capacity. Note that the number of data bytes at this time includes an error correction code as in the conventional example.

FIG. 5 shows the recording modulation circuit block 2 and
3 is a block diagram showing an internal configuration of a state reset bit addition block 30. FIG. The data bits are converted into channel bits in 1-byte units according to the modulation conversion rule table 21, and the converted channel bits are once synchronized with the byte clock by the channel bit latch 22 and then output, as shown in FIG. Is the same as. At this time, a point of performing modulation conversion by switching a plurality of modulation conversion tables for each byte in a recording modulation method with a high recording density, and which table is used for conversion of each byte is held in an internal state latch 23 inside the modulation circuit. The same applies to the determination by the internal status display bit. The internal state defining the table to be used for the next conversion is defined by the rules incorporated in the modulation conversion table, which is sent to the internal state latch 23 as the next internal state.

When the conversion of one byte is completed, the internal state latch 23 latches the channel bit by the channel bit latch 22 and, at the same time, stores the next internal state in the internal state latch 23. Further, the internal state latch 23 is reset to the initial state by the frame synchronization signal received from the format encode block 3 when the recording frame is delimited.

In the present invention, the OR circuit 31 is configured to sum the frame synchronization signal and the status reset timing signal to reset the internal status latch 23. Therefore, in addition to the frame start position, the status reset bit is also included in the format. When the timing to add is received, a state reset timing signal is received from the format encoder to reset the internal state latch 23 to the initial state. At this time, the conversion rule table used for the modulation conversion of the next byte is reset to the prescribed table.

When the state reset timing signal is received,
A state reset bit is inserted into the channel bit string of the channel bit latch output by the state reset bit adding circuit 32. The bit to be inserted here is selected so as to satisfy the run length constraint of the modulation method at the boundary between the channel bit string of the preceding data and the channel bit string of the subsequent data.

Embodiment 2 FIG. 2 is a block diagram showing the configuration of the entire data reproducing system of the present invention. In the figure, a recording medium 5, a reproducing head, and a reproducing amplifier block 6,
The format decoding block 7, the recording demodulation circuit 8 and the error decoding block 9 are the same blocks as those described in FIG. In the present invention, as shown in FIG. 2, a state reset bit removing block 70 is provided and connected to the format decoding block 8. Detects and removes the status reset bit inserted in the channel bit string at the specified position on the data recording format, and resets the internal state of the demodulation conversion circuit at the time of subsequent data byte demodulation to the specified initial state. Have a function.

FIG. 6 is a block diagram showing the internal construction of the recording demodulation block 8 and the state reset bit removal block 70. The channel bits are converted into data bits in 1-byte units according to the demodulation conversion rule table 81, and the converted data bits are transferred to the data bit latch 8
It is the same as in FIG. 14 of the conventional example that it is output after being synchronized with the byte clock by 2. At this time,
As described with reference to FIG. 14, modulation conversion is performed by switching a plurality of modulation conversion tables for each byte in a recording modulation method having a high recording density, and conversion for each byte is performed to demodulate a signal modulated by such a modulation method. The same applies to switching the table used for.

The demodulation conversion table used for demodulating the current byte is determined by the internal state display bit held in the internal state latch 83 inside the demodulation circuit. The internal state defining the table to be used for the next demodulation conversion is defined by the rules incorporated in the demodulation conversion table, and it is sent to the internal state latch 83 as the next internal state. When the conversion of 1 byte is completed, the internal state latch 83 latches the data bit by the data bit latch 82 and, at the same time, stores the next internal state in the internal state latch 83.
Further, the internal state latch 83 is reset to the initial state by the frame synchronization signal received from the format decode block 7 when the recording frame breaks.

In the present invention, the OR circuit 71 is configured to add the frame synchronization signal and the status reset timing signal to reset the internal status latch 83. Therefore, in addition to the frame head position, the status reset bit is also added in the format. When the time comes to remove the state reset timing signal from the format decoder, the internal state latch 83 is reset to the initial state. At this time, the conversion rule table used for the demodulation conversion of the next byte is reset to the prescribed table.

When the state reset timing signal arrives, the state reset bits are removed from the input channel bit string of the demodulation conversion rule table 81 by the state reset bit removing circuit 72. Only the channel bit string in which the data is modulated is input. The demodulation conversion rule as in the conventional example can be applied.

Embodiment 3 An example in which an appropriate bit pattern is specifically obtained as the state reset bit will be shown. First, the presupposed modulation method is given as follows. The conversion table used for the modulation conversion is a modulation conversion method using the same four types of tables as shown in FIGS. 17 and 18. This is a method of converting 8-bit data into 16 channel bits. Here, the initial state at the time of resetting the state at the beginning of the frame is set to "1", and in this state, Table-1 is used. In each table, 256 data patterns and the corresponding channel bit patterns are defined.

In the modulation method used here, the characteristic of the channel bit pattern used in each table is defined by the length of consecutive bits "0" at the beginning and the end, that is,
When represented by 0-run length, the following method is assumed. This is shown in FIG. The channel bit pattern used in the table-1 selected in the state "1" has 2 to 9 consecutive "0" s in the head portion. The channel bit pattern used in the table-2 selected in the state "2" has 1 to 5 consecutive "0" s in the head portion. State "3"
The channel bit pattern used in Table-3 selected in step 1 has 0 to 5 consecutive "0" s at the beginning. Table-4 selected in state "4"
The channel bit pattern used in the above has 0 or 1 continuous "0" at the beginning.

Further, the 0-run length at the end of each channel bit pattern of any table is 0 to 9, but the 0-run length at the end determines the next internal state. When the 0-run length at the end is 0 or 1, the next internal state is set to "1". When the last part 0-run length is 2 to 5, the next internal state is set to "2" or "3". When the 0-run length at the end is 6 to 9, the next internal state is set to "4". With the above definition, the 0-run length of the channel bit string at the byte boundary can be restricted to 2 to 10.

FIG. 8 shows a method of adding a state reset bit without changing the 0-run length condition of the internal state and the byte boundary portion and the state transition condition defined as described above. Here, the state is reset to "1" immediately after the state reset bit, and the length of the state reset bit is 4 channel bits. At this time, the following conditions are given. Case 1: When the next internal state defined by the data byte preceding the state reset bit is "1", the state reset bit is set to "0010". Case 2.3.4: The next internal state defined by the data byte preceding the state reset bit is "2", "3",
When it is "4", the state reset bit is set to "1001".

In this way, the 0-run length at the boundary between the preceding byte and the status reset bit is 1 in case.
2 or 3, 2 to 5 in case 2 and 3 and 6 to 9 in case 4. Further, the 0-run length of the boundary portion between the status reset bit and the succeeding byte is 3 to 10 in the case 1 and 2 to 9 in the case 2 · 3 · 4. In this way, the 0-run length of the channel bit string at the byte boundary portion can be restricted to 2 to 10.

Embodiment 4 FIG. 9 shows an example of a recording format to which the status reset bit of the present invention is applied. 1
Inner parity and outer parity are added to the information data of 70 bytes × 200 rows as shown in the figure to perform error correction coding by a product code. A 2-byte length synchronization byte is added to the data thus generated at a ratio of 1 to 90 bytes, and a total of 92 bytes form one frame. The order of recording on the recording medium is to record the lower data in order from left to right on the top line of the figure, then from left to right on the second line, and so on. As a modulation method capable of high-density recording on a recording medium, a modulation method for switching the modulation conversion rule to be used according to the content of the preceding data bit string is applied to the recording method of such a format as a high-density recording method. In this case, as described above, the disadvantage that a 1-bit error propagates to the end of the frame appears.

In order to prevent this error propagation, the state reset bit described in the third embodiment is applied in the example shown in FIG. The 90-byte data and the parity are divided into 9 pieces of 10 bytes each, and each of the 4 state reset bits is inserted in the boundary portion at 8 positions.
This allows error propagation to be limited to a maximum of 10 bytes and an average of 5 bytes.

In this example, a Reed-Solomon code is used as the inner parity error correction code. This Reed-Solomon code adds 10 bytes of parity bytes to 170 bytes of information. Since the minimum distance is 11, errors of up to 5 bytes can be corrected. Therefore, by limiting the error propagation to an average of 5 bytes, it becomes possible to prevent half of the random errors that occur from being corrected by the inner parity.

The average error propagation length can be shortened by inserting more status reset bits, but this causes a slight decrease in recording capacity, which is a design trade-off. If you look at it slightly, and if the cycle for inserting the status reset bit is set to 3 times or less of the error length that can be corrected by the error correction code, the error propagation at the time of demodulation is limited shortly while suppressing the decrease in recording capacity slightly. The average error rate can be kept low.

In this example, the capacity decrease due to the state reset bit insertion is inversely proportional to the increase of the frame length, so that (1- (92/94)) = 2.1%.

[0053]

Since the present invention is constructed as described above, it has the following effects.

It becomes possible to limit the error propagation at the time of demodulation to be short and to keep the average error rate low.

It is possible to slightly suppress the decrease in recording capacity due to the addition of the redundant pattern.

The circuit structure for limiting the error propagation at the time of demodulation to be short is simple and costs little.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an entire data recording system of the present invention.

FIG. 2 is a diagram showing a configuration of an entire data reproducing system of the present invention.

FIG. 3 is a diagram showing an example of a data recording format of the present invention.

FIG. 4 is a diagram showing error propagation in an example of a data recording format of the present invention.

FIG. 5 is a diagram showing a block configuration of a modulation circuit of the present invention.

FIG. 6 is a diagram showing a block configuration of a demodulation circuit of the present invention.

FIG. 7 is a diagram showing an example of channel bit patterns of a modulation system to which the present invention is applied.

FIG. 8 is a diagram showing an example of a status reset bit of the present invention.

FIG. 9 is a diagram showing an example of a data recording format to which the present invention is applied.

FIG. 10 is a diagram showing an example of a data recording format to which the present invention is applied.

FIG. 11 is a diagram showing a conventional example of the configuration of the entire data recording system.

FIG. 12 is a diagram showing a conventional example of the configuration of the entire data reproducing system.

FIG. 13 is a diagram showing a conventional example of a block configuration of a modulation circuit.

FIG. 14 is a diagram showing a conventional example of a block configuration of a demodulation circuit.

FIG. 15 is a diagram showing the structure of a modulation conversion rule table.

FIG. 16 is a diagram showing the structure of a demodulation conversion rule table.

FIG. 17 is a diagram showing an example of a modulation conversion table.

FIG. 18 is a diagram showing an example of a modulation conversion table.

FIG. 19 is a diagram showing a block configuration of a modulation circuit of the present invention.

FIG. 20 is a diagram showing a block configuration of a demodulation circuit of the present invention.

FIG. 21 is a diagram showing a conventional example of a data recording format.

FIG. 22 is a diagram showing error propagation in a conventional example of a data recording format.

[Explanation of symbols]

1 error correction coding block, 2 recording modulation block,
3 format encode block, 4 recording amplifier and recording head block, 5 recording medium, 6 reproducing head and reproducing amplifier block, 7 format decoding block, 8 recording demodulating block, 9 error decoding block, 21 modulation conversion rule table, 22 channel bits Latch, 23 Internal state latch, 30 State reset bit addition block, 31 Logical sum circuit, 32 State reset bit addition circuit, 70 State reset bit removal block, 71 Logical sum circuit, 72 State reset bit removal circuit, 81 Demodulation conversion rule table , 82
Data bit latch, 83 internal state latch, 211
Conversion rule table, 212 conversion rule table, 213
Conversion rule table, 214 conversion rule table, 21
5 modulation conversion rule table selector, 811 conversion rule table, 812 conversion rule table, 813 conversion rule table, 814 conversion rule table, 815 demodulation conversion rule table selector.

Claims (5)

[Claims] 1. A digital modulation method for converting an error correction coded data bit string into a channel bit string to be recorded on a recording medium, wherein a modulation conversion rule used when converting the data bit string into a channel bit string is preceded. In the modulation method for switching according to the contents of the data bit string, a state reset bit for resetting the modulation conversion rule to a prescribed state is periodically added to the channel bit string. 2. The digital modulation method according to claim 1, wherein the period for adding the state reset bit is set to be three times or less than an error length correctable by the error correction code. Digital modulation method. 3. A digital demodulation method for reading the information converted into a channel bit string and recorded on a recording medium by the digital modulation method according to claim 1 and reproducing the data, wherein a plurality of demodulation conversions are performed. A channel bit string is converted into a reproduction data bit string by a rule, a state reset bit periodically added in the channel bit string is detected, and when the state reset bit is detected, a conversion rule in the demodulation conversion is used as a rule that defines a conversion rule. A digital demodulation method characterized by resetting to a state in which it is activated. 4. A digital modulator for converting an error correction coded data bit string into a channel bit string to be recorded on a recording medium, wherein a modulation conversion rule used when converting the data bit string into the channel bit string is preceded. In a digital modulator for switching according to the contents of a data bit string, a state reset bit adding circuit for periodically adding a state reset bit for resetting a modulation conversion rule to a prescribed state is provided in a channel bit string, A digital modulation device characterized in that a cycle for adding a reset bit is 3 times or less of an error length correctable by the error correction code. 5. A digital demodulation device for reading the information converted into a channel bit string and recorded on a recording medium by the digital modulator according to claim 4 and reproducing the data, wherein the channel bit string is reproduced. A plurality of demodulation conversion circuits for converting into a data bit string, a circuit for detecting a status reset bit periodically added in a channel bit string, and a conversion for defining a conversion in the demodulation conversion circuit when the status reset bit is detected And a state reset circuit for resetting the circuit to a state of using the digital demodulator.